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JPS5743256A - Memory which capable of making parallel access - Google Patents

Memory which capable of making parallel access

Info

Publication number
JPS5743256A
JPS5743256A JP11862680A JP11862680A JPS5743256A JP S5743256 A JPS5743256 A JP S5743256A JP 11862680 A JP11862680 A JP 11862680A JP 11862680 A JP11862680 A JP 11862680A JP S5743256 A JPS5743256 A JP S5743256A
Authority
JP
Japan
Prior art keywords
memory
accessed
bus
parallel
memory modules
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11862680A
Other languages
Japanese (ja)
Inventor
Hidehiko Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11862680A priority Critical patent/JPS5743256A/en
Publication of JPS5743256A publication Critical patent/JPS5743256A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To contrive improvement of using efficiencies of memories, by connecting a plural number of memory modules to a plural group of memory buses, selecting a plural group of memory buses in parallel, and then, by making an arrangement so that a plural number of memory modules are accessed in parallel. CONSTITUTION:Even when a memory module 00 connected to a memory bus l0 is being accessed, any one out of the other three memory modules 01, 02, and 03 connected to the same bus l0 can be accessed at the same time through another bus l1. Then, when a memory request comes when a memory module 02 among a memory group 0 is accessed through the bus l0 and another memory module 10 is accessed through a bus l3 in parallel with the memory module 02, the request is accepted if there are addresses which correspond to the remaining six memory modules. By making an arrangement so that a plural number of memory modules may make accesses at the same time as mentioned above, parallel accesses can be performed against a wide range addresses.
JP11862680A 1980-08-28 1980-08-28 Memory which capable of making parallel access Pending JPS5743256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11862680A JPS5743256A (en) 1980-08-28 1980-08-28 Memory which capable of making parallel access

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11862680A JPS5743256A (en) 1980-08-28 1980-08-28 Memory which capable of making parallel access

Publications (1)

Publication Number Publication Date
JPS5743256A true JPS5743256A (en) 1982-03-11

Family

ID=14741181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11862680A Pending JPS5743256A (en) 1980-08-28 1980-08-28 Memory which capable of making parallel access

Country Status (1)

Country Link
JP (1) JPS5743256A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60217443A (en) * 1984-04-12 1985-10-31 Nec Corp Storage control system
JPS6220042A (en) * 1985-07-19 1987-01-28 Fujitsu Ltd Memory access port controller
JPS6254350A (en) * 1985-01-24 1987-03-10 Nec Corp Switching device
JPS6292054A (en) * 1985-10-18 1987-04-27 Usac Electronics Ind Co Ltd Dynamic access memory device
JPH01197864A (en) * 1988-02-02 1989-08-09 Pfu Ltd Bus window control system
US5293489A (en) * 1985-01-24 1994-03-08 Nec Corporation Circuit arrangement capable of centralizing control of a switching network

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60217443A (en) * 1984-04-12 1985-10-31 Nec Corp Storage control system
JPH0368420B2 (en) * 1984-04-12 1991-10-28 Nippon Electric Co
JPS6254350A (en) * 1985-01-24 1987-03-10 Nec Corp Switching device
JPH0510693B2 (en) * 1985-01-24 1993-02-10 Nippon Electric Co
US5293489A (en) * 1985-01-24 1994-03-08 Nec Corporation Circuit arrangement capable of centralizing control of a switching network
JPS6220042A (en) * 1985-07-19 1987-01-28 Fujitsu Ltd Memory access port controller
JPH0412857B2 (en) * 1985-07-19 1992-03-05 Fujitsu Ltd
JPS6292054A (en) * 1985-10-18 1987-04-27 Usac Electronics Ind Co Ltd Dynamic access memory device
JPH01197864A (en) * 1988-02-02 1989-08-09 Pfu Ltd Bus window control system

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