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JPS5679324A - Memory access system - Google Patents

Memory access system

Info

Publication number
JPS5679324A
JPS5679324A JP15545779A JP15545779A JPS5679324A JP S5679324 A JPS5679324 A JP S5679324A JP 15545779 A JP15545779 A JP 15545779A JP 15545779 A JP15545779 A JP 15545779A JP S5679324 A JPS5679324 A JP S5679324A
Authority
JP
Japan
Prior art keywords
access
memory access
data channel
priority
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15545779A
Other languages
Japanese (ja)
Inventor
Naotoshi Ukai
Haruo Wakabayashi
Ryoji Miwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP15545779A priority Critical patent/JPS5679324A/en
Publication of JPS5679324A publication Critical patent/JPS5679324A/en
Pending legal-status Critical Current

Links

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  • Bus Control (AREA)

Abstract

PURPOSE: To secure memory access from a data channel device with lower priority by preventing the right to access from being given to one device continuously for a long period, by providing a method of controlling the memory access in a data channel device with higher priority.
CONSTITUTION: Between one memory 1 and data channel devices, memory access priority determining circuit 2 is connected and in the data channel device with high priority, memory access request signal generator 6, access cycle monitoring circuit 7 and access cycle control circuit 8 are provided. When the high priority of memory access is given by determining circuit 2, a channel device short in memory repetitive cycle operates and the operation state of the data channel after the end of the processing time of the memory access is compared with that of the other channel device; according to the comparison result, the next memory access is controlled to prevent the right to access from being given to one device for a long period, thereby securing access from the low-priority device.
COPYRIGHT: (C)1981,JPO&Japio
JP15545779A 1979-11-30 1979-11-30 Memory access system Pending JPS5679324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15545779A JPS5679324A (en) 1979-11-30 1979-11-30 Memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15545779A JPS5679324A (en) 1979-11-30 1979-11-30 Memory access system

Publications (1)

Publication Number Publication Date
JPS5679324A true JPS5679324A (en) 1981-06-29

Family

ID=15606456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15545779A Pending JPS5679324A (en) 1979-11-30 1979-11-30 Memory access system

Country Status (1)

Country Link
JP (1) JPS5679324A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003131937A (en) * 2001-08-31 2003-05-09 Koninkl Philips Electronics Nv Dynamic access control for handling grouped resources

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003131937A (en) * 2001-08-31 2003-05-09 Koninkl Philips Electronics Nv Dynamic access control for handling grouped resources

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