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JPS5617583A - Television picture receiver - Google Patents

Television picture receiver

Info

Publication number
JPS5617583A
JPS5617583A JP9305079A JP9305079A JPS5617583A JP S5617583 A JPS5617583 A JP S5617583A JP 9305079 A JP9305079 A JP 9305079A JP 9305079 A JP9305079 A JP 9305079A JP S5617583 A JPS5617583 A JP S5617583A
Authority
JP
Japan
Prior art keywords
signal
display
clock pulse
circuit
size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9305079A
Other languages
Japanese (ja)
Inventor
Tatsuo Kawasaki
Masahiro Kurihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9305079A priority Critical patent/JPS5617583A/en
Publication of JPS5617583A publication Critical patent/JPS5617583A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45—Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To ensure a display with a balanced size between the sight of the remote controller and the screen, by securing the magnification and reduction for the channel display which is given in piling on the picture image. CONSTITUTION:The horizontal synchronous signal is applied through terminal 3 and then divided through horizontal synchronous variable dividing circuit 10; and the vertical synchronous signal is applied through terminal 4 and then supplied to timing signal generating circuit 6. The clock pulse which is used to decide the minimum size in the horizontal direction is applied from clock pulse generator 5 with a fixed frequency and then divided by variable dividing circuit 9 to be supplied to circuit 6. Then the parallel signal of the display pattern generated from pattern generating circuit 2 is converted by the timing signal into the serial signal which synchronizes with the horizontal synchronous signal and the clock pulse each. The size of the display varies by the change of the division ratio.
JP9305079A 1979-07-20 1979-07-20 Television picture receiver Pending JPS5617583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9305079A JPS5617583A (en) 1979-07-20 1979-07-20 Television picture receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9305079A JPS5617583A (en) 1979-07-20 1979-07-20 Television picture receiver

Publications (1)

Publication Number Publication Date
JPS5617583A true JPS5617583A (en) 1981-02-19

Family

ID=14071672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9305079A Pending JPS5617583A (en) 1979-07-20 1979-07-20 Television picture receiver

Country Status (1)

Country Link
JP (1) JPS5617583A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991780A (en) * 1982-11-17 1984-05-26 Matsushita Electronics Corp Integrated circuit device for display
EP0261893A2 (en) * 1986-09-20 1988-03-30 Sony Corporation Picture-in-picture television receivers
JPS6442667U (en) * 1987-09-10 1989-03-14

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991780A (en) * 1982-11-17 1984-05-26 Matsushita Electronics Corp Integrated circuit device for display
EP0261893A2 (en) * 1986-09-20 1988-03-30 Sony Corporation Picture-in-picture television receivers
JPS6442667U (en) * 1987-09-10 1989-03-14

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