JPS55117781A - High-speed address converter - Google Patents
High-speed address converterInfo
- Publication number
- JPS55117781A JPS55117781A JP2528179A JP2528179A JPS55117781A JP S55117781 A JPS55117781 A JP S55117781A JP 2528179 A JP2528179 A JP 2528179A JP 2528179 A JP2528179 A JP 2528179A JP S55117781 A JPS55117781 A JP S55117781A
- Authority
- JP
- Japan
- Prior art keywords
- address
- size
- segment
- unit
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To reduce the capacity of the address conversion buffer of an information processing system, by giving effect to registration by changing the size of a segment.
CONSTITUTION: Once virtual address 100 is set in virtual address unit 200, address conversion buffer 103 is referred to by the entirety or part of segment number 100a. When there is not an address conversion couple to be found in buffer 103, address boundary selecting method 202 selects an address conversion couple from address boundary unit 201. Segment size 10lb read out from a main memory unit is set in unit 201 and then compared 203 with address 100b in a segment in unit 200. In case of a large segment, when there are an address size 101b assigns and that address 100b assigns in the same 64k byte boundary area, sixteen low-order bits of size 101b are registered in size part 103c of buffer 103.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2528179A JPS55117781A (en) | 1979-03-05 | 1979-03-05 | High-speed address converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2528179A JPS55117781A (en) | 1979-03-05 | 1979-03-05 | High-speed address converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55117781A true JPS55117781A (en) | 1980-09-10 |
JPS6137655B2 JPS6137655B2 (en) | 1986-08-25 |
Family
ID=12161632
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2528179A Granted JPS55117781A (en) | 1979-03-05 | 1979-03-05 | High-speed address converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55117781A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59124077A (en) * | 1982-12-28 | 1984-07-18 | フランス国 | Memory management system for processor or microprocessor |
JPS62237547A (en) * | 1986-04-09 | 1987-10-17 | Hitachi Ltd | Address conversion system |
-
1979
- 1979-03-05 JP JP2528179A patent/JPS55117781A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59124077A (en) * | 1982-12-28 | 1984-07-18 | フランス国 | Memory management system for processor or microprocessor |
JPS62237547A (en) * | 1986-04-09 | 1987-10-17 | Hitachi Ltd | Address conversion system |
JPH0552540B2 (en) * | 1986-04-09 | 1993-08-05 | Hitachi Ltd |
Also Published As
Publication number | Publication date |
---|---|
JPS6137655B2 (en) | 1986-08-25 |
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