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JPH1117202A - Solar cell device - Google Patents

Solar cell device

Info

Publication number
JPH1117202A
JPH1117202A JP9170150A JP17015097A JPH1117202A JP H1117202 A JPH1117202 A JP H1117202A JP 9170150 A JP9170150 A JP 9170150A JP 17015097 A JP17015097 A JP 17015097A JP H1117202 A JPH1117202 A JP H1117202A
Authority
JP
Japan
Prior art keywords
silicon substrate
solar cell
conductivity type
cell element
semiconductor impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9170150A
Other languages
Japanese (ja)
Other versions
JP3377931B2 (en
Inventor
Yosuke Inomata
洋介 猪股
Kenji Fukui
健次 福井
Katsuhiko Shirasawa
勝彦 白沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP17015097A priority Critical patent/JP3377931B2/en
Publication of JPH1117202A publication Critical patent/JPH1117202A/en
Application granted granted Critical
Publication of JP3377931B2 publication Critical patent/JP3377931B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/546Polycrystalline silicon PV cells

Landscapes

  • Weting (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce surface reflection factor and improve short-circuit current value by providing a number of fine protrusions with specific values of height and the width on the front surface of a silicon substrate and implanting a semiconductor impurity of opposite conductivity type of so as to have a specific value of sheet resistance on the front surface of the silicon substrate. SOLUTION: A reflection reducing coating 2 is formed on the front surface of a silicon surface 1 and then a front electrode 3 is formed thereon. A number of fine protrusions 1c are also formed on the surface of the silicon substrate 1. The height and the width of the fine protrusions are formed 2 μm or below, respectively. By providing fine protrusions, light which irradiates the front surface of the silicon substrate 1 is made to multiple-reflect, and the surface reflection is decreased. A semiconductor impurity of the opposite conductivity type is implanted so as to exhibit a sheet resistance of 60 to 300 Ω/(square) for the front surface. A layer 1b and a rear electrode 4 are formed on the rear surface of the silicon substrate 1, the layer 1b being heavily diffused with a semiconductor impurity of one conductivity type.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は太陽電池素子に関
し、特にシリコン基板を用いた太陽電池素子に関する。
The present invention relates to a solar cell device, and more particularly to a solar cell device using a silicon substrate.

【0002】[0002]

【従来の技術及び発明が解決しようとする課題】通常、
多結晶シリコン基板を用いて太陽電池素子を形成する場
合、まず基板表面の切断面を清浄化するために15μm
程度エッチングする。例えば濃度15%程度の水酸化ナ
トリウム水溶液を80℃に保持してエッチングを行う
と、約7分で15μm程度エッチングできる。また、基
板表面での反射率をより低減するために、薄い濃度のア
ルカリ水溶液でエッチングする。例えば濃度が5%程度
の水酸化ナトリウム水溶液を75℃に保持してエッチン
グを行うと、表面に微細な凹凸が形成され、基板表面で
の反射率をある程度低減することができる。
BACKGROUND OF THE INVENTION Generally,
When forming a solar cell element using a polycrystalline silicon substrate, first, a 15 μm
Etch to the extent. For example, when etching is performed while an aqueous solution of sodium hydroxide having a concentration of about 15% is maintained at 80 ° C., the etching can be performed at about 15 μm in about 7 minutes. Further, in order to further reduce the reflectance on the substrate surface, the etching is performed with an alkaline aqueous solution having a low concentration. For example, when etching is performed while maintaining an aqueous solution of sodium hydroxide having a concentration of about 5% at 75 ° C., fine irregularities are formed on the surface, and the reflectance on the substrate surface can be reduced to some extent.

【0003】ところが、面方位が(100)面の単結晶
シリコン基板を用いた場合は、このような方法でテクス
チャー構造と呼ばれるピラミッド構造を基板表面に均一
に形成することができるものの、多結晶シリコン基板で
太陽電池素子を形成する場合、アルカリ水溶液によるエ
ッチングは結晶の面方位に依存することから、ピラミッ
ド構造を均一には形成できず、そのため全体の反射率も
効果的には低減できないという問題があった。基板表面
での反射率を効果的に低減できなければ、太陽電池素子
の特性も効果的には向上させることができない。
However, when a single crystal silicon substrate having a (100) plane orientation is used, a pyramid structure called a texture structure can be uniformly formed on the substrate surface by such a method. When a solar cell element is formed on a substrate, the problem that the pyramid structure cannot be formed uniformly because etching with an alkaline aqueous solution depends on the plane orientation of the crystal, and therefore the overall reflectance cannot be reduced effectively. there were. If the reflectance on the substrate surface cannot be effectively reduced, the characteristics of the solar cell element cannot be effectively improved.

【0004】このような問題を解決するために、多結晶
シリコン基板で太陽電池素子を形成する場合に、反応性
イオンエッチング(Reactive Ion Etching:RIE)法で基
板表面に微細な突起を形成することが提案されている
(例えば特公昭60−27195号、特開平5−751
52号、特開平9−102625号公報参照)。この方
法によると、多結晶シリコンにおける不規則な結晶の面
方位に左右されることなく、微細な突起を均一に形成す
ることができ、特に多結晶シリコンを用いた太陽電池素
子においては、より効果的に反射率を低減することがで
きるようになる。
In order to solve such a problem, when a solar cell element is formed on a polycrystalline silicon substrate, fine projections are formed on the substrate surface by a reactive ion etching (RIE) method. (For example, JP-B-60-27195, JP-A-5-751).
No. 52, JP-A-9-102625). According to this method, fine projections can be uniformly formed without being affected by the plane orientation of irregular crystals in the polycrystalline silicon. Particularly, in a solar cell element using polycrystalline silicon, the effect is more effective. The reflectivity can be effectively reduced.

【0005】ところが、基板表面に微細な突起を形成し
て太陽電池素子を形成した場合、基板表面での反射率が
大きく低減するにも拘らず、短絡電流値がそれほど向上
しないという問題あり、さらに改善が望まれていた。
However, when a solar cell element is formed by forming fine projections on the substrate surface, there is a problem that the short-circuit current value does not improve so much, although the reflectivity on the substrate surface is greatly reduced. Improvement was desired.

【0006】本発明はこのような従来技術に鑑みてなさ
れたものであり、表面反射率は低減できてもそれに見合
った短絡電流値の向上が得られないという従来技術の問
題点を解消した太陽電池素子を提供することを目的とす
る。
The present invention has been made in view of such prior art, and has solved the problem of the prior art in that the surface reflectivity can be reduced but the short-circuit current value cannot be improved correspondingly. An object is to provide a battery element.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係る太陽電池素子では、一導電型半導体不
純物を含有するシリコン基板の表面側に逆導電型半導体
不純物を含有させると共に、このシリコン基板の表面側
と裏面側に電極を形成した太陽電池素子において、前記
シリコン基板の表面側に幅と高さがそれぞれ2μm以下
の微細な突起を多数設け、このシリコン基板の表面側の
シート抵抗が60〜300Ω/□となるように前記逆導
電型半導体不純物を含有させる。
Means for Solving the Problems In order to achieve the above object, in a solar cell element according to the present invention, a silicon substrate containing a semiconductor impurity of one conductivity type contains a semiconductor impurity of an opposite conductivity type on the surface side thereof. In a solar cell element having electrodes formed on the front side and the back side of the silicon substrate, a large number of fine projections each having a width and a height of 2 μm or less are provided on the front side of the silicon substrate, and a sheet on the front side of the silicon substrate is provided. The reverse conductivity type semiconductor impurity is contained so that the resistance is 60 to 300 Ω / □.

【0008】また、本発明に係る太陽電池素子では、前
記微細な突起のアスペクト比が0.1〜2であることが
望ましい。
Further, in the solar cell element according to the present invention, it is preferable that the aspect ratio of the fine projection is 0.1 to 2.

【0009】さらに、本発明に係る太陽電池素子では、
単結晶シリコン基板や多結晶シリコン基板のいずれでも
用いることができるが、多結晶シリコン基板を用いた場
合に特に効果的である。
Further, in the solar cell element according to the present invention,
Although any of a single crystal silicon substrate and a polycrystalline silicon substrate can be used, it is particularly effective when a polycrystalline silicon substrate is used.

【0010】[0010]

【発明の実施の形態】以下、本発明を添付図面に基づき
詳細に説明する。図1は、本発明に係る太陽電池素子の
一実施形態を示す断面図である。図1において、1はシ
リコン基板、2は反射防止膜、3は表面電極、4は裏面
電極である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing one embodiment of a solar cell element according to the present invention. In FIG. 1, 1 is a silicon substrate, 2 is an antireflection film, 3 is a front electrode, and 4 is a back electrode.

【0011】前記シリコン基板1は、単結晶シリコン基
板又は多結晶シリコン基板などから成る。このシリコン
基板1は、一導電型半導体不純物を1×1016atom
/cm3 程度含有し、比抵抗1.5Ωcm程度の基板で
ある。このシリコン基板1は、p型、n型のいずれでも
よい。単結晶シリコンの場合は引き上げ法などによって
形成され、多結晶シリコンの場合は鋳造法などによって
形成される。多結晶シリコンは、大量生産が可能で製造
コスト面で単結晶シリコンよりも極めて有利である。引
き上げ法や鋳造法によって形成されたインゴットを30
0μm程度の厚みにスライスして、10cm×10cm
もしくは15cm×15cm程度の大きさに切断してシ
リコン基板となる。
The silicon substrate 1 is composed of a single crystal silicon substrate or a polycrystalline silicon substrate. This silicon substrate 1 contains 1 × 10 16 atoms of one conductivity type semiconductor impurity.
/ Cm 3 and a specific resistance of about 1.5 Ωcm. This silicon substrate 1 may be either p-type or n-type. In the case of single crystal silicon, it is formed by a pulling method or the like, and in the case of polycrystalline silicon, it is formed by a casting method or the like. Polycrystalline silicon can be mass-produced and is extremely advantageous over single crystal silicon in terms of manufacturing cost. 30 ingots formed by pulling or casting
Slice to a thickness of about 0μm, 10cm x 10cm
Alternatively, the silicon substrate is cut into a size of about 15 cm × 15 cm.

【0012】シリコン基板1の表面側には、逆導電型半
導体不純物が拡散された層1aが形成されている。この
逆導電型半導体不純物が拡散された層1aは、シリコン
基板1内に半導体接合部を形成するために設けるものあ
り、例えばn型の不純物を拡散させる場合、POCl3
を用いた気相拡散法、P2 5 を用いた塗布拡散法、及
びP+ イオンを直接拡散させるイオン打ち込み法などに
よって形成される。この逆導電型半導体不純物を含有す
る層1は、0.3〜0.5μm程度の深さに形成され
る。
On the surface side of silicon substrate 1, a layer 1a in which a semiconductor impurity of the opposite conductivity type is diffused is formed. The layer 1a in which the opposite conductivity type semiconductor impurity is diffused is provided for forming a semiconductor junction in the silicon substrate 1. For example, when an n-type impurity is diffused, POCl 3 is used.
, A coating diffusion method using P 2 O 5 , and an ion implantation method for directly diffusing P + ions. The layer 1 containing the opposite conductivity type semiconductor impurity is formed at a depth of about 0.3 to 0.5 μm.

【0013】このシリコン基板1の表面側には、反射防
止膜2が形成されている。この反射防止膜2は、シリコ
ン基板1の表面で光が反射するのを防止して、シリコン
基板1内に光を有効に取り込むために設ける。この反射
防止膜は、シリコン基板1との屈折率差などを考慮し
て、屈折率が2程度の材料で構成され、厚み500〜2
000Å程度の窒化シリコン(SiNx )膜や酸化シリ
コン(SiO2 )膜などで構成される。
An antireflection film 2 is formed on the surface of the silicon substrate 1. The antireflection film 2 is provided to prevent light from being reflected on the surface of the silicon substrate 1 and to effectively take in light into the silicon substrate 1. This antireflection film is made of a material having a refractive index of about 2 in consideration of a refractive index difference from the silicon substrate 1 and the like, and has a thickness of 500 to 2
It is composed of a silicon nitride (SiN x ) film or a silicon oxide (SiO 2 ) film of about 000 °.

【0014】シリコン基板1の裏面側には、一導電型半
導体不純物が高濃度に拡散された層1bを形成すること
が望ましい。この一導電型半導体不純物が高濃度に拡散
された層1bは、シリコン基板1の裏面近くでキャリア
の再結合による効率の低下を防ぐために、シリコン基板
1の裏面側に内部電界を形成するものである。つまり、
シリコン基板1の裏面近くで発生したキャリアがこの電
界によって加速される結果、電力が有効に取り出される
こととなり、特に長波長の光感度が増大すると共に、高
温における太陽電池特性の低下を軽減できる。このよう
に一導電型半導体不純物が高濃度に拡散された層1bが
形成されたシリコン基板1の裏面側のシート抵抗は、1
5Ω/□程度になる。
It is desirable to form a layer 1b in which a semiconductor impurity of one conductivity type is diffused at a high concentration on the back side of the silicon substrate 1. The layer 1b in which the one-conductivity-type semiconductor impurity is diffused at a high concentration forms an internal electric field on the back surface side of the silicon substrate 1 in order to prevent a decrease in efficiency due to carrier recombination near the back surface of the silicon substrate 1. is there. That is,
As a result of the carriers generated near the back surface of the silicon substrate 1 being accelerated by this electric field, power is effectively extracted, and in particular, the long-wavelength photosensitivity is increased and the deterioration of solar cell characteristics at high temperatures can be reduced. As described above, the sheet resistance on the back surface side of the silicon substrate 1 on which the layer 1b in which the one conductivity type semiconductor impurity is diffused at a high concentration is formed is 1
It becomes about 5Ω / □.

【0015】シリコン基板1の表面側には、表面電極3
が形成されている。この表面電極3は、銀(Ag)と銅
(Cu)の二層構造のものなどから成る。この表面電極
3は、例えば幅80μm程度に、またピッチ1.6mm
程度に形成される多数のフィンガー電極と、この多数の
フィンガー電極を相互に接続する2本のバスバー電極で
構成される。この表面電極3の表面部には、複数の太陽
電池素子同志をリード線で接続するための半田層などが
被着形成される。
A surface electrode 3 is provided on the front side of the silicon substrate 1.
Are formed. The surface electrode 3 has a two-layer structure of silver (Ag) and copper (Cu). The surface electrode 3 has, for example, a width of about 80 μm and a pitch of 1.6 mm.
It is composed of a large number of finger electrodes formed to a certain extent and two bus bar electrodes interconnecting the large number of finger electrodes. A solder layer or the like for connecting a plurality of solar cell elements with lead wires is formed on the surface of the front electrode 3.

【0016】シリコン基板1の裏面側には、裏面電極4
が形成されている。この裏面電極4も、銀(Ag)と銅
(Cu)の二層構造のものなどから成り、さらに半田層
が被着形成される。
On the back side of the silicon substrate 1, a back electrode 4
Are formed. The back electrode 4 also has a two-layer structure of silver (Ag) and copper (Cu), and further has a solder layer formed thereon.

【0017】本発明に係る太陽電池素子では、シリコン
基板1の表面側に微細な突起1cが多数形成されてい
る。この微細な突起1cは、シリコン基板1の表面側に
照射される光を多重反射させて、表面反射を減少させる
ために設ける。この微細な突起1cは、円錐形もしくは
それが連なったような形状を呈し、RIE法によるガス
濃度若しくはエッチング時間を制御することにより、そ
の大きさを変化させることができる。この微細な突起1
cの幅と高さはがそれぞれ2μm以下に形成される。こ
の突起1cの幅と高さが2μm以上になると、エッチン
グの処理時間が長くなる反面、基板1表面での反射率は
さほど低減されない。この微細な突起1cをシリコン基
板1の表面側の全面にわたって均一且つ正確に制御性を
もたせて形成するためには、1μm以下が好適である。
また、この微細な突起は極めて微小なものでも反射率低
減の効果はあるが、面内に均一かつ正確に形成するため
には、製造工程上1nm以上であることが望まれる。
In the solar cell element according to the present invention, a large number of fine projections 1c are formed on the surface side of the silicon substrate 1. The fine projections 1c are provided to reduce the surface reflection by multiple-reflecting the light applied to the surface side of the silicon substrate 1. The fine projection 1c has a conical shape or a shape like a series of conical shapes, and its size can be changed by controlling the gas concentration or the etching time by the RIE method. This fine projection 1
The width and height of c are each formed to be 2 μm or less. When the width and height of the projections 1c are 2 μm or more, the processing time for etching is prolonged, but the reflectance on the surface of the substrate 1 is not so reduced. In order to form the fine projections 1c uniformly and accurately with controllability over the entire surface of the silicon substrate 1, the thickness is preferably 1 μm or less.
Even if the minute projections are extremely small, they have the effect of reducing the reflectance. However, in order to form them uniformly and accurately in a plane, it is desirable that the thickness be 1 nm or more in the manufacturing process.

【0018】この微細な突起1cのアスペクト比(突起
1cの幅/高さ)は、0.1〜2であることが望まし
い。このアスペクト比が0.1以下の場合は、例えば波
長500〜1000nmの光の平均反射率が25%程度
であり、基板1表面での反射率が大きくなる。また、こ
のアスペクト比が2以上の場合、製造過程で微細な突起
1cが破損し、太陽電池素子を形成した場合にリーク電
流が多くなって良好な出力特性が得られない。
It is desirable that the aspect ratio (width / height of the protrusion 1c) of the fine protrusion 1c is 0.1 to 2. When the aspect ratio is 0.1 or less, for example, the average reflectance of light having a wavelength of 500 to 1000 nm is about 25%, and the reflectance on the surface of the substrate 1 increases. Further, when the aspect ratio is 2 or more, the fine projections 1c are damaged in the manufacturing process, and when a solar cell element is formed, a leak current increases and good output characteristics cannot be obtained.

【0019】本発明に係る太陽電池素子では、微細な突
起1cが多数形成されたシリコン基板1の表面部のシー
ト抵抗を60〜300Ω/□とする。この値は四探針法
により測定される値である。すなわち、シリコン基板1
の表面に一直線上に並んだ4本の金属針を加圧しながら
接触させ、外側の2本の針に電流を流したときに、内側
の2本の針の間に発生した電圧を測定し、この電圧と流
した電流からオームの法則によって抵抗値を求める。こ
のように微細な突起1cが多数形成されたシリコン基板
1の表面部のシート抵抗を60〜300Ω/□とする
と、太陽電池を形成たときの短絡電流を大幅に増大させ
ることができる。すなわち、シリコン基板1の表面に上
述のような微細な突起1cを形成する場合、このような
微細な突起1cを形成しない場合に比較して、逆導電型
半導体不純物がシリコン基板1の表面側に拡散されやす
くなり、逆導電型半導体不純物が深く且つ大量に拡散さ
れる。したがって、半導体接合部がシリコン基板1の表
面から離れた深いところに形成され、この半導体接合部
に光が到達しにくくなって短絡電流が向上しないものと
考えられる。そこで、本発明では、シリコン基板1の表
面に微細な突起1cを多数形成した場合に、シリコン基
板1の表面部のシート抵抗値を従来品よりも高くなるよ
うに設定して、半導体接合部がシリコン基板1の比較的
浅いところで形成されるようにして短絡電流値の向上を
図る。15cm×15cmの太陽電池素子では、基板表
面のシート抵抗値が60Ω/□以下の場合、後述するよ
うに短絡電流Iscは7.6Aしか得られないが、シリ
コン基板1表面部のシート抵抗が60Ω/□以上になる
と、短絡電流Iscも7.9A以上になり、短絡電流値
が急激に向上する。なお、このウェハ表面のシート抵抗
値が、300Ω/以上になると、基板1の表面側の全面
にわたって逆導電型半導体不純物を均一に拡散させるこ
とが困難になって不適である。
In the solar cell element according to the present invention, the sheet resistance of the surface portion of the silicon substrate 1 on which many fine projections 1c are formed is set to 60 to 300 Ω / □. This value is a value measured by the four probe method. That is, the silicon substrate 1
Four metal needles lined up in a straight line are brought into contact with the surface while pressing, and when a current is applied to the two outer needles, the voltage generated between the two inner needles is measured. The resistance value is obtained from this voltage and the flowing current according to Ohm's law. When the sheet resistance of the surface portion of the silicon substrate 1 on which many fine protrusions 1c are formed is set to 60 to 300Ω / □, the short-circuit current when forming a solar cell can be greatly increased. That is, when the fine projections 1c as described above are formed on the surface of the silicon substrate 1, the opposite conductivity type semiconductor impurities are deposited on the surface side of the silicon substrate 1 as compared with the case where such fine projections 1c are not formed. It becomes easy to diffuse, and the opposite conductivity type semiconductor impurity is diffused deeply and in large quantities. Therefore, it is considered that the semiconductor junction is formed at a deep place away from the surface of the silicon substrate 1, and it is difficult for light to reach the semiconductor junction and the short-circuit current is not improved. Therefore, in the present invention, when a large number of fine protrusions 1c are formed on the surface of the silicon substrate 1, the sheet resistance value of the surface portion of the silicon substrate 1 is set to be higher than that of the conventional product, and the semiconductor bonding portion is formed. The short-circuit current value is improved by being formed at a relatively shallow portion of the silicon substrate 1. In the case of a 15 cm × 15 cm solar cell element, when the sheet resistance value of the substrate surface is 60Ω / □ or less, a short-circuit current Isc of only 7.6 A can be obtained as described later, but the sheet resistance of the silicon substrate 1 surface portion is 60Ω. When the value is // or more, the short-circuit current Isc also becomes 7.9 A or more, and the short-circuit current value sharply increases. If the sheet resistance value of the wafer surface is 300 Ω / or more, it is difficult to uniformly diffuse the opposite conductivity type semiconductor impurity over the entire surface of the substrate 1, which is not suitable.

【0020】次に、本発明に係る太陽電池素子の製造方
法を図2に基づいて詳細に説明する。まず、一導電型半
導体不純物を含有するシリコン基板1を用意する。この
シリコン基板1は、インゴットから所定寸法に切り出さ
れたものである(同図(a)参照)。
Next, a method for manufacturing a solar cell element according to the present invention will be described in detail with reference to FIG. First, a silicon substrate 1 containing a semiconductor impurity of one conductivity type is prepared. The silicon substrate 1 is cut out from an ingot into a predetermined size (see FIG. 1A).

【0021】このシリコン基板1の表面部のスライスダ
メージを除去するために、HNO3:HF=7:1の水
溶液に浸漬して、15μm程度エッチングした後、RI
E法で微細な突起1cを多数形成する。このRIE法で
は、例えば三フッ化メタン(CHF3 )を12.0sc
cm程度、塩素(Cl2 )を72sccm程度、酸素
(O2 )を9sccm程度、および六フッ化硫黄(SF
6 )を65sccm程度流しながら、反応圧力50mT
orr程度、プラズマをかけるRFパワー500W程度
で、10秒〜15分間程度行う。
In order to remove slice damage on the surface of the silicon substrate 1, the silicon substrate 1 is immersed in an aqueous solution of HNO 3 : HF = 7: 1, etched about 15 μm, and then subjected to RI
Many fine projections 1c are formed by the E method. In this RIE method, for example, 12.0 sc of methane trifluoride (CHF 3 )
cm, about 72 sccm of chlorine (Cl 2 ), about 9 sccm of oxygen (O 2 ), and sulfur hexafluoride (SF).
6 ) The reaction pressure is 50 mT while
This is performed for about 10 seconds to 15 minutes at about RF power of about 500 W or about orr.

【0022】次に、シリコン基板1の表面部に逆導電型
半導体不純物を気相成長法、塗布拡散法、或いはイオン
打ち込み法などで拡散して逆導電型半導体不純物を含有
する層1aを形成すると共に、この層1aが基板1の表
面側のみに残るように、他の部分をエッチング除去する
(同図(c)参照)。
Next, a layer 1a containing the opposite conductivity type semiconductor impurity is formed on the surface portion of the silicon substrate 1 by diffusing the opposite conductivity type semiconductor impurity by a vapor phase growth method, a coating diffusion method, an ion implantation method, or the like. At the same time, other portions are removed by etching so that this layer 1a remains only on the front surface side of the substrate 1 (see FIG. 3C).

【0023】次に、シリコン基板1の裏面側に例えばア
ルミニウム(Al)などを主成分とする金属ペーストを
塗布して焼き付けることにより、シリコン基板1の裏面
側に一導電型半導体不純物を多量に拡散させた層1bを
形成する(同図(d)参照)。
Next, a metal paste containing, for example, aluminum (Al) as a main component is applied and baked on the back surface of the silicon substrate 1 to diffuse a large amount of one-conductivity-type semiconductor impurities on the back surface of the silicon substrate 1. The formed layer 1b is formed (see FIG. 4D).

【0024】次に、シリコン基板1の表面側に例えば窒
化シリコン膜などから成る反射防止膜2をプラズマCV
D法などで厚み500〜2000Å程度の厚みに形成す
る(同図(e)参照)。
Next, an anti-reflection film 2 made of, for example, a silicon nitride film is formed on the surface side of the silicon substrate 1 by plasma CV.
It is formed to a thickness of about 500 to 2000 mm by a method D or the like (see FIG. 3E).

【0025】最後に、シリコン基板1の表裏両面に銀
(Ag)をスパッタリングして蒸着し、銅(Cu)をメ
ッキし、フィンガー電極バスバー電極を形成した後、半
田ディップ法で半田をコーティングした表面電極3 裏面
電極4を形成して完成する(図1参照)。
Finally, silver (Ag) is sputter-deposited on both the front and back surfaces of the silicon substrate 1, copper (Cu) is plated, finger electrodes and bus bar electrodes are formed, and then the surface coated with solder by a solder dip method Electrode 3 The back electrode 4 is formed and completed (see FIG. 1).

【0026】[0026]

【実施例】厚みが300μmで、比抵抗が1.5Ωcm
の15cm×15cm角の多結晶シリコンから成る基板
をHNO3 :HF=7:1の溶液に浸漬して、片面15
μmエッチングした後、三フッ化メタン(CHF3 )を
12sccm、塩素(Cl2 )を72sccm、酸素
(O2 )を9sccm、および六フッ化硫黄(SF6
を65sccm流しながら、反応圧力50mTorr、
RFパワー500WでRIE法により基板表面に微細な
突起を形成した。次に、シリコン基板の表面部のシート
抵抗が40Ω/□、50Ω/□、60Ω/□、70Ω/
□、80Ω/□、90Ω/□、100Ω/□、120Ω
/□となるようにリン(P)を拡散した。次に、シリコ
ン基板の裏面側にアルミニウム(Al)ペーストをスク
リーン印刷して750℃の温度で焼成した。このシリコ
ン基板の裏面側のシート抵抗は15Ω/□であった。シ
リコン基板の表面側に、屈折率2.1、膜厚800Åの
SiN膜をプラズマCVD法で形成して反射防止膜とし
た。シリコン基板の表裏両面にスパッタリング法で銀
(Ag)を蒸着し、銅(Cu)メッキを行って、幅80
μm、ピッチ1.6mmのフィンガー電極と、幅2mm
のバスバー電極を2本形成し、半田ディップ法で電極表
面に半田層を形成して太陽電池素子を形成した。
[Example] The thickness is 300 μm and the specific resistance is 1.5 Ωcm.
Of 15 cm × 15 cm square polycrystalline silicon is immersed in a solution of HNO 3 : HF = 7: 1 to form
After the μm etching, 12 sccm of methane trifluoride (CHF 3 ), 72 sccm of chlorine (Cl 2 ), 9 sccm of oxygen (O 2 ), and sulfur hexafluoride (SF 6 )
While the reaction pressure is 50 mTorr,
Fine projections were formed on the substrate surface by RIE at an RF power of 500 W. Next, the sheet resistance of the surface portion of the silicon substrate is 40Ω / □, 50Ω / □, 60Ω / □, 70Ω / □.
□, 80Ω / □, 90Ω / □, 100Ω / □, 120Ω
Phosphorus (P) was diffused so as to be / □. Next, an aluminum (Al) paste was screen-printed on the back surface side of the silicon substrate and fired at a temperature of 750 ° C. The sheet resistance on the back side of this silicon substrate was 15Ω / □. An SiN film having a refractive index of 2.1 and a film thickness of 800 ° was formed on the surface side of the silicon substrate by a plasma CVD method to form an antireflection film. Silver (Ag) is vapor-deposited on both sides of the silicon substrate by a sputtering method, copper (Cu) plating is performed, and a width of 80
μm, 1.6 mm pitch finger electrode and 2 mm width
Were formed, and a solder layer was formed on the electrode surface by a solder dipping method to form a solar cell element.

【0027】それぞれの試料について、短絡電流Isc
を図った。その結果を図3の黒菱印の線で示す。なお、
図3中の黒四角の線(B)はRIE法によって微細な突
起を形成する代わりに、濃度15%の水酸化ナトリウム
(NaOH)の水溶液を用いて85℃で7分間エッチン
グした従来の太陽電池素子の短絡電流値である。
For each sample, the short-circuit current Isc
Was planned. The results are shown by the black diamond line in FIG. In addition,
A black square line (B) in FIG. 3 is a conventional solar cell etched at 85 ° C. for 7 minutes using an aqueous solution of sodium hydroxide (NaOH) having a concentration of 15% instead of forming fine projections by the RIE method. This is the short-circuit current value of the element.

【0028】図3から明らかなように、微細な突起を形
成しない従来の太陽電池素子では、シリコン基板の表面
部のシート抵抗が50Ω/□のときの短絡電流が7.5
1Aで、60Ω/□のときの短絡電流が7.60Aであ
ったのに対して、RIE法で微細な突起を形成した太陽
電池素子では、基板表面のシート抵抗が50Ω/□のと
きの短絡電流が7.62Aで、微細な突起を形成しない
太陽電池素子とさほど変わらないが、60Ω/□のとき
の短絡電流は7.94Aであり、微細な突起を形成しな
かった太陽電池素子に比較して大きく向上していること
がわかった。さらに、RIEエッチング法で微細な突起
を形成した太陽電池素子では、基板表面のシート抵抗が
70Ω/□、80Ω/□、90Ω/□となるにしたがっ
て短絡電流が大きくなり、従来の太陽電池素子よりもは
るかに大きな短絡電流値が得られることが判明した。
As is apparent from FIG. 3, in the conventional solar cell element having no fine projections, the short-circuit current when the sheet resistance of the surface of the silicon substrate is 50Ω / □ is 7.5.
At 1 A, the short-circuit current at 60 Ω / □ was 7.60 A. On the other hand, in the solar cell element having fine projections formed by the RIE method, the short-circuit current at the sheet resistance of the substrate surface was 50 Ω / □. The current is 7.62 A, which is not much different from a solar cell element that does not form fine projections, but the short-circuit current at 60 Ω / □ is 7.94 A, which is compared to a solar cell element that did not form fine projections. It has been found that it has greatly improved. Further, in a solar cell element having fine projections formed by the RIE etching method, the short-circuit current increases as the sheet resistance of the substrate surface becomes 70Ω / □, 80Ω / □, 90Ω / □. It was also found that a much larger short-circuit current value could be obtained.

【0029】[0029]

【発明の効果】以上のように、本発明に係る太陽電池素
子によれば、シリコン基板の表面側に幅と高さがそれぞ
れ2μm以下の微細な突起を多数設け、このシリコン基
板の表面側のシート抵抗が60〜300Ω/□となるよ
うに、逆導電型半導体不純物を含有させることから、太
陽電池素子の表面側の反射率を極力低減して光を有効に
利用できると共に、光の反射率の低減に相応して短絡電
流値の向上が得られ、高効率な出力が得られる太陽電池
素子となる。特に、面方位が一定でない多結晶シリコン
を用いた太陽電池素子において極めて有効である。
As described above, according to the solar cell element of the present invention, a large number of fine projections each having a width and a height of 2 μm or less are provided on the surface side of the silicon substrate. Since a semiconductor impurity of the opposite conductivity type is contained so that the sheet resistance becomes 60 to 300 Ω / □, the reflectance on the surface side of the solar cell element can be reduced as much as possible, and light can be used effectively, and the reflectance of light can be improved. The short-circuit current value can be improved in accordance with the reduction of the solar cell element, and the solar cell element can obtain a highly efficient output. In particular, it is extremely effective in a solar cell element using polycrystalline silicon having a non-uniform plane orientation.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る太陽電池素子の一実施形態を示す
断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a solar cell element according to the present invention.

【図2】本発明に係る太陽電池素子の製造工程を示す図
である。
FIG. 2 is a view showing a manufacturing process of the solar cell element according to the present invention.

【図3】本発明に係る太陽電池素子の表面部のシート抵
抗と短絡電流との関係を示す図である。
FIG. 3 is a view showing the relationship between the sheet resistance of the surface of the solar cell element according to the present invention and the short-circuit current.

【符号の説明】[Explanation of symbols]

1………シリコン基板、1c………微細な突起、2……
…反射防止膜、3………表面電極、4………裏面電極
1 .... silicon substrate, 1c ... fine protrusion, 2 ....
... Anti-reflective coating, 3 ... Front electrode, 4 ... Back electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 一導電型半導体不純物を含有するシリコ
ン基板の表面側に逆導電型半導体不純物を含有させると
共に、このシリコン基板の表面側と裏面側に電極を形成
した太陽電池素子において、前記シリコン基板の表面側
に幅と高さがそれぞれ2μm以下の微細な突起を多数設
け、このシリコン基板の表面側のシート抵抗が60〜3
00Ω/□となるように前記逆導電型半導体不純物を含
有させたことを特徴とする太陽電池素子。
1. A solar cell element comprising a silicon substrate containing one conductivity type semiconductor impurity and a reverse conductivity type semiconductor impurity on the surface side thereof, and electrodes formed on the front side and the back side of the silicon substrate. A large number of fine projections each having a width and a height of 2 μm or less are provided on the surface side of the substrate, and the sheet resistance on the surface side of the silicon substrate is 60 to 3
A solar cell element comprising the opposite conductivity type semiconductor impurity so as to be 00Ω / □.
【請求項2】 前記微細な突起のアスペクト比が0.1
〜2であることを特徴とする請求項1に記載の太陽電池
素子。
2. The fine projections have an aspect ratio of 0.1.
The solar cell element according to claim 1, wherein
【請求項3】 前記シリコン基板が多結晶シリコン基板
であることを特徴とする請求項1に記載の太陽電池素
子。
3. The solar cell device according to claim 1, wherein said silicon substrate is a polycrystalline silicon substrate.
JP17015097A 1997-06-26 1997-06-26 Solar cell element Expired - Lifetime JP3377931B2 (en)

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Country Status (1)

Country Link
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