JPH11145477A - Thin-film transistor, liquid crystal display device equipped therewith, and manufacture of tft array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device which is high in uniformity of TFT characteristics throughout a display plane and superior in display quality by a method, where TFTs are lessened in ON-state resistance and enhanced in drive capacity. SOLUTION: A gate electrode 2 is formed on a glass substrate 1, a gate insulating film 3, an i layer 4, and an n layer 5 are formed, and the i layer 4 and the n layer 5 are patterned into island forms. Then, a resist is formed on a part of the n layer 5 which is to serve as a TFT channel, and all the n layer 5 other than a part covered with the resist and a part of the i layer are etched. Thereafter, n-type impurities are obliquely implanted to reform an n layer 5 on source/drain contact regions. In this way, the i layer 4 is formed sufficiently thick at the channel and thin under a source/drain electrodes, whereby a channel resistance can be set stable and low, and at the same time a part under the source/drain electrode can be lessened in resistance, so that a TFT is lessened in ON-state resistance and improve in drive capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a thin film transistor, a liquid crystal display device having the same, and a method for manufacturing a TFT array substrate.

[0002]

2. Description of the Related Art A matrix type display device generally includes a switching element including a thin film transistor (TFT), a TFT array substrate having display elements controlled through the switching element, and a counter electrode having a color filter, a black matrix, and the like. A display material such as liquid crystal is sandwiched between substrates, and a voltage is selectively applied to the display material. FIG. 8 is a diagram showing an example of an equivalent circuit of a TFT array substrate in a general liquid crystal display device. In the figure, 10 is a TFT, 11 is an auxiliary capacitor, G
1, G2 and G3 are scanning signal lines, S1, S2 and S3 are video signal lines, and Cs1, Cs2 and Cs3 are Cs for forming auxiliary capacitances.
s wiring is shown. The electrodes of the pixels arranged in a matrix are formed of a transparent electrode such as ITO, and use the TFT 10 as a switching element to control the charge and discharge of the charge to the pixel electrode. The TFT 10 is turned on and off by using the scanning signal line as a gate electrode. The pixel electrode is connected to a video signal line via the TFT 10, and the amount of charge charged to the pixel electrode changes depending on the level of the video signal, and the potential of the pixel electrode is set. The amount of displacement of the liquid crystal changes according to the voltage between the pixel electrode and the counter electrode, and the amount of light transmitted from the back surface changes. Therefore, by controlling the signal level of the video signal line, the optical signal change is controlled and displayed as a video. In order to improve the image quality, it is necessary to minimize the fluctuation of the pixel potential due to a change in the signal level of the scanning signal line or the like. The auxiliary capacitance 11 is provided in the pixel electrode to increase the total capacitance of the pixel. The auxiliary capacitance 11 is formed by providing an insulating film between a Cs wiring having the same potential as the counter electrode and the pixel electrode.

FIG. 9 is a diagram showing a layout example of one pixel on a conventional TFT array substrate. Also,
FIG. 10A is a cross-sectional view when the TFT portion in FIG. 9 is cut in the AA ′ direction. In the drawings, the same and corresponding parts are denoted by the same reference numerals. In the figure, 1 is a glass substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is an ia-Si layer (hereinafter abbreviated as i layer), which is an intrinsic semiconductor layer, and 5 is a semiconductor layer containing n-type impurities. N-a-Si layer (hereinafter abbreviated as n layer), 6 is a pixel electrode, 7 is a drain electrode, 8
Denotes a source electrode, 9 denotes an insulating film, 13 denotes a gate wiring, 14 denotes a source wiring, 15 denotes a Cs wiring, and 16 denotes a semiconductor thin film. The structure and function of a conventional TFT will be described with reference to the drawings. In FIG. 10A, when the pixel electrode 6 is charged with electric charge, a voltage of about 9 V is applied to the source electrode 8 and a positive voltage of about 20 V is applied to the gate electrode 2 to turn on the TFT. , And the drain electrode 7 and the pixel electrode 6 are charged to near 9V. Thereafter, when the potential of the pixel electrode 6 is sufficiently increased, -5 is applied to the gate electrode 2.
A negative voltage of about V is applied to turn off the TFT and confine charges in the pixel. In the above-described series of operations, the degree to which the potential of the pixel electrode 6 increases greatly depends on the size of the capacitor connected to the pixel electrode 6 and the ON resistance of the TFT.

As shown in FIG. 10 (b), the ON resistance of a TFT can be considered by separating a section near a channel of the TFT and separating the TFT into components corresponding to the sectional structure. That is, as the ON resistance, the resistance Rss on the source electrode 8 side is used.
And the resistance Rsc of the channel portion and the resistance R of the drain electrode 7 side.
There is sd. The drain electrode 7 and the source electrode 8 are made of metal, and the resistance of the n-layer 5 provided under each electrode is Rss, Rsc
And Rsd, which is sufficiently small and can be ignored as the ON resistance of the TFT. Therefore, as shown in FIG. 10 (c), the TFT in the state where a voltage is applied to the gate has Rsd on the drain electrode 7 side, Rsc on the channel portion, and the source electrode 8c.
It can be described as an equivalent circuit in which a resistor of Rss is connected to the side.
Therefore, the ON resistance of the TFT depends on the thickness of the i-layer 4 under the source electrode 8 and the drain electrode 7 and the i-th of the channel portion.
It is greatly affected by the thickness of the layer 4. In order to reduce the ON resistance, it is desirable that the thickness of the i-layer below the source / drain electrodes is small and the thickness of the i-layer in the channel portion is large.

Next, a conventional method of manufacturing a TFT array substrate will be described with reference to FIGS. First, a metal thin film such as Cr is formed on a glass substrate 1, and a gate electrode 2 is patterned (FIGS. 11A and 11B). Next, the gate insulating film 3, the i-layer 4, and the n-layer 5 are successively formed, and the i-layer 4 and the n-layer 5 are patterned into an island shape (FIGS. 11C and 11D). Further, a transparent conductive film such as ITO is formed, and the pixel electrode 6 is patterned (FIGS. 11E and 11F).
) Then, a metal thin film of Al, Cr, etc. is formed (FIG. 12).
(g)) After patterning the drain electrode 7 and the source electrode 8, all of the n-layer 5 and the i-layer 4 on the TFT channel portion are etched (back channel etching) (FIG. 12 (h), (i)) Finally, an insulating film 9 is formed (FIG. 12 (j)), and a TFT array substrate is manufactured. In the conventional method of manufacturing a TFT array substrate as described above, since it is necessary to completely remove the n-layer 5 on the channel portions of all TFTs in the substrate surface, usually, the film thickness distribution of the n-layer 5 and the etching In consideration of the distribution, it is necessary to set the etching time to be considerably longer than the time required for completely removing the n-layer 5. Therefore, a part of the i layer 4 in the TFT channel portion is also etched, and the remaining film thickness has a distribution. On the other hand, when the thickness of the i-layer 4 in the channel portion is reduced, the resistance Rsc of the channel portion increases as shown in FIG. Therefore, in the conventional method for manufacturing a TFT array substrate, the thickness of the i-layer 4 needs to be large enough to ensure a sufficient remaining thickness of the i-layer 4 in the channel portion after back channel etching. there were.

[0006]

As described above, in the conventional method for manufacturing a TFT array substrate, the i-layer 4 is formed so that the remaining thickness of the i-layer 4 in the channel portion after the back channel etching can be sufficiently ensured. The i-layer 4 in the channel portion is formed to be thicker than the i-layer 4 under the source electrode 8 and the drain electrode 7.
It was formed thinner than the layer 4. Therefore, a large series resistance R is provided on the source electrode 8 and drain electrode 7 side of the TFT.
Since ss and Rsd are connected, the ON resistance is large, the time required to charge the pixel electrode to a predetermined potential is lengthened, and the driving capability of the TFT and the uniformity of the TFT characteristics on the display surface are low. There was a problem. Further, the resistances Rss and Rsd on the source electrode 8 and the drain electrode 7 side are used.
When the thickness of the i-layer 4 is reduced to reduce the thickness, the thickness of the i-layer 4 in the channel portion is further reduced, so that the resistance Rsc in the channel portion increases, and the ON resistance of the TFT as a whole cannot be reduced. This is because, as the number of display pixels of the liquid crystal display device increases from XGA to SXGA and UXGA, the charging time allocated to one pixel becomes shorter, so that sufficient charging becomes difficult within a predetermined time, and the display quality becomes higher. Was a cause of deterioration.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and reduces the ON resistance of the TFT, improves the driving capability, and achieves high uniformity of the TFT characteristics on the display surface and high display quality. An object is to provide an excellent liquid crystal display device.

[0008]

A thin film transistor according to the present invention is provided with a gate electrode formed on a transparent insulating substrate and an intrinsic film provided on the gate electrode with a gate insulating film interposed therebetween, with a central portion serving as a channel. A semiconductor layer including an n-type impurity provided in a source / drain contact region on the intrinsic semiconductor layer; a source electrode and a drain electrode forming a semiconductor element together with the intrinsic semiconductor layer and the impurity-containing semiconductor layer; The thickness of the intrinsic semiconductor layer below the source / drain electrodes is made equal to or less than the thickness of the intrinsic semiconductor layer in the channel portion. The thickness of the intrinsic semiconductor layer below the source / drain electrodes is at least １ ／ and at most 1 times the thickness of the intrinsic semiconductor layer at the channel portion. Further, a liquid crystal display device according to the present invention includes a TFT array substrate having a switching element including any one of the above-described thin film transistors and a display element controlled via the switching element, and interposing a liquid crystal between the TFT array substrate. And a driving circuit for the switching element.

Further, a method of manufacturing a TFT array substrate according to the present invention includes a first step of forming a metal thin film of Cr or the like on a transparent insulating substrate and pattern-forming a gate electrode line; A second step of continuously forming an intrinsic semiconductor layer and a semiconductor layer containing an n-type impurity through a gate insulating film and patterning the island-shaped pattern;
A third step in which a resist is patterned in a portion serving as a channel of the FT and all of the semiconductor layer containing impurities other than the portion covered with the resist and a part of the intrinsic semiconductor layer are etched.
And rotating the substrate while covering the channel portion with the resist, ion-implanting an n-type impurity from an oblique direction, and reforming a semiconductor layer containing the n-type impurity in the source / drain contact region. Step, a fifth step of forming a metal thin film of Al, Cr, or the like by sputtering or the like, and patterning the source electrode line and the drain electrode, and removing the semiconductor layer containing impurities on the channel by dry etching or the like. The manufacturing method includes a sixth step and a seventh step of forming an insulating film. Further, in the second step, the intrinsic semiconductor layer is formed to have a thickness of about 120 nm, in the third step, the thickness of the intrinsic semiconductor layer other than the channel portion is reduced to about 100 nm, and in the fourth step, the semiconductor layer containing an n-type impurity is formed. Is formed to have a thickness of about 30 nm so that the intrinsic semiconductor layer below the source / drain electrodes has a thickness of about 70 nm.

A first step of forming a metal thin film of Cr or the like on a transparent insulating substrate to form a pattern of gate electrode lines, and forming an intrinsic semiconductor layer on the gate electrode lines via a gate insulating film. A second step of forming a pattern in an island shape, a third step of forming a resist in a portion to be a channel of the TFT, and etching a part of the intrinsic semiconductor layer other than the portion covered with the resist; After removing the resist, a semiconductor layer containing an n-type impurity is formed, and a fourth step of forming a pattern in the shape of an island, a metal thin film of Al, Cr, or the like is formed by a sputtering method or the like. The manufacturing method includes a fifth step of patterning an electrode, a sixth step of removing a semiconductor layer containing impurities on a channel by dry etching or the like, and a seventh step of forming an insulating film. Those were Unishi.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a method for manufacturing a thin film transistor (TFT) according to the first embodiment of the present invention and a TFT array substrate including the same will be described with reference to the drawings. FIG. 1 shows a TFT according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a structure of a TFT section of an array substrate. In the figure, 1 is a glass substrate which is a transparent insulating substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is an ia-Si layer (hereinafter abbreviated as i layer) which is an intrinsic semiconductor layer, and 5 is an n-type. Reference numeral 6 denotes a pixel electrode made of a transparent conductive film, 7 denotes a drain electrode, 8 denotes a source electrode, and 9 denotes an insulating film. The thin film transistor according to the present embodiment is a glass substrate 1
A gate electrode 2 formed thereon, an i-layer 4 provided on the gate electrode 2 with a gate insulating film 3 interposed therebetween, and a central portion serving as a channel, which is an intrinsic semiconductor layer, and a source / drain on the i-layer 4 The semiconductor device includes an n-layer 5, which is a semiconductor layer containing an n-type impurity, provided in a contact region, and a source electrode 8 and a drain electrode 7, which form a semiconductor element together with the i-layer 4 and the n-layer 5. The thickness of the i-layer 4 is equal to or less than the thickness of the i-layer 4 in the channel portion.

A method of manufacturing a TFT array substrate according to the present embodiment will be described with reference to FIGS. In the figure,
Reference numeral 12 denotes a resist. First, a metal thin film such as Cr is formed on a glass substrate 1 (FIG. 2A), and a gate electrode 2 is patterned (FIG. 2B). Next, the gate insulating film 3, i
The layer 4 and the n-layer 5 are successively formed (FIG. 2 (c)), and the i-layer 4 and the n-layer 5 are patterned into islands (FIGS. 2 (d) and (e)). Thereafter, a resist 12 is formed in a pattern on a portion to be a channel of the TFT (FIG. 3F), and all of the n-layer 5 and a part of the i-layer 4 other than the portion covered with the resist 12 are etched to form a channel portion. The other i-layer 4 is thinned (FIG. 3 (g)). In the present embodiment, for example, the initial film thickness of the i-layer 4 is about 120 nm, and the film thickness of the i-layer 4 other than the channel portion after the etching is about 100 nm. Next, the substrate is rotated while the channel portion is covered with the resist 12, ions of an n-type impurity are obliquely implanted (FIG. 3 (h)), and the n-layer 5 is formed again in the source / drain contact region. Thereafter, the resist 12 is removed, and a structure is obtained in which the n-layer 5 under the source electrode 8 and the drain electrode 7 and the n-layer 5 on the channel portion are electrically connected (FIG. 3 (i)). Here, the thickness of the n-layer 5 formed by ion implantation is set to about 30 nm or less, so that the thickness of the i-layer 4 under the source electrode 8 and the drain electrode 7 is set to about 70 nm. The thickness of the i-layer 4 under the source / drain electrodes is the same as that of the i-layer 4 in the channel portion.
It is sufficient that the thickness be equal to or more than の of the film thickness. Next, a transparent conductive film such as ITO is formed by a sputtering method or the like, and the pixel electrode 6 is patterned (FIGS. 4 (j) and 4 (k)).
The drain electrode 7 and the source electrode 8 are formed in a pattern by forming a thin metal film such as the above by a sputtering method or the like (FIG. 4).
(l), (m)). Further, after removing all of the n-layer 5 and a part of the i-layer 4 on the channel portion of the TFT by dry etching or the like, the resist 12 is removed (FIG. 5 (n)). Finally, the insulating film 9 is formed. (FIG. 5 (o)), the TFT array substrate according to the present embodiment is completed.

In the TFT on the TFT array substrate manufactured by the above method, the i-layer 4 in the channel portion is formed sufficiently thick, and the i-layer 4 under the source electrode 8 and the drain electrode 7 is formed thin. , The channel resistance Rsc can be made small and stable, and at the same time, the source electrode 8
Since the resistance Rss in the lower part and the resistance Rsd in the lower part of the drain electrode 7 can be reduced, the ON resistance of the TFT can be reduced, and the driving capability is improved.

Embodiment 2 FIG. In this embodiment, another manufacturing method for manufacturing a TFT array substrate having a cross-sectional structure similar to that of Embodiment 1 will be described. 6 and 7 are diagrams showing a method of manufacturing a TFT array substrate according to the present embodiment. In the drawings, the same or corresponding parts have the same reference characters allotted, and description thereof will not be repeated.

First, a gate electrode 2 is formed on a glass substrate 1 in the same manner as in the first embodiment, and then a gate insulating film 3 and an i-layer 4 are formed (FIG. 6A). Subsequently, the i-layer 4 is patterned into an island shape (FIGS. 6B and 6C).
). After the resist 12 is removed, a pattern of the resist 12 is formed on a portion serving as a channel of the TFT (FIG. 6D), and the i-layer 4 other than the portion covered with the resist 12, i.e., a portion below the source electrode 8 and the drain electrode 7. A part of the layer 4 is etched (FIG. 7E). After the removal of the resist 12, an n-layer 5 is formed (FIG. 7 (f)), and a pattern is formed in an island shape (FIG. 7 (g)). Thus, a structure similar to that of FIG. 3 (i) shown in the first embodiment is obtained. Thereafter, as in the first embodiment, a transparent conductive film such as ITO is formed by a sputtering method or the like, the pixel electrode 6 is patterned, and then a thin metal film of Al or Cr is formed by a sputtering method or the like. Then, a drain electrode 7 and a source electrode 8 are patterned. Further, all n layers 5 on the channel portion of the TFT
Then, a part of the i-layer 4 is removed by dry etching or the like, and finally, an insulating film 9 is formed, thereby completing the TFT array substrate according to the present embodiment. In the TFT of the TFT array substrate manufactured in the present embodiment, the i-layer 4 in the channel portion is sufficiently thick, and the i-layer 4 under the source electrode 8 and the drain electrode 7 is thin, as in the first embodiment. Therefore, the ON resistance of the TFT can be reduced, and the driving capability is improved.

Further, a liquid crystal is interposed between the TFT array substrate having the switching element including the TFT manufactured in the first or second embodiment and the display element controlled via the switching element, and the TFT array substrate. The liquid crystal display device including the opposing electrode substrate to be sandwiched and the driving circuit of the switching element can charge the pixel electrode 6 to a sufficiently high potential within a predetermined time allocated for charging, and display the TFT characteristics. The in-plane uniformity is high and the display quality is excellent.

[0017]

As described above, according to the present invention, the thickness of the intrinsic semiconductor layer below the source / drain electrodes is made equal to or less than the thickness of the intrinsic semiconductor layer in the channel portion. And the resistance under the source electrode and the drain electrode can be reduced, so that the ON resistance of the thin film transistor can be reduced and the driving capability can be improved.

Further, by providing a thin film transistor having a small ON resistance and excellent driving ability, it is possible to obtain a liquid crystal display device having high uniformity of TFT characteristics in a display surface and excellent display quality.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a TFT portion of a TFT array substrate according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a method for manufacturing the TFT array substrate according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a method for manufacturing the TFT array substrate according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a method of manufacturing the TFT array substrate according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a method for manufacturing the TFT array substrate according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a method of manufacturing a TFT array substrate according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a method for manufacturing a TFT array substrate according to a second embodiment of the present invention.

FIG. 8 is a diagram showing an example of an equivalent circuit of a TFT array substrate in a general liquid crystal display device.

FIG. 9 is a diagram showing a layout example of one pixel of a conventional TFT array substrate.

FIG. 10 is a diagram for explaining the relationship between the structure of a TFT portion of a conventional TFT array substrate and ON resistance.

FIG. 11 is a diagram showing a conventional method for manufacturing a TFT array substrate.

FIG. 12 is a diagram showing a conventional method for manufacturing a TFT array substrate.

FIG. 13 is a diagram showing a relationship between a remaining i-layer thickness of a TFT channel portion and a channel resistance Rsc.

[Explanation of symbols]

1 glass substrate, 2 gate electrode, 3 gate insulating film,
4 ia-Si layer (i-layer), 5 na-Si layer (n-layer)
Layer), 6 pixel electrode, 7 drain electrode, 8 source electrode, 9 insulating film, 10 TFT, 11 auxiliary capacitance, 12
Resist, 13 gate wiring, 14 source wiring, 1
5 Cs wiring, 16 semiconductor thin film.

Claims (6)

[Claims] 1. A gate electrode formed on a transparent insulating substrate, an intrinsic semiconductor layer provided on the gate electrode via a gate insulating film, a central portion of which is a channel, and a source / source on the intrinsic semiconductor layer. A semiconductor layer containing an n-type impurity provided in a drain contact region; a source electrode and a drain electrode forming a semiconductor element together with the intrinsic semiconductor layer and the semiconductor layer containing the impurity; A thin film transistor, wherein the thickness of the semiconductor layer is equal to or less than the thickness of the intrinsic semiconductor layer in the channel portion. 2. The film thickness of an intrinsic semiconductor layer below a source / drain electrode is one of the film thickness of the intrinsic semiconductor layer in a channel portion.
2. The thin film transistor according to claim 1, wherein the ratio is not less than / 2 and not more than 1. 3. A TF having a switching element including the thin film transistor according to claim 1 or 2 and a display element each controlled via the switching element.
A liquid crystal display device comprising: a T array substrate; a counter electrode substrate for sandwiching liquid crystal between the TFT array substrate; and a drive circuit for the switching element. 4. A first step of forming a metal thin film of Cr or the like on a transparent insulating substrate and pattern-forming a gate electrode line, wherein an intrinsic semiconductor layer and an n-type are formed on the gate electrode line via a gate insulating film. A second step of continuously forming a semiconductor layer containing an impurity of the type described above and forming a pattern in an island shape, forming a resist pattern on a portion serving as a channel of the TFT, and removing the impurity other than the portion covered with the resist. A third step of etching all of the semiconductor layers including the semiconductor layer and a part of the intrinsic semiconductor layer; rotating the substrate while covering the channel portion with the resist; ion-implanting n-type impurities from an oblique direction; A fourth step of re-forming a semiconductor layer containing an n-type impurity in the drain contact region, forming a metal thin film of Al, Cr, or the like by sputtering or the like; T, characterized in that it comprises a fifth step, a sixth step of the semiconductor layer containing the impurity on the channel is removed by dry etching or the like, a seventh step of forming an insulating film patterning
A method for manufacturing an FT array substrate. 5. In the second step, the intrinsic semiconductor layer is reduced by about 1
In the third step, the thickness of the intrinsic semiconductor layer other than the channel portion is reduced to about 100 nm in a third step.
The semiconductor layer containing the n-type impurity to about 30 nm
5. The method according to claim 4, wherein the formation of the intrinsic semiconductor layer below the source / drain electrodes is about 70 nm.
The manufacturing method of the TFT array substrate described in the above. 6. A first step of forming a metal thin film of Cr or the like on a transparent insulating substrate and patterning a gate electrode line, forming an intrinsic semiconductor layer on the gate electrode line via a gate insulating film. A second step of forming a pattern in an island shape, a third step of forming a resist on a portion to be a channel of the TFT, and etching a part of the intrinsic semiconductor layer other than the portion covered with the resist; After removing the resist, a semiconductor layer containing an n-type impurity is formed, and a fourth step of forming a pattern in an island shape is performed. A thin metal film of Al, Cr, or the like is formed by a sputtering method or the like. A fifth step of patterning an electrode; a sixth step of removing a semiconductor layer containing the impurity on the channel by dry etching or the like; and a seventh step of forming an insulating film. T characterized by
A method for manufacturing an FT array substrate.