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JPH11135537A - Mounting structure for semiconductor chip and semiconductor device - Google Patents

Mounting structure for semiconductor chip and semiconductor device

Info

Publication number
JPH11135537A
JPH11135537A JP9297428A JP29742897A JPH11135537A JP H11135537 A JPH11135537 A JP H11135537A JP 9297428 A JP9297428 A JP 9297428A JP 29742897 A JP29742897 A JP 29742897A JP H11135537 A JPH11135537 A JP H11135537A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor chips
electrodes
wire
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9297428A
Other languages
Japanese (ja)
Inventor
Masaaki Hiromitsu
正明 弘光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP9297428A priority Critical patent/JPH11135537A/en
Priority to US09/166,260 priority patent/US6441495B1/en
Publication of JPH11135537A publication Critical patent/JPH11135537A/en
Priority to US10/122,982 priority patent/US6861760B2/en
Priority to US11/032,840 priority patent/US7242100B2/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/788—Means for moving parts
    • H01L2224/78821—Upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/78822—Rotational mechanism
    • H01L2224/78823—Pivoting mechanism
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To appropriately connect electrodes to desired areas being wiring connecting objects at the time of mounting plural semiconductor chips through the use of the structure of what is called chip-on-chip. SOLUTION: In a mounting structure of a semiconductor chips, plural semiconductor chips 2A-2C are overlapped in the direction of thickness and plural electrodes 21a-21c provided for the plural semiconductor chips 2A-2C are connected to areas 10 being the wiring connection objects, which are positioned on sides through plural wires W. Wire bonding faces of the areas 10 being the wiring connection objects are provided in the middle height of the surfaces between the electrode 21c in the highest position and the electrode 21c in the lowest position.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【技術分野】本願発明は、複数の半導体チップをそれら
の厚み方向に積み重ねたいわゆるチップ・オン・チップ
と称される構造を用いて複数の半導体チップをリードフ
レームや基板などに対して適切に実装するための技術に
関する。BACKGROUND OF THE INVENTION The present invention relates to a so-called chip-on-chip structure in which a plurality of semiconductor chips are stacked in their thickness direction to appropriately mount the plurality of semiconductor chips on a lead frame, a substrate, or the like. Related to technology.

【０００２】[0002]

【従来の技術】周知のとおり、複数の半導体チップを用
いて所望の電子回路や半導体装置を製造する場合、半導
体チップの実装密度を高めることによって、電子回路や
半導体装置全体の小型化を図ることが強く要請される場
合が多い。この場合、複数の半導体チップを基板上に平
面的に配列しただけでは、その実装密度を高める上で一
定の限界がある。また、複数の半導体チップをワンチッ
プ化することは、半導体チップの製造作業が煩雑化する
ために、その製造コストは著しく高価となる。2. Description of the Related Art As is well known, when a desired electronic circuit or semiconductor device is manufactured by using a plurality of semiconductor chips, the mounting density of the semiconductor chips is increased to reduce the size of the entire electronic circuit or semiconductor device. Is often strongly required. In this case, simply arranging a plurality of semiconductor chips in a plane on the substrate has a certain limit in increasing the mounting density. In addition, making a plurality of semiconductor chips into one chip complicates the operation of manufacturing the semiconductor chips, so that the manufacturing cost becomes extremely high.

【０００３】そこで、従来では、いわゆるチップ・オン
・チップと称される構造を用いる手段がある。この手段
は、たとえば本願の図１１に示すように、複数の半導体
チップ９ａ〜９ｃを上下に積み重ねた状態で基板９０の
表面に実装する手段である。このような手段によれば、
基板９０の表面における半導体チップ９ａ〜９ｃの占有
面積が小さくなり、半導体チップの実装密度を高める上
で、有利となる。[0003] Therefore, conventionally, there is a means using a so-called chip-on-chip structure. This means is, for example, as shown in FIG. 11 of the present application, a means for mounting a plurality of semiconductor chips 9a to 9c on a surface of a substrate 90 in a state of being vertically stacked. According to such means,
The area occupied by the semiconductor chips 9a to 9c on the surface of the substrate 90 is reduced, which is advantageous in increasing the mounting density of the semiconductor chips.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、上記従
来の手段では、次のような不具合を生じていた。However, the above-mentioned conventional means has the following disadvantages.

【０００５】すなわち、複数の半導体チップ９ａ〜９ｃ
を上下に積み重ねた状態に実装すると、それらに設けら
れている電極９４ａ〜９４ｃの高さも順次高くなり、最
上層に位置する半導体チップ９ｃの電極９４ｃは、基板
９０の表面からかなり高い位置に存在することとなる。
その一方、従来では、ワイヤ９３を介して上記電極９４
ａ〜９４ｃと結線接続される複数の端子部９２は、上記
複数の半導体チップ９ａ〜９ｃの実装面と同一高さであ
る基板９０の表面に設けられていた。このため、従来で
は、複数の電極９４ａ〜９４ｃの全てが端子部９２より
も高い位置に存在し、しかも端子部９２から順次段階的
に遠ざかってゆく高さとなっており、最上位置に存在す
る電極９４ｃと端子部９２との高低差Ｈａはかなり大き
な寸法となっていた。That is, a plurality of semiconductor chips 9a to 9c
Are mounted in a vertically stacked state, the heights of the electrodes 94a to 94c provided thereon are sequentially increased, and the electrode 94c of the semiconductor chip 9c located on the uppermost layer is located at a position considerably higher than the surface of the substrate 90. Will be done.
On the other hand, conventionally, the electrode 94
The plurality of terminal portions 92 connected and connected to the terminals a to 94c are provided on the surface of the substrate 90 which is the same height as the mounting surface of the plurality of semiconductor chips 9a to 9c. For this reason, conventionally, all of the plurality of electrodes 94a to 94c are present at a position higher than the terminal portion 92, and furthermore, have a height that gradually moves away from the terminal portion 92 in a stepwise manner. The height difference Ha between the terminal 94c and the terminal portion 92 was considerably large.

【０００６】ところが、上記したようにたとえば電極９
４ｃと端子部９２との高低差Ｈａが大きくなってしまう
と、ワイヤ９３を用いてこれらの部分を適切に導通接続
することが困難となる場合があった。すなわち、電極９
４ｃと端子部９２とを結線接続する作業にはワイヤボン
ディング装置が用いられるが、一般的なワイヤボンディ
ング装置においてそのキャピラリが上下方向に移動して
ボンディング可能なストロークは、基準高さから±３０
０μｍ程度のストローク範囲に設定されているのが通例
である。したがって、従来では、上記高低差Ｈａの値が
大きく、その値が上記キャピラリのボンディング可能ス
トロークを超えてしまうことに原因し、ワイヤボンディ
ング装置を用いたワイヤボンディング作業を行うこと自
体が困難となる場合があった。また、従来では、仮にそ
うでない場合であっても、上記高低差Ｈａの値が大きい
ことに原因し、たとえば図１２に示すように、キャピラ
リ９５を用いてワイヤ９３を電極９４ｃまたは端子部９
２のボンディング対象位置に押しつけるときに、キャピ
ラリ９５が大きく傾く事態を招いていた。これでは、キ
ャピラリ９５の先端部がボンディング対象位置に対して
いわゆる片当たり状態となって、ワイヤ９３とボンディ
ング対象位置との間に隙間Ｓが生じ、ワイヤ９３を確実
にボンディングすることができない。このように、従来
では、ワイヤ９３の端部を電極９４ａ〜９４ｃや端子部
９２に対して適切にボンディングする作業が困難となっ
ており、ワイヤの接続箇所に接続不良を生じる虞れが大
きくなっていた。However, as described above, for example, the electrode 9
If the height difference Ha between the terminal portion 4c and the terminal portion 92 becomes large, it may be difficult to appropriately conduct and connect these portions using the wire 93. That is, the electrode 9
A wire bonding apparatus is used for the work of connecting and connecting the terminal 4c and the terminal portion 92. In a general wire bonding apparatus, the stroke at which the capillary moves up and down and can be bonded is ± 30 degrees from the reference height.
Usually, the stroke range is set to about 0 μm. Therefore, conventionally, when the value of the height difference Ha is large, and the value exceeds the bondable stroke of the capillary, it is difficult to perform the wire bonding operation using the wire bonding apparatus itself. was there. Conventionally, even if it is not the case, if the value of the height difference Ha is large, the wire 93 is connected to the electrode 94c or the terminal portion 9 using a capillary 95 as shown in FIG. 12, for example.
When the capillary 95 is pressed against the bonding position of No. 2, the capillary 95 is greatly inclined. In this case, the tip end of the capillary 95 is in a so-called one-sided contact state with respect to the bonding target position, and a gap S is generated between the wire 93 and the bonding target position, so that the wire 93 cannot be securely bonded. As described above, conventionally, it is difficult to appropriately bond the end of the wire 93 to the electrodes 94a to 94c and the terminal portions 92, and the possibility of poor connection at the wire connection point increases. I was

【０００７】本願発明は、このような事情のもとで考え
出されたものであって、いわゆるチップ・オン・チップ
の構造を用いて複数の半導体チップを実装する場合に、
それらの電極を所望の配線接続対象領域に対して適切に
結線接続できるようにすることをその課題としている。The present invention has been conceived under such circumstances, and when mounting a plurality of semiconductor chips using a so-called chip-on-chip structure,
It is an object of the present invention to appropriately connect and connect those electrodes to a desired wiring connection target region.

【０００８】[0008]

【発明の開示】上記の課題を解決するため、本願発明で
は、次の技術的手段を講じている。DISCLOSURE OF THE INVENTION In order to solve the above problems, the present invention employs the following technical means.

【０００９】本願発明の第１の側面によれば、半導体チ
ップの実装構造が提供される。この半導体チップの実装
構造は、複数の半導体チップがそれらの厚み方向に重ね
られており、かつこれら複数の半導体チップに設けられ
ている複数の電極がそれらの側方に位置する配線接続対
象領域に複数本のワイヤを介して接続されている半導体
チップの実装構造であって、上記配線接続対象領域のワ
イヤボンディング面は、上記複数の電極のうち、最も高
い位置の電極と最も低い位置の電極とのそれぞれの表面
の中間の高さに設けられていることに特徴づけられる。According to a first aspect of the present invention, there is provided a semiconductor chip mounting structure. In the mounting structure of the semiconductor chip, a plurality of semiconductor chips are stacked in their thickness direction, and a plurality of electrodes provided on the plurality of semiconductor chips are connected to a wiring connection target area located on their side. In a mounting structure of a semiconductor chip connected via a plurality of wires, the wire bonding surface of the wiring connection target area, the electrode of the highest position and the electrode of the lowest position among the plurality of electrodes Are provided at an intermediate height between the respective surfaces.

【００１０】本願発明においては、配線接続対象領域の
高さが、厚み方向に重ねられた複数の半導体チップのそ
れぞれの電極のうち最も高い位置の電極と最も低い位置
の電極とのそれぞれの表面の中間高さに設定されている
ために、上記複数の半導体チップのそれぞれの電極の一
部が配線接続対象領域から極端に遠く離れた高さになる
ことが解消され、配線接続対象領域と各電極との高低差
を小さくすることが可能となる。したがって、配線接続
対象領域と各電極との高低差が、ワイヤボンディング装
置のキャピラリのボンディング可能ストロークを超える
ことに原因して、配線接続対象領域と各電極とを結線接
続することが困難になるといった虞れを少なくすること
ができることは勿論のこと、ワイヤボンディング装置の
キャピラリを配線接続対象領域や各電極の表面に対して
傾きの少ない角度で押しつけることも可能となり、ワイ
ヤを配線接続対象領域や各電極の表面に対して適切に密
着させ得ることとなる。その結果、本願発明では、複数
の半導体チップの電極と配線接続対象領域とがワイヤを
介して適切に結線接続された接続不良の少ないチップ・
オン・チップ構造の半導体チップの実装構造が得られ
る。[0010] In the present invention, the height of the wiring connection target region is determined by adjusting the height of the surface of the highest electrode and the lowest surface of the electrodes of the plurality of semiconductor chips stacked in the thickness direction. Since the intermediate height is set, a part of each electrode of the plurality of semiconductor chips is prevented from having a height extremely far from the wiring connection target area. Can be reduced. Therefore, it is difficult to connect and connect the wiring connection target area and each electrode due to the height difference between the wiring connection target area and each electrode exceeding the bondable stroke of the capillary of the wire bonding apparatus. Needless to say, the danger can be reduced, and the capillary of the wire bonding apparatus can be pressed at a small angle to the wiring connection target area and the surface of each electrode. The electrode can be appropriately brought into close contact with the surface of the electrode. As a result, according to the present invention, a chip with few connection failures in which electrodes of a plurality of semiconductor chips and a wiring connection target region are appropriately connected and connected via wires.
A mounting structure of a semiconductor chip having an on-chip structure is obtained.

【００１１】本願発明の好ましい実施の形態では、上記
ワイヤの両端のボンディングは、電極側がファーストボ
ンディングとされているとともに、配線接続対象領域側
がセカンドボンディングとされている構成とすることが
できる。[0011] In a preferred embodiment of the present invention, the bonding at both ends of the wire may be configured such that the electrode side is first bonded and the wiring connection target area side is second bonding.

【００１２】このような構成によれば、複数の半導体チ
ップの各電極の表面に対してワイヤの一端をファースト
ボンディングするときには、ワイヤの先端部分が局所的
に溶融して表面張力によってボール状に凝集したボール
部（このボール部とは、たとえばワイヤが金線の場合に
は金ボールを意味する）を各電極に押しつけることとな
るために、上記ワイヤを保持するワイヤボンディング装
置のキャピラリが各電極の表面に対して多少傾いている
場合であっても、上記ワイヤのボール部を各電極の表面
に対して比較的容易に密着させることができる。このた
め、各電極の表面には、ワイヤの一端を広い面積で密着
させることできる。一方、配線接続対象領域に対してワ
イヤの他端をセカンドボンディングするときには、上記
配線接続対象領域をワイヤボンディングの基準高さとす
ることにより、すなわちキャピラリが配線接続対象領域
の表面に対して略垂直の角度姿勢となるように設定する
ことにより、上記ワイヤの他端の比較的広い範囲を上記
キャピラリによって配線接続対象領域に的確に押しつけ
て密着させることができる。結局、上記構成では、高さ
が種々相違する複数の電極に対するボンディングについ
ては、キャピラリの多少の傾きが許容されるファースト
ボンディングとする一方、配線接続対象領域に対するボ
ンディングについてはキャピラリを傾かせることのない
セカンドボンディングとすることによって、複数の半導
体チップの各電極と配線接続対象領域とのそれぞれへの
ワイヤボンディングをより一層適切に行うことができる
こととなる。According to such a configuration, when one end of the wire is first bonded to the surface of each electrode of the plurality of semiconductor chips, the tip portion of the wire is locally melted and aggregated into a ball shape by surface tension. (For example, when the wire is a gold wire, it means a gold ball) against each electrode. Therefore, the capillary of the wire bonding apparatus holding the wire is connected to each electrode. Even when the wire is slightly inclined with respect to the surface, the ball portion of the wire can be relatively easily brought into close contact with the surface of each electrode. Therefore, one end of the wire can be brought into close contact with the surface of each electrode over a wide area. On the other hand, when the other end of the wire is second-bonded to the wiring connection target area, the wiring connection target area is set to the reference height of the wire bonding, that is, the capillary is substantially perpendicular to the surface of the wiring connection target area. By setting the angle attitude, a relatively wide range of the other end of the wire can be accurately pressed and brought into close contact with the wiring connection target area by the capillary. After all, in the above configuration, the bonding to a plurality of electrodes having different heights is the first bonding in which a slight inclination of the capillary is allowed, whereas the bonding to the wiring connection target region is not inclined. By performing the second bonding, it is possible to more appropriately perform the wire bonding to each of the electrodes of the plurality of semiconductor chips and the wiring connection target region.

【００１３】本願発明の他の好ましい実施の形態では、
上記複数の半導体チップは、リードフレームのダイパッ
ド部上に実装されているとともに、このリードフレーム
の上記ダイパッド部の側方に位置する内部リード部が上
記配線接続対象領域とされており、かつ上記内部リード
部は、上記ダイパッド部よりも高い位置に設けられてい
る構成とすることができる。In another preferred embodiment of the present invention,
The plurality of semiconductor chips are mounted on a die pad portion of a lead frame, and an internal lead portion located on a side of the die pad portion of the lead frame is set as the wiring connection target area; The lead portion may be provided at a position higher than the die pad portion.

【００１４】このような構成によれば、リードフレーム
の内部リード部が上下厚み方向に重ねられた複数の半導
体チップが実装されているリードフレームのダイパッド
部よりも高い位置に存在するために、これらダイパッド
部と内部リード部との高低差を利用することによって、
上記内部リード部を上記複数の半導体チップの複数の電
極のうち最も高い位置の電極と最も低い位置の電極との
それぞれの表面の中間高さに設定することが容易に行え
ることとなる。According to such a configuration, since the internal lead portion of the lead frame exists at a position higher than the die pad portion of the lead frame on which a plurality of semiconductor chips stacked in the vertical thickness direction are mounted. By utilizing the height difference between the die pad and the internal lead,
The internal lead portion can be easily set to an intermediate height between the surfaces of the highest electrode and the lowest electrode among the plurality of electrodes of the plurality of semiconductor chips.

【００１５】本願発明の第２の側面によれば、半導体装
置が提供される。この半導体装置は、本願発明の第１の
側面によって提供される半導体チップの実装構造を有し
ていることに特徴づけられる。According to a second aspect of the present invention, there is provided a semiconductor device. This semiconductor device is characterized by having a semiconductor chip mounting structure provided by the first aspect of the present invention.

【００１６】本願発明の第２の側面では、本願発明の第
１の側面によって得られるのと同様な効果が期待でき、
複数の半導体チップの実装密度が高く、しかもそれら複
数の半導体チップの電極と配線接続対象領域との結線接
続が適切に行われた構造の半導体装置が得られる。According to the second aspect of the present invention, the same effect as obtained by the first aspect of the present invention can be expected.
A semiconductor device having a structure in which the mounting density of the plurality of semiconductor chips is high and the connection between the electrodes of the plurality of semiconductor chips and the wiring connection target region is appropriately performed is obtained.

【００１７】[0017]

【発明の実施の形態】以下、本願発明の好ましい実施の
形態について、図面を参照しつつ具体的に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

【００１８】図１は、本願発明に係る半導体チップの実
装構造を有する半導体装置中間品Ａの一例を示す要部断
面図である。図２は、図１の要部平面図である。FIG. 1 is a sectional view of an essential part showing an example of a semiconductor device intermediate product A having a semiconductor chip mounting structure according to the present invention. FIG. 2 is a plan view of a main part of FIG.

【００１９】図１および図２に示す半導体装置中間品Ａ
は、３つの半導体チップ２Ａ，２Ｂ，２Ｃのそれぞれ
を、それらの厚み方向である上下方向に重ねた状態でリ
ードフレーム１上に搭載し、かつそれら３つの半導体チ
ップ２Ａ〜２Ｃのそれぞれを複数本のワイヤＷを介して
上記リードフレーム１の内部リード部１０に導通接続し
た構造を有している。本実施形態では、上記半導体チッ
プ２Ａ〜２Ｃのうち、最下層の半導体チップ２Ａを第１
の半導体チップと称する。また、中間層の半導体チップ
２Ｂを第２の半導体チップと称し、最上層の半導体チッ
プ２Ｃを第３の半導体チップと称する。Semiconductor device intermediate product A shown in FIGS. 1 and 2
Is mounted on a lead frame 1 in a state where three semiconductor chips 2A, 2B and 2C are stacked in the vertical direction which is their thickness direction, and a plurality of each of the three semiconductor chips 2A to 2C is mounted. The structure is electrically connected to the internal lead portion 10 of the lead frame 1 via the wire W. In the present embodiment, of the semiconductor chips 2A to 2C, the lowermost semiconductor chip 2A is the first semiconductor chip 2A.
Semiconductor chip. The intermediate semiconductor chip 2B is referred to as a second semiconductor chip, and the uppermost semiconductor chip 2C is referred to as a third semiconductor chip.

【００２０】図３は、上記リードフレーム１の平面図で
ある。このリードフレーム１は、たとえば銅製の金属板
に打ち抜きプレス加工を施すなどして形成されたもので
あり、一定方向に延びる長尺状である。このリードフレ
ーム１の基本的な構成は、後述する点を除き、半導体装
置の製造用途に従来から用いられている一般的なリード
フレームの構成と共通している。すなわち、このリード
フレーム１は、半導体チップを搭載するためのダイパッ
ド部１１をその長手方向に一定間隔で複数箇所形成した
ものであり、このダイパッド部１１を支持するサポート
リード１２、上記ダイパッド部１１から離反した位置に
設けられた複数条の内部リード部１０、およびこれら複
数条の内部リード部１０とタイバー１３を介して繋がっ
た複数条の外部リード部１４を具備している。FIG. 3 is a plan view of the lead frame 1. The lead frame 1 is formed, for example, by punching and pressing a copper metal plate, and has a long shape extending in a certain direction. The basic configuration of the lead frame 1 is common to the configuration of a general lead frame conventionally used for semiconductor device manufacturing purposes, except for the points described below. That is, the lead frame 1 is formed by forming a plurality of die pad portions 11 for mounting a semiconductor chip at regular intervals in the longitudinal direction thereof. The support leads 12 for supporting the die pad portions 11 and the die pad portions 11 are provided. It has a plurality of internal leads 10 provided at separated positions, and a plurality of external leads 14 connected to the plurality of internal leads 10 via tie bars 13.

【００２１】ただし、上記リードフレーム１は、図１に
よく表れているように、上記複数条の内部リード部１０
のそれぞれの基端部１０ａが上方に屈曲し、立ち上がっ
ている。これにより、上記各内部リード部１０の上記基
端部１０ａ以外の箇所が、ダイパッド部１１や外部リー
ド部１４などの上記リードフレーム１の他の部分の表面
よりも一定寸法Ｈだけ高くなるように設けられている。
上記各内部リード部１０は、ワイヤＷの一端がボンディ
ングされる部分であり、本願発明でいう配線接続対象領
域の一例に相当する。However, as shown in FIG. 1, the lead frame 1 has a plurality of internal lead portions 10 as described above.
Are bent upward and stand up. Thereby, the portion other than the base end portion 10a of each of the internal lead portions 10 is higher than the surface of the other portion of the lead frame 1 such as the die pad portion 11 and the external lead portion 14 by a predetermined dimension H. Is provided.
Each of the internal lead portions 10 is a portion to which one end of the wire W is bonded, and corresponds to an example of a wiring connection target area in the present invention.

【００２２】上記３つの半導体チップ２Ａ〜２Ｃのそれ
ぞれは、たとえばＬＳＩチップやその他のＩＣチップと
して構成されたものであり、シリコンチップ上に所望の
電子回路を集積させて一体的に造り込んだものである。
上記３つの半導体チップ２Ａ〜２Ｃは、電極２１ａ〜２
１ｃが設けられている主面２０ａ〜２０ｃが上向きとな
る姿勢とされており、第１の半導体チップ２Ａはその主
面２０ａとは反対側の面が上記リードフレーム１のダイ
パッド部１１の上面に接着剤を介して接着されている。
上記第２の半導体チップ２Ｂは、上記第１の半導体チッ
プ２Ａよりも小サイズであり、上記第１の半導体チップ
２Ａの電極２１ａの上方を覆わないように位置決めさ
れ、その主面２０ｂとは反対側の面が上記第１の半導体
チップ２Ａの主面２０ａに接着されている。上記第３の
半導体チップ２Ｃは、上記第２の半導体チップ２Ｂより
もさらに小サイズであり、上記第２の半導体チップ２Ｂ
の電極２１ｂの上方を覆わないように位置決めされ、そ
の主面２０ｃとは反対側の面が上記第２の半導体チップ
２Ｂの主面２０ｂに接着されている。Each of the three semiconductor chips 2A to 2C is configured as, for example, an LSI chip or another IC chip, and is obtained by integrating a desired electronic circuit on a silicon chip and integrally forming the same. It is.
The three semiconductor chips 2A to 2C are connected to the electrodes 21a to 2c.
The first semiconductor chip 2A has a surface opposite to the main surface 20a on an upper surface of the die pad portion 11 of the lead frame 1. It is bonded via an adhesive.
The second semiconductor chip 2B is smaller in size than the first semiconductor chip 2A, is positioned so as not to cover above the electrodes 21a of the first semiconductor chip 2A, and is opposite to the main surface 20b. The side surface is bonded to the main surface 20a of the first semiconductor chip 2A. The third semiconductor chip 2C is even smaller in size than the second semiconductor chip 2B.
Is positioned so as not to cover the upper part of the electrode 21b, and the surface opposite to the main surface 20c is bonded to the main surface 20b of the second semiconductor chip 2B.

【００２３】上記３つの半導体チップ２Ａ〜２Ｃの複数
の電極２１ａ〜２１ｃは、トータルとして見た場合に、
上・中・下の３段階の高さとなっているが、既述したよ
うに、上記各内部リード部１０はダイパッド部１１より
も高い位置に存在している。これにより、本実施形態で
は、上記各内部リード部１０の表面の高さは、中間高さ
の複数の電極２１ｂと略同等の高さに設定されており、
最も低い複数の電極２１ａと最も高い複数の電極２１ｃ
との中間の高さとなっている。なお、上記複数の電極２
１ａ〜２１ｃのそれぞれは、いずれもワイヤボンディン
グに適するパッド状の電極として形成されており、その
材質はたとえばアルミ製とされている。ただし、好まし
くは、ワイヤＷとの導電接続性を良好にするための手段
として、上記電極２１ａ〜２１ｃを構成するアルミ電極
の表面には金メッキが施されている。The plurality of electrodes 21a to 21c of the three semiconductor chips 2A to 2C, when viewed as a whole,
Although the height has three levels of upper, middle, and lower, as described above, each of the internal lead portions 10 exists at a position higher than the die pad portion 11. Thus, in the present embodiment, the height of the surface of each of the internal lead portions 10 is set to be substantially equal to the height of the plurality of electrodes 21b having an intermediate height.
The lowest plural electrodes 21a and the highest plural electrodes 21c
And the middle height. The plurality of electrodes 2
Each of 1a to 21c is formed as a pad-shaped electrode suitable for wire bonding, and its material is, for example, aluminum. Preferably, however, gold plating is applied to the surfaces of the aluminum electrodes constituting the electrodes 21a to 21c as a means for improving the conductive connection with the wire W.

【００２４】上記複数本のワイヤＷとしては、たとえば
金線が用いられている。これら複数本のワイヤＷの両端
は、上記３つの半導体チップ２Ａ〜２Ｃの複数の電極２
１ａ〜２１ｃとそれに対応する内部リード部１０とにボ
ンディングされており、そのワイヤボンディング法とし
ては、たとえば熱超音波ボンディング法が用いられてい
る。上記電極２１ａ〜２１ｃに対するボンディングは、
内部リード部１０に対するボンディングよりも先に行わ
れるファーストボンディングとされている。したがっ
て、上記内部リード部１０に対するボンディングは、セ
カンドボンディングとされている。As the plurality of wires W, for example, gold wires are used. Both ends of these wires W are connected to the electrodes 2 of the three semiconductor chips 2A to 2C.
The wires 1a to 21c and the corresponding internal lead portions 10 are bonded to each other. As a wire bonding method, for example, a thermosonic bonding method is used. The bonding to the electrodes 21a to 21c is as follows.
The first bonding is performed before the bonding to the internal lead portion 10. Therefore, the bonding to the internal lead portion 10 is a second bonding.

【００２５】上記半導体チップの実装構造においては、
まず、３段階の高さとなっている複数の電極２１ａ〜２
１ｃのうち、中間高さの電極２１ｂの表面の高さは、各
内部リード部１０の表面の高さと略同等とされている。
このため、上記電極２１ｂとこれに対応する内部リード
部１０とにワイヤＷの両端のボンディング作業を行うと
きには、そのワイヤＷを保持するワイヤボンディング装
置のキャピラリを、上記電極２１ｂの表面と上記内部リ
ード部１０の表面とのいずれに対しても垂直または略垂
直の姿勢で押しつけることが可能となる。したがって、
ワイヤＷの両端をそれらの表面に密着させた適正なワイ
ヤボンディングが行え、電極２１ｂとそれに対応する内
部リード部１０とが適切に結線接続された構造とするこ
とができる。In the mounting structure of the semiconductor chip,
First, a plurality of electrodes 21a to 21a having three levels of height are provided.
In 1c, the height of the surface of the intermediate height electrode 21b is substantially equal to the height of the surface of each internal lead portion 10.
For this reason, when performing the bonding operation of both ends of the wire W to the electrode 21b and the corresponding internal lead portion 10, the capillary of the wire bonding apparatus holding the wire W is connected to the surface of the electrode 21b and the internal lead. It is possible to press against any of the surfaces of the part 10 in a vertical or substantially vertical posture. Therefore,
Appropriate wire bonding in which both ends of the wire W are in close contact with their surfaces can be performed, and a structure in which the electrode 21b and the corresponding internal lead portion 10 are appropriately connected and connected can be obtained.

【００２６】一方、他の２組の複数の電極２１ａ，２１
ｃは、上記電極２１ｂとは異なり、内部リード部１０よ
りも低い位置または高い位置に存在するが、内部リード
部１０は上記電極２１ａ，２１ｃの中間の高さであるた
めに、これらの電極２１ａ，２１ｃのそれぞれと内部リ
ード部１０との高低差Ｈ１，Ｈ２をかなり小さくするこ
とができる。具体的には、それらの高低差Ｈ１，Ｈ２の
それぞれの値を、電極２１ａ，２１ｃ間の高低差の約１
／２にすることができる。したがって、それらの部分に
ワイヤＷの両端のボンディング作業を行う場合に、ワイ
ヤボンディング装置のキャピラリが上記内部リード部１
０の高さを基準として上下方向に動作するように設定す
ることによって、電極２１ａ，２１ｃに対してワイヤボ
ンディングを行うときのそれら電極２１ａ，２１ｃの各
表面に対するキャピラリの傾き角度を小さくすることが
できることとなる。したがって、キャピラリの大きな傾
きに原因してワイヤボンディング不良が生じる虞れを少
なくすることができる。On the other hand, the other two sets of a plurality of electrodes 21a, 21
Unlike the electrodes 21b, c is present at a position lower or higher than the internal lead portion 10. However, since the internal lead portion 10 is at a height intermediate between the electrodes 21a and 21c, these electrodes 21a , 21c and the internal lead portion 10, the height difference H1, H2 can be considerably reduced. Specifically, the respective values of the height differences H1 and H2 are set to about 1 of the height difference between the electrodes 21a and 21c.
/ 2. Therefore, when the bonding operation of both ends of the wire W is performed on those portions, the capillary of the wire bonding apparatus is connected to the internal lead portion 1.
By setting to operate vertically with reference to the height of 0, it is possible to reduce the inclination angle of the capillary with respect to each surface of the electrodes 21a, 21c when performing wire bonding to the electrodes 21a, 21c. You can do it. Therefore, it is possible to reduce a possibility that a wire bonding failure occurs due to a large inclination of the capillary.

【００２７】また、上記複数の電極２１ａ〜２１ｃへの
ワイヤボンディングがファーストボンディングとされて
いるために、次に説明するように、それらの部分および
各内部リード部１０にはワイヤＷのボンディング不良が
一層生じ難くなっている。すなわち、たとえば図４を参
照して最も高い位置に存在する電極２１ｃにワイヤＷの
一端をファーストボンディングする場合について説明す
ると、このファーストボンディングは、まずキャピラリ
３に保持されたワイヤＷの先端部を加熱して金ボールＷ
ａを作製した後に、この金ボールＷａをキャピラリ３の
先端部によって電極２１ｃの表面に押しつけることによ
って行われる。したがって、このように金が溶融軟化状
態にある金ボールＷａを電極２１ｃの表面に押しつける
場合に、キャピラリ３が多少の角度θだけ鉛直線に対し
て傾斜していても、図５に示すように、上記金ボールＷ
ａの底部を電極２１ｃの表面に対して隙間なく押しつけ
ることが可能である。金ボールＷａをボンディング面に
押しつけるファーストボンディングは、後述するセカン
ドボンディングの場合と比較すると、キャピラリの傾き
の許容度が大きい。このため、上記電極２１ｃに対する
ワイヤボンディング作業をより一層適切に行うことが可
能となる。むろん、他の電極２１ａについてのワイヤボ
ンディング作業についても同様である。Further, since wire bonding to the plurality of electrodes 21a to 21c is performed by first bonding, a bonding failure of the wire W is not generated in these portions and each internal lead portion 10 as described below. It is even less likely to occur. That is, for example, a case in which one end of the wire W is first bonded to the electrode 21c located at the highest position with reference to FIG. 4 will be described. In the first bonding, first, the tip of the wire W held by the capillary 3 is heated. And gold ball W
After the fabrication of a, the gold ball Wa is pressed against the surface of the electrode 21 c by the tip of the capillary 3. Therefore, when the gold ball Wa in which the gold is in the molten and softened state is pressed against the surface of the electrode 21c, even if the capillary 3 is inclined with respect to the vertical line by a certain angle θ, as shown in FIG. , The above gold ball W
It is possible to press the bottom of a without any gap against the surface of the electrode 21c. In the first bonding in which the gold ball Wa is pressed against the bonding surface, the tolerance of the inclination of the capillary is larger than that in the second bonding described later. For this reason, it is possible to more appropriately perform the wire bonding operation for the electrode 21c. It goes without saying that the same applies to the wire bonding operation for the other electrodes 21a.

【００２８】次いで、内部リード部１０に対するワイヤ
Ｗのセカンドボンディングは、たとえば図６において、
内部リード部１０を加熱しながらキャピラリ３に保持さ
れたワイヤＷを上記内部リード部１０の表面に押しつけ
て超音波をかけて行われる。このため、このセカンドボ
ンディングでは、キャピラリ３の傾きの許容度は比較的
小さい。ところが、本実施形態では、上記内部リード部
１０の高さが、キャピラリ３が昇降動作するときの基準
高さとされており、上記内部リード部１０の表面に対し
てはキャピラリ３を垂直または略垂直の姿勢で押しつけ
ことができるようになっている。一方、リードフレーム
１に複数設けられている内部リード部１０のそれぞれ
は、全て同一高さである。したがって、各内部リード部
１０に対するワイヤボンディング作業も適切に行えるこ
ととなる。このように、上記半導体チップの実装構造に
おいては、３つの半導体チップ２Ａ〜２Ｃの電極２１ａ
〜２１ｃの全ての箇所について、それらに対応する内部
リード部１０に対して適切に結線接続することができ
る。Next, the second bonding of the wire W to the internal lead portion 10 is performed, for example, in FIG.
The heating is performed by pressing the wire W held by the capillary 3 against the surface of the internal lead 10 while heating the internal lead 10 and applying ultrasonic waves. Therefore, in this second bonding, the tolerance of the inclination of the capillary 3 is relatively small. However, in the present embodiment, the height of the internal lead portion 10 is a reference height when the capillary 3 moves up and down, and the capillary 3 is vertically or substantially perpendicular to the surface of the internal lead portion 10. It can be pressed in the posture of. On the other hand, each of the plurality of internal lead portions 10 provided on the lead frame 1 has the same height. Therefore, the wire bonding operation for each internal lead portion 10 can be appropriately performed. Thus, in the mounting structure of the semiconductor chip, the electrodes 21a of the three semiconductor chips 2A to 2C are provided.
21c can be appropriately connected and connected to the corresponding internal lead portions 10.

【００２９】図７は、上記図１および図２に示した半導
体装置中間品Ａを利用して製造された半導体装置Ｂの一
例を示す断面図である。FIG. 7 is a sectional view showing an example of a semiconductor device B manufactured using the semiconductor device intermediate product A shown in FIGS.

【００３０】同図に示す半導体装置Ｂは、上記半導体装
置中間品Ａの３つの半導体チップ２Ａ〜２Ｃやその周辺
部分をモールド樹脂４によって覆う樹脂パッケージ作業
や、リードフレーム１のフォーミング加工を行うことに
よって得られる。このような一連の作業は、従来のリー
ドフレームを用いた半導体装置の製造工程と同様であ
り、その詳細な説明は省略するが、上記モールド樹脂４
によって半導体チップ２Ａ〜２Ｃの主面や他の部分、お
よびワイヤＷなどの導電部分が適切に保護される。ま
た、各内部リード部１０に繋がっている外部リード部１
４が、ハンダ付け用の端子としての役割を果たし、上記
半導体装置Ｂは所望の部位への面実装が可能なものとな
る。The semiconductor device B shown in FIG. 1 performs a resin package operation of covering the three semiconductor chips 2A to 2C of the semiconductor device intermediate product A and the peripheral portion thereof with a mold resin 4, and performs a forming process of the lead frame 1. Obtained by Such a series of operations are the same as those in the manufacturing process of a semiconductor device using a conventional lead frame, and detailed description thereof is omitted.
Thereby, the main surfaces and other portions of the semiconductor chips 2A to 2C and the conductive portions such as the wires W are appropriately protected. Further, the external lead 1 connected to each internal lead 10
4 serves as a terminal for soldering, and the semiconductor device B can be surface-mounted on a desired portion.

【００３１】図８ないし図１０は、本願発明に係る半導
体チップの実装構造の他の例をそれぞれ示す要部断面図
である。FIGS. 8 to 10 are cross-sectional views of main parts showing other examples of the mounting structure of the semiconductor chip according to the present invention.

【００３２】図８に示す構造は、３つの半導体チップ２
Ａ〜２Ｃの実装箇所となるリードフレーム１Ａのダイパ
ッド部１１Ａを、内部リード部１０Ａや外部リード部１
４Ａなどの上記リードフレーム１Ａの他の部分よりも低
い高さに形成することによって、ワイヤＷの一端がボン
ディングされる内部リード部１０Ａを上記半導体チップ
２Ａ〜２Ｃの電極２１ａ，２１ｃの中間高さに設定した
構造である。このように、本願発明では、内部リード部
をダイパッド部よりも高い位置に設ける手段としては、
上記図８に示すようにリードフレームのダイパッド部を
部分的に低くする手段と、上記図１および図２に示した
先の実施形態のようにリードフレームの内部リード部を
部分的に高くする手段とのいずれの手段を採用してもよ
い。The structure shown in FIG.
The die pad portion 11A of the lead frame 1A, which is a mounting portion for the A to 2C, is replaced with the internal lead portion 10A or the external lead
By forming the inner lead portion 10A, to which one end of the wire W is bonded, at an intermediate height between the electrodes 21a and 21c of the semiconductor chips 2A to 2C by forming the lead portion 1A at a height lower than other portions of the lead frame 1A. This is the structure set in. As described above, in the present invention, as means for providing the internal lead portion at a position higher than the die pad portion,
Means for partially lowering the die pad portion of the lead frame as shown in FIG. 8 and means for partially raising the internal lead portion of the lead frame as in the previous embodiment shown in FIG. 1 and FIG. Any of the means may be adopted.

【００３３】図９に示す構造は、３つの半導体チップ２
Ａ〜２Ｃを一定の厚みを有するプレート状の基板１Ｂに
実装し、上記半導体チップ２Ａ〜２Ｃの電極２１ａ〜２
１ｃのそれぞれを上記基板１Ｂの表面に設けられた端子
部１９にワイヤＷを介して結線接続した構造である。上
記半導体チップ２Ａ〜２Ｃは、上記基板１Ｂの表面に設
けられた凹部１８内に配置されるなどして、それら半導
体チップ２Ａ〜２Ｃの実装面１７ａと上記端子部１９の
表面との間には高低差Ｈ３が設けられている。むろん、
これに代えて、基板１Ｂの表面部のうち上記端子部１９
が形成されている箇所を部分的に他の箇所よりも高くな
るように形成することによって、半導体チップ２Ａ〜２
Ｃの実装面と端子部１９との間に高低差Ｈ３を設けても
よい。上記構造では、上記高低差Ｈ３が設けられている
ことにより、上記端子部１９は、上記半導体チップ２
Ａ，２Ｃのそれぞれの電極２１ａ，２１ｃの中間高さと
なっている。The structure shown in FIG.
A to 2C are mounted on a plate-shaped substrate 1B having a certain thickness, and the electrodes 21a to 2c of the semiconductor chips 2A to 2C are mounted.
1c is connected to a terminal 19 provided on the surface of the substrate 1B via a wire W. The semiconductor chips 2 </ b> A to 2 </ b> C are disposed in a concave portion 18 provided on the surface of the substrate 1 </ b> B, for example, so that there is a gap between the mounting surface 17 a of the semiconductor chips 2 </ b> A to 2 </ b> C and the surface of the terminal portion 19. A height difference H3 is provided. Of course,
Instead of this, the terminal portion 19 of the surface portion of the substrate 1B is used.
Is formed so as to be partially higher than the other portions, thereby forming the semiconductor chips 2A to 2A.
A height difference H3 may be provided between the mounting surface of C and the terminal portion 19. In the above structure, since the height difference H3 is provided, the terminal portion 19 is connected to the semiconductor chip 2.
The height is an intermediate height between the electrodes 21a and 21c of A and 2C.

【００３４】このように、本願発明では、半導体チップ
をリードフレームに実装する場合に限らず、プレート状
などの形態を有する基板に実装する場合にも適用するこ
とができる。また、基板としては、セラミック製や合成
樹脂製などの比較的硬質な基板に限らず、たとえば薄肉
の合成樹脂樹脂製フィルムに銅箔などを用いてワイヤボ
ンディング箇所となる端子部を形成したようなフィルム
状の基板を用いることも可能である。したがって、本願
発明にいう配線接続対象領域の具体的な構成もとくに問
わない。As described above, the present invention can be applied not only to the case where the semiconductor chip is mounted on the lead frame but also to the case where the semiconductor chip is mounted on a substrate having a plate shape or the like. Further, the substrate is not limited to a relatively hard substrate such as a ceramic or synthetic resin, for example, a thin synthetic resin resin film formed with a copper foil or the like to form a terminal portion serving as a wire bonding portion. It is also possible to use a film-like substrate. Therefore, the specific configuration of the wiring connection target area according to the present invention does not matter.

【００３５】図１０に示す構造は、３つの半導体チップ
２Ｄ〜２Ｆを上下に積み重ねた状態で基板１Ｃに実装し
た構造であるが、最下層と中間層の２つの半導体チップ
２Ｄ，２Ｅどうしはバンプ電極２９，２９ａを介して互
いに接続されている。このため、最下層と最上層の２つ
の半導体チップ２Ｄ，２Ｆの電極２１ｄ，２１ｆのみが
ワイヤＷを介して基板１Ａの端子部１９Ａに結線接続さ
れている。上記端子部１９Ａは、上記２組の電極２１
ｄ，２１ｆの中間高さに設けられている。このように、
本願発明では、チップ・オン・チップ構造に実装された
複数の半導体チップの全てを所定の配線接続対象領域に
ワイヤを用いて結線接続する必要はなく、互いに厚み方
向に重ねられた複数の半導体チップのうち、一部の半導
体チップどうしを直接電気的に接続した構造を採用して
もよい。The structure shown in FIG. 10 is a structure in which three semiconductor chips 2D to 2F are mounted on a substrate 1C in a state of being stacked vertically, and two semiconductor chips 2D and 2E of a lowermost layer and an intermediate layer are bumped. They are connected to each other via the electrodes 29 and 29a. Therefore, only the electrodes 21d and 21f of the two lowermost and uppermost semiconductor chips 2D and 2F are connected to the terminal portion 19A of the substrate 1A via the wires W. The terminal portion 19A is connected to the two sets of electrodes 21.
It is provided at an intermediate height between d and 21f. in this way,
In the present invention, it is not necessary to wire-connect all of the plurality of semiconductor chips mounted in the chip-on-chip structure to the predetermined wiring connection target area using wires, and the plurality of semiconductor chips stacked in the thickness direction are mutually stacked. Among them, a structure in which some semiconductor chips are directly electrically connected to each other may be adopted.

【００３６】本願発明に係る半導体チップの実装構造、
および半導体装置の各部の具体的な構成は、上述した実
施形態に限定されず、種々に設計変更自在である。本願
発明は、互いに重ねられる半導体チップの具体的な数は
３つに限定されず、２つ、あるいは４つ以上であっても
よい。本願発明は、２つ以上の半導体チップをそれらの
厚み方向に重ねた構造において、それら複数の半導体チ
ップに高さが相違する少なくとも２組以上の電極が存在
し、かつこれら２組以上の電極をワイヤを用いて所定の
配線接続対象領域に結線接続する全ての場合に適用する
ことが可能である。先の図１０から理解されるように、
ワイヤボンディング対象となる半導体チップの電極が２
組しか存在しない場合は、むろん配線接続対象領域の高
さは、それら２組の電極のそれぞれの表面の高さの中間
高さに設定すればよい。また、本願発明では、配線接続
対象領域の高さが、半導体チップの複数の電極のうち、
最も高い位置の電極と最も低い位置の電極とのそれぞれ
の表面の高さの中間の高さであることが要件とされる
が、この中間の高さとは、配線接続対象領域が最も高い
位置の電極の表面よりも低く、かつ最も低い位置の電極
の表面よりも高い位置に存在すれば足りることを意味
し、必ずしも上記２つの電極間の中央の高さである必要
はない。ただし、ワイヤボンディング作業を最適に行う
ためには、一般的には配線接続対象領域の高さを上記２
つの電極間の略中央の高さに設定することが好ましい。A semiconductor chip mounting structure according to the present invention,
The specific configuration of each part of the semiconductor device is not limited to the above-described embodiment, and various design changes can be made. In the present invention, the specific number of semiconductor chips stacked on each other is not limited to three, and may be two or four or more. The present invention relates to a structure in which two or more semiconductor chips are stacked in their thickness direction, the plurality of semiconductor chips have at least two or more sets of electrodes having different heights, and these two or more sets of electrodes are connected to each other. The present invention can be applied to all cases where a wire is connected to a predetermined wiring connection target area. As understood from FIG. 10 above,
The electrode of the semiconductor chip to be wire-bonded is 2
In the case where only pairs exist, the height of the wiring connection target region may be set to an intermediate height between the heights of the surfaces of the two sets of electrodes. Further, according to the present invention, the height of the wiring connection target region is set to a value selected from among a plurality of electrodes of the semiconductor chip.
It is required that the height be an intermediate height between the surface heights of the highest electrode and the lowest electrode, and the intermediate height is the height of the position where the wiring connection target area is the highest. It means that it suffices if it is present at a position lower than the surface of the electrode and higher than the surface of the electrode at the lowest position, and it is not necessarily required to be the center height between the two electrodes. However, in order to perform the wire bonding operation optimally, generally, the height of the wiring connection target area is set to the above-mentioned value.
It is preferable that the height be set at a substantially central height between the two electrodes.

【００３７】さらに、上記実施形態では、ワイヤとして
金線を用いたが、本願発明はやはりこれに限定されず、
他の材質のワイヤを用いてもかまわない。また、本願発
明は、半導体チップの具体的な種類も問わず、たとえば
強誘電体メモリ（ferroelectrics-RAM）などの各種のメ
モリ素子をはじめとして、その他の種々のＩＣチップや
ＬＳＩチップなどの半導体チップを適用することができ
る。Further, in the above embodiment, the gold wire is used as the wire, but the present invention is not limited to this, but
A wire of another material may be used. In addition, the present invention is not limited to a specific type of semiconductor chip, and includes various memory elements such as a ferroelectric memory (ferroelectrics-RAM), and other various types of semiconductor chips such as an IC chip and an LSI chip. Can be applied.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本願発明に係る半導体チップの実装構造を有す
る半導体装置中間品の一例を示す要部断面図である。FIG. 1 is a cross-sectional view of a main part showing an example of a semiconductor device intermediate product having a semiconductor chip mounting structure according to the present invention.

【図２】図１の要部平面図である。FIG. 2 is a plan view of a main part of FIG.

【図３】図１および図２に示す半導体装置中間品に用い
られているリードフレームの平面図である。FIG. 3 is a plan view of a lead frame used in the intermediate semiconductor device shown in FIGS. 1 and 2;

【図４】ワイヤのファーストボンディング工程を示す要
部斜視図である。FIG. 4 is an essential part perspective view showing a wire first bonding step;

【図５】ワイヤのファーストボンディング工程を示す要
部斜視図である。FIG. 5 is an essential part perspective view showing a wire first bonding step;

【図６】ワイヤのセカンドボンディング工程を示す要部
斜視図である。FIG. 6 is an essential part perspective view showing a second bonding step of the wire;

【図７】図１および図２に示した半導体装置中間品を利
用して製造された半導体装置の一例を示す断面図であ
る。FIG. 7 is a sectional view showing an example of a semiconductor device manufactured using the semiconductor device intermediate product shown in FIGS. 1 and 2;

【図８】本願発明に係る半導体チップの実装構造の他の
例を示す説明図である。FIG. 8 is an explanatory view showing another example of the mounting structure of the semiconductor chip according to the present invention.

【図９】本願発明に係る半導体チップの実装構造の他の
例を示す説明図である。FIG. 9 is an explanatory view showing another example of the mounting structure of the semiconductor chip according to the present invention.

【図１０】本願発明に係る半導体チップの実装構造の他
の例を示す説明図である。FIG. 10 is an explanatory view showing another example of the mounting structure of the semiconductor chip according to the present invention.

【図１１】従来の半導体チップの実装構造の一例を示す
説明図である。FIG. 11 is an explanatory view showing an example of a conventional mounting structure of a semiconductor chip.

【図１２】従来のワイヤボンディング工程を示す要部断
面図である。FIG. 12 is a cross-sectional view of relevant parts showing a conventional wire bonding step.

【符号の説明】[Explanation of symbols]

１ リードフレーム １Ａ，１Ｂ 基板 ２Ａ 第１の半導体チップ ２Ｂ 第２の半導体チップ ２Ｃ 第３の半導体チップ ２Ｄ〜２Ｆ 半導体チップ １０，１０Ａ 内部リード部（配線接続対象領域） １１，１１Ａ ダイパッド部 １９，１９Ａ 端子部（配線接続対象領域） ２１ａ〜２１ｄ，２１ｆ 電極 Ｗ ワイヤ Ａ 半導体装置中間品 Ｂ 半導体装置 DESCRIPTION OF SYMBOLS 1 Lead frame 1A, 1B board | substrate 2A 1st semiconductor chip 2B 2nd semiconductor chip 2C 3rd semiconductor chip 2D-2F Semiconductor chip 10, 10A Internal lead part (wiring connection target area) 11, 11A Die pad part 19, 19A Terminal part (wiring connection target area) 21a to 21d, 21f Electrode W Wire A Semiconductor device intermediate product B Semiconductor device

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 複数の半導体チップがそれらの厚み方向
に重ねられており、かつこれら複数の半導体チップに設
けられている複数の電極がそれらの側方に位置する配線
接続対象領域に複数本のワイヤを介して接続されてい
る、半導体チップの実装構造であって、 上記配線接続対象領域のワイヤボンディング面は、上記
複数の電極のうち、最も高い位置の電極と最も低い位置
の電極とのそれぞれの表面の中間の高さに設けられてい
ることを特徴とする、半導体チップの実装構造。A plurality of semiconductor chips are stacked in a thickness direction thereof, and a plurality of electrodes provided on the plurality of semiconductor chips are arranged in a wiring connection target region located on a side of the plurality of semiconductor chips. A semiconductor chip mounting structure connected via wires, wherein a wire bonding surface of the wiring connection target region is a highest electrode and a lowest electrode of the plurality of electrodes, respectively. A mounting structure for a semiconductor chip, wherein the mounting structure is provided at an intermediate height of the surface of the semiconductor chip. 【請求項２】 上記ワイヤの両端のボンディングは、電
極側がファーストボンディングとされているとともに、
配線接続対象領域側がセカンドボンディングとされてい
る、請求項１に記載の半導体チップの実装構造。2. The bonding at both ends of the wire includes a first bonding on an electrode side,
2. The semiconductor chip mounting structure according to claim 1, wherein the wiring connection target area side is second-bonded. 【請求項３】 上記複数の半導体チップは、リードフレ
ームのダイパッド部上に実装されているとともに、この
リードフレームの上記ダイパッド部の側方に位置する内
部リード部が上記配線接続対象領域とされており、かつ
上記内部リード部は、上記ダイパッド部よりも高い位置
に設けられている、請求項１または２に記載の半導体チ
ップの実装構造。3. The semiconductor chip is mounted on a die pad portion of a lead frame, and an internal lead portion of the lead frame located on a side of the die pad portion is set as the wiring connection target region. 3. The semiconductor chip mounting structure according to claim 1, wherein said internal lead portion is provided at a position higher than said die pad portion. 【請求項４】 請求項１ないし３のいずれかに記載の半
導体チップの実装構造を有していることを特徴とする、
半導体装置。4. A semiconductor chip mounting structure according to claim 1, wherein:
Semiconductor device.
JP9297428A 1997-10-06 1997-10-29 Mounting structure for semiconductor chip and semiconductor device Pending JPH11135537A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP9297428A JPH11135537A (en) 1997-10-29 1997-10-29 Mounting structure for semiconductor chip and semiconductor device
US09/166,260 US6441495B1 (en) 1997-10-06 1998-10-05 Semiconductor device of stacked chips
US10/122,982 US6861760B2 (en) 1997-10-06 2002-04-11 Semiconductor device with stacked-semiconductor chips and support plate
US11/032,840 US7242100B2 (en) 1997-10-06 2005-01-10 Method for manufacturing semiconductor device with plural semiconductor chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9297428A JPH11135537A (en) 1997-10-29 1997-10-29 Mounting structure for semiconductor chip and semiconductor device

Publications (1)

Publication Number Publication Date
JPH11135537A true JPH11135537A (en) 1999-05-21

Family

ID=17846394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9297428A Pending JPH11135537A (en) 1997-10-06 1997-10-29 Mounting structure for semiconductor chip and semiconductor device

Country Status (1)

Country Link
JP (1) JPH11135537A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010064907A (en) * 1999-12-20 2001-07-11 마이클 디. 오브라이언 wire bonding method and semiconductor package using it
US6617688B2 (en) 2001-03-27 2003-09-09 Nec Electronics Corporation Semiconductor device and flat electrodes
US6664643B2 (en) 2000-05-11 2003-12-16 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
US7170158B2 (en) 2001-06-29 2007-01-30 Samsung Electronics Co., Ltd. Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010064907A (en) * 1999-12-20 2001-07-11 마이클 디. 오브라이언 wire bonding method and semiconductor package using it
US6664643B2 (en) 2000-05-11 2003-12-16 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
US6617688B2 (en) 2001-03-27 2003-09-09 Nec Electronics Corporation Semiconductor device and flat electrodes
US7170158B2 (en) 2001-06-29 2007-01-30 Samsung Electronics Co., Ltd. Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture

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