JPH11109914A - Flasm display panel driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of light emission by constituting trickle discharge performed by the number of specified times for obtaining optical luminance between first and second electrodes with a first discharge of the main external applied voltage and a second discharge of the main wall charge. SOLUTION: An overall write-in pulse Pxp is applied to a first row electrode X. Since this pulse is a high voltage, a discharge is started between the first row electrode X and a second row electrode Y, and massive wall charges are generated. Then, in trickle period, display luminance is obtained by discharging a display cell selected in an address period by the number of specified times. In such a case, the trickle discharge performed by the number of specified times for obtaining the optional luminance is composed of the first discharge of the main external applied voltage and the second discharge of the main wall charge. At this time, a trickle pulse Sp is set in < the voltage that the cell not discharging between the first row electrode X and the second row electrode Y in the address period starts to discharge, and in >= the voltage that the cell discharging in the address period continues to discharge.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC plasma display panel (hereinafter referred to as an AC-PDP), and more particularly to a method of driving a surface discharge type AC-PDP.

[0002]

2. Description of the Related Art As is well known, a plasma display panel has a structure in which minute discharge cells (pixels) are formed between two glass plates, and has been variously studied as a thin television or display monitor. One known type is an AC-type plasma display panel (AC-PDP) having a memory function. As one of AC-PDPs, there is a surface discharge type AC-PDP. FIG. 14 is a perspective view showing the structure of a surface discharge type AC-PDP.
922 and JP-A-7-287548. In the figure, reference numeral 1 denotes a surface discharge type plasma display panel, 2 denotes a front glass substrate serving as a display surface, and 3 denotes a rear glass substrate which is arranged to face the front glass substrate 2 with a discharge space therebetween. 4 and 5 were coated in the first row electrodes X ₁ to X _n and the second row electrodes Y ₁ to Y _n, 6 on these row electrodes which are formed so as to be paired with each other on a front glass substrate The dielectric layer 7 is MgO (magnesium oxide) formed on the dielectric layer by a method such as vapor deposition. 8 is a rear column electrodes W ₁ is formed to a glass substrate orthogonally to the row electrodes to _W-m, 9 phosphor layer formed on the column electrodes, red respectively for each column electrode, green, blue Phosphor layers that emit light are provided in stripes in order. Reference numeral 10 denotes a partition formed between the column electrodes. The partition has a role of separating the discharge cells and also a role of a column for preventing the PDP from being crushed by the atmospheric pressure. In the space between the glass substrates, a discharge gas such as a Ne-Xe mixed gas or a He-Xe mixed gas is sealed at a pressure lower than the atmospheric pressure, and a discharge cell at an intersection of a row electrode and a column electrode orthogonal to each other is formed as a pixel. Become. Hereinafter, the first row electrode may be called an X electrode, the second row electrode may be called a Y electrode, and the column electrode may be called a W electrode.

In an AC-PDP shown in FIG. 15, a first row electrode 4 and a second row electrode 5 are covered with a dielectric layer 6, and a voltage pulse is alternately applied between the two row electrodes during display. , A discharge whose polarity is inverted every half cycle is caused to cause the cell to emit light. In the color display, the phosphor layer 9 formed in each cell is excited by ultraviolet light from discharge to emit light. Since the first row electrode 4 and the second row electrode 5 for performing the discharge for display are covered with the dielectric layer 6, once a discharge occurs between the electrodes of each cell, the electrons generated in the discharge space are generated. And ions move in the direction of the applied voltage and accumulate on the dielectric layer 6. The charges such as electrons and ions accumulated on the dielectric layer are called wall charges. The electric field formed by the wall charges acts in a direction to weaken the applied electric field, and thus the discharge is rapidly extinguished with the formation of the wall charges. After the discharge is extinguished, when an electric field whose polarity is inverted to that of the previous discharge is applied, the electric field formed by the wall charges and the applied electric field are superimposed in a direction in which the applied electric field is added. And discharge is possible.
Thereafter, the discharge can be maintained by inverting the low voltage every half cycle. Of course, in the steady state, the wall charge amount depends on the externally applied voltage value, and no wall charge higher than the externally applied voltage can be formed. Therefore, it can be said that the wall voltage is working as an auxiliary to the effective voltage for the discharge applied to the cell, although the externally applied voltage is mainly used. Here, this discharge at the rise of the voltage pulse is called "discharge mainly composed of an externally applied voltage". On the other hand, when the externally applied voltage is very high, the wall charges to be formed may be higher than the discharge starting voltage. At this time, at the fall of the voltage pulse, discharge is performed only by the wall charges. This discharge that occurs when no external voltage is applied may be called a self-erasing discharge. Here, a discharge in which an effective voltage mainly includes wall charges and an externally applied voltage acts as an assist, including a case where a voltage is externally applied, is referred to as “mainly wall charge discharge”.

[0004] In addition, a wall charge is formed when lighted once, and a discharge maintained at a low applied voltage thereafter is called a sustain discharge, and is applied to the first row electrode 4 and the second row electrode 5 every half cycle. The applied voltage pulse is called a sustain pulse. This sustain discharge is continued as long as the sustain pulse is applied, until the wall charges disappear. Eliminating the wall charges is called erasing, and first forming the wall charges on the dielectric is called writing.

Writing is performed for an arbitrary cell on the screen of the AC-PDP, and thereafter, by performing a sustain discharge, characters, figures, images, etc. can be displayed. In addition, writing, sustaining discharge, and erasing can be performed at high speed. By
Moving images can also be displayed. When performing gradation display,
This can be performed by controlling the time for emitting light in the sustain discharge.

[0006] Charged particles generated in the discharge space (herein, electrons, ions, and excitables are collectively referred to) have the effect of increasing the discharge probability in the next discharge and reducing the discharge starting voltage. In the case of DC-type PDP, for example,
As shown in Japanese Patent No. 274339, an auxiliary discharge cell is provided adjacent to the display cell, and an auxiliary discharge is generated in the auxiliary discharge cell to lower the write voltage of the display cell and increase the discharge probability. Further, the sustain discharge is performed immediately after the write discharge, and the discharge can be performed at a low applied voltage because the charged particles are present and the discharge start voltage is reduced. In order to stop the discharge, it is only necessary to provide a pause period for eliminating charged particles in the sustain pulse, and it is not necessary to perform an erasing operation for eliminating wall charges as in the AC type PDP. The lifetime of charged particles depends on the gas pressure, gas type, and cell structure, but is about 10 to 10.
It is about 20 μsec. The memory function of the DC PDP using such charged particles is called a pulse memory.

FIG. 16 is a diagram showing a voltage waveform in one subfield of a conventional method for driving a plasma display panel disclosed in Japanese Patent Application Laid-Open No. 7-160218, for example. One subfield is composed of a reset period for erasing the display history, an address period for selecting a cell to be displayed, and a sustain period for obtaining a luminance required to discharge a specified number of times. The voltage waveforms in the figure are column electrodes W in order from the top.
_j, first row electrodes X, a second row electrodes Y _1, Y _2, the applied voltage waveform of the Y _n.

First, in the reset period, an entire-surface write pulse Pxp is applied to the first row electrodes X commonly connected to all the screens in FIG. This entire write pulse Px
p may be called a priming pulse. Since this full write pulse Pxp is set to be equal to or higher than the discharge starting voltage between the first row electrode X and the second row electrode Y and is applied for a sufficiently long time of about 10 μsec, the light emission / non-light emission of the previous subfield is performed. , All cells discharge and emit light. At this time, the voltage pulse Pwp is also applied to the column electrode W, but this reduces the potential difference between the X-W electrodes so as to make it difficult for discharge to occur between the first row electrode X and the column electrode W. And set to a value of about 1/2 of the voltage between the XY electrodes. When the entire surface write pulse Pxp is applied, a strong discharge occurs between the X and Y electrodes, and a large amount of wall charges are accumulated between the X and Y electrodes, and the discharge ends. Next, when the full write pulse Pxp falls in b in the figure and the applied voltage to the first row electrode X and the second row electrode Y disappears, the previous full write pulse Pxp is accumulated between the XY electrodes. An electric field due to wall charges remains. Since this electric field exceeds the discharge starting voltage, a self-erasing discharge occurs, and the wall charges disappear.

As described above, regardless of the presence / absence of the wall charge in the previous subfield, writing and erasing of all the cells allows the wall charge of the cell of the entire screen to be “absent”.
And the reset is performed.

At the end of the reset period, at time c in the figure, a negative charge remains on the first row electrode X, and a slight positive charge remains on the second row electrode Y. The remaining amount depends on the characteristics of the cells. A small amount of cells are left in a cell having a low firing voltage (cells that are easy to light), and a large amount of wall charge is left in a cell having a high discharge firing voltage (cells that are difficult to light). This works in the direction to alleviate the cell variation when the next lighting is performed. In the discharge cell, the previous entire write pulse Px
A small amount of charged particles generated by the discharge due to p remains. These charged particles no longer have the effect of lowering the above-mentioned starting voltage, and serve to ensure the discharge in the next writing. That is, it becomes a seed for writing discharge. This is the reason why the entire-surface write pulse Pxp is called a priming pulse. Therefore, this method, which combines the priming effect and the erasing effect with one pulse and has a "self-adjustment function" for absorbing cell variations after erasing, is quite good for stably operating the plasma display panel. It is a method. Since this priming effect has a time constant of several milliseconds, the entire write pulse Pxp is applied once to several subfields, and an erase pulse having a narrow pulse width or a low voltage value is applied to the remaining subfields. Alternatively, only the cells lit in the previous subfield may be discharged and erased. Japanese Unexamined Patent Publication No. Hei 8-278766 discloses that a narrow pulse is applied at the same voltage as the priming pulse by utilizing the fact that the discharge delay time is different between the cell that was lit in the previous subfield and the cell that was not lit. A method for reducing the number of lighting times and improving the contrast is shown.

In the address period, a negative scan pulse Scyp is sequentially applied to the independent second row electrodes Y1 to Yn to perform scanning. On the other hand, a positive address pulse Awp is applied to the column electrode W according to the content of the image data.
The scan pulse Scy applied to the second row electrode Y
An arbitrary cell on the screen can be matrix-selected by p and the address pulse Awp applied to the column electrode W. Since the total voltage value of the scan pulse Scyp and the address pulse Awp is set to be equal to or higher than the discharge starting voltage between the Y-W electrodes of the cell, the cell to which the scan pulse Scyp and the address pulse Awp are simultaneously applied is the Y-W electrode Discharge occurs between the two. During the address period, the common first row electrode X is maintained at a positive voltage value. Although this voltage value does not discharge between the X and Y electrodes even when summed with the voltage value of the scan pulse Scyp, when a discharge occurs between the Y and W electrodes, this discharge is used as a trigger and at the same time, between the X and Y electrodes. However, the voltage value is set so that discharge occurs. The discharge between the X and Y electrodes that is triggered by the discharge between the Y and W electrodes may be referred to as a write sustain discharge. By this write sustaining discharge, wall charges are accumulated on the first and second row electrodes.

After the scanning of the entire screen in the address period is completed, the sustain pulse Sp is applied to the entire screen all at once, and the sustain discharge is performed only in the cells addressed in the address period and storing the wall charges. Then, the next subfield again starts, and in the reset period, the entire surface write pulse Pxp is applied to all cells, and reset is performed.

As described above, the driving method for separating the address period and the sustain discharge period over the entire screen of the AC-PDP is called an "address / sustain separation method". is there.

Next, the efficiency of AC-PDP will be described.
Fig. 17 shows the latest technology of plasma display (Mikoshiba:
ED Research, 1996), showing the relationship between current density and luminous efficiency. It is a well-known fact that reducing the current density improves the efficiency.
As a method of lowering the current density, a method of lowering the driving voltage and a method of forcibly reducing the externally applied voltage before the discharge is completed (before the discharge current flows) are known. For the former, for example, as shown in JP-A-3-219528 (FIG. 18), a method is known in which an auxiliary electrode is used in front of a main electrode, and the voltage of the main electrode is reduced by the discharge of the auxiliary electrode as a trigger. I have. The latter is sometimes called Townsend discharge. For example, in JP-A-7-134565, after the first pulse during the sustain period is lengthened to stabilize the discharge, a very narrow pulse is applied after the second pulse, and the pulse rises before the end of the discharge current. The current density is lowered by lowering it. In addition to these methods, it can be considered that the wall charge is reduced by performing a self-erasing discharge, and the effective voltage (applied voltage + wall charge) is reduced. FIG. 19 is a diagram showing the relationship between the externally applied voltage and the efficiency. The voltage value varies depending on the structure of the panel, the type of gas to be filled, and the type of gas. However, a PDP having a structure in which electrodes are covered with a dielectric can qualitatively obtain the same characteristic line. It can be seen that the efficiency decreases with increasing voltage on the low voltage side and that the efficiency increases on the high voltage side. This rise on the high voltage side is a region where self-erasure has occurred.

Japanese Patent Application Laid-Open No. 8-314405 discloses an apparatus utilizing self-erasing discharge during the sustain discharge period.
FIG. 20 is a voltage waveform diagram at that time. This method is used in a steady state where the discharge start voltage is not affected by charged particles, etc., accumulates sufficient wall charges equal to or higher than the discharge start voltage during the voltage application period, and between the pulses during the sustain period (hereinafter, referred to as This is a method in which a self-erasing discharge is generated during the idle period by setting the idle period) to the ground state. During the idle period, since no externally applied voltage is present, charged particles are not attracted to the display electrode and there is no ion bombardment.
It is characterized by obtaining twice the number of times of light emission. Furthermore, the self-erasing discharge used here controls the self-erasing discharge by reducing the pulse width to reduce the amount of accumulated wall charge, so that the self-erasing discharge does not occur, and when the applied voltage is reduced, the self-erasing discharge does not occur. This is useful for gradation display.

[0016]

In order to improve the efficiency by improving the driving method, it is necessary to use the vicinity of the lower limit or the upper limit of the margin as shown in FIG. In a low voltage region, there is a possibility that a cell to be lit cannot be lit, and in a high voltage region (self-erasing region), a cell which is supposed to be non-lit may be lit. To create a panel with a wide margin (good yield) in consideration of the mass productivity of the actual PDP, an operating point must be selected near the middle of the margin, resulting in the use of a very inefficient area. You are doing.

The self-erasing discharge obtained by applying a high voltage pulse causes a discharge not only between the X and Y electrodes but also with the W electrode because of the high voltage. If self-erasing discharge is not used, even if a discharge occurs once with the W electrode, W
The wall charge on the electrode becomes a mask and cannot be AC driven. Therefore, no discharge occurs again. However, if the self-erasing discharge is used, the W electrode and the wall charge discharged at the rising edge are discharged again at the falling edge and disappear, so that the discharge continues. Discharge with the W electrode not only causes erroneous addressing, but also causes phosphor degradation by using the phosphor as a cathode (causing spattering).

Further, driving at a high voltage has a problem that the loss of a circuit proportional to the square of the voltage increases with respect to a capacitive load such as a PDP.

Further, even if the self-erasing discharge is actively used, since the electrode is in the ground state during the idle period, the discharge generated at the fall of the applied pulse can be discharged only by the wall charge. Inevitably, the intensity of the discharge was limited.

There is also a problem with the conventional driving method for obtaining a high contrast. In order to obtain a high contrast, for example, the entire surface is lit once every several subfields, and only the cells lit in the previous subfield are turned on and erased in the remaining subfields, as described in the related art. . At this time, if the "self-adjustment function" of the self-erasing discharge is used, the pulse width must be narrowed. It lights up. In addition, since some cells discharge halfway, the discharge ends before the wall charges that can be self-erased accumulate, resulting in erroneous discharge. When erasing without using the self-erasing discharge (for example, narrow width erasing) is used, the state of the remaining wall charge differs between a subfield that has been fully lit and a subfield that has not been lit, and the operation margin differs for each subfield.

The present invention has been made in order to solve such a problem, and the falling discharge mainly caused by wall charges, which has conventionally been caused by applying a high voltage, is reduced to a low voltage.
By maximizing the PDP efficiency, the efficiency of the PDP is improved without increasing the circuit loss and without reducing the margin.

Further, the present invention prevents a discharge from being caused between the W electrode and the sustain electrode by using a self-erasing pulse during the sustain period.

Further, by using the discharge mainly composed of wall charges for erasing, the operating points of the subfield using full lighting and the subfield not using it are equalized, and the "self-adjustment" of the discharge mainly composed of wall charges is achieved. The function is used to reduce the variation of the cells.

[0024]

According to a first aspect of the present invention, there is provided a driving method of a plasma display in which a sustain discharge which is performed a specified number of times to obtain an arbitrary luminance is generated as a first discharge mainly composed of an externally applied voltage. The second discharge mainly includes wall charges.

In the driving method of the plasma display according to the second configuration of the present invention, the second discharge in the sustain discharge utilizes charged particles generated in the first discharge and is generated at a low discharge starting voltage. It was done.

Further, in the driving method of the plasma display according to the third configuration of the present invention, the sustain discharge itself is maintained in a state where the discharge starting voltage by the charged particles is low.

Further, in the driving method of the plasma display according to the fourth configuration of the present invention, the pulse width of the sustain discharge pulse is specified to be 1.6 μsec or less.

In the driving method of a plasma display according to the fifth configuration of the present invention, the pulse of the sustain discharge pulse and the pause period of the pulse are specified to be 0.8 μsec or more.

Further, in the driving method of the plasma display according to the sixth configuration of the present invention, the fall of the sustain discharge pulse is further specified to be 300 nsec or less.

Further, in the driving method of the plasma display according to the seventh aspect of the present invention, the sustain discharge which is performed a specified number of times to obtain an arbitrary luminance is mainly performed by the first discharge mainly composed of an externally applied voltage and the generated wall charges. And a second discharge,
At the end of the second discharge, an auxiliary pulse is applied in a direction in which the second discharge is positively used until the polarity of the remaining wall charge does not reverse.

Further, in the driving method of the plasma display according to the eighth configuration of the present invention, the auxiliary pulse is formed to be negative with respect to the GND level at the fall of the sustain pulse.

Further, in the driving method of the plasma display according to the ninth configuration of the present invention, the auxiliary pulse forms the other electrode positively with respect to the GND level at the fall of the sustain pulse.

Further, the driving method of the plasma display according to the tenth configuration of the present invention is divided into an address period for arbitrarily selecting a cell and a sustain period for discharging the selected cell simultaneously for a specified number of times. Things.

Further, the driving method of the plasma display according to the eleventh configuration of the present invention is characterized in that the third period is maintained during the above-mentioned sustain period.
Are allowed to have a time during which the electrodes are in a floating state.

Further, the driving method of the plasma display according to the twelfth structure of the present invention includes the first discharging and the second discharging.
Is used as an erase pulse.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. An embodiment of the present invention will be described with reference to the drawings. The panel used may be a conventional panel similar to FIG. FIG. 1 is a voltage waveform (timing chart) showing a method of driving a plasma display panel according to Embodiment 1 of the present invention. In the figure, the voltage waveforms are shown in order from the top, with a column electrode Wj, a first row electrode Xi, Second row electrode Yi
3 is a voltage waveform applied to the first embodiment. Pxp is a priming pulse (full-surface write pulse) applied to the Xi electrode for performing full-surface writing and erasing, and Pwp is a pulse applied to the Wj electrode at the same timing. These may be applied once to several subfields, but may be applied to all subfields. Sp is a sustain pulse for performing sustain discharge, Scyp is a scan pulse for scanning, Awp
Is an address pulse applied according to the display data content. In the present embodiment, for example, the priming pulse Pxp has a pulse width of 7 μsec, a voltage of 310 V, Pw
p is set to 150 V, sustain pulse Sp is set to 180 V, scan pulse Scp is set to -180 V, and address pulse Awp is set to 60 V. Although no special pulse for erasing is applied here, erasing may be achieved by applying a narrow pulse or the like as in the conventional driving method.

Next, the operation will be described. First, in the reset period at the beginning of one subfield, the entire-surface write pulse Pxp is applied to the first row electrodes X commonly connected to all the screens. Since this pulse has a high voltage of 310 V, discharge is started between the first row electrode X and the second row electrode Y, and a large amount of wall charges are generated. Thereafter, at the falling edge of Pxp, the discharge is performed again using only the generated accumulated wall charges. However, since there is no externally applied voltage, after this discharge,
No reverse charge is formed, only the amount of wall charge is reduced.
When the reset period ends, the operation enters the address period. The negative scan pulse S is sequentially applied to the independent second row electrodes Y _{1 to} Y _n.
An address pulse Awp corresponding to the image data is applied to the column electrode Wj at the same time as the cyp is applied, and the displayed cells are discharged in a matrix. At this time, the discharge between the X and Y electrodes is triggered by the discharge between the Y and W electrodes, thereby forming wall charges on the X and Y electrodes.

In the sustain period, display luminance is obtained by discharging the display cells selected during the address period a specified number of times. Here, the sustain pulse Sp is lower than the voltage at which the cells that did not discharge during the address period between the first row electrode X and the second row electrode Y start discharging, and the cells that discharge during the address period continue discharging. It is set higher than the voltage that can be used. FIG. 2 is a diagram showing a voltage waveform and a light emission waveform applied during the sustain period. Note that each condition in FIG. 2 does not need to have all of them, and each has an independent meaning as described later. At the rise of the applied pulse, the effective voltage, which is the sum of the wall charge and the externally applied voltage, becomes equal to or higher than the discharge starting voltage, and discharge occurs. At this time, the wall charges of the opposite polarity accumulate and the discharge ends. The wall charge amount at this time depends on the externally applied voltage, and is not formed above the externally applied voltage. At the falling edge of the pulse, the externally applied voltage becomes 0 V, and an electric field due to wall charges remains in the discharge space. At this time, the discharge can be performed again by setting the wall charge to be equal to or higher than the discharge starting voltage. Unlike the first discharge that occurs at the rise of the pulse, the second discharge at the fall of the pulse does not accumulate wall charges of the opposite polarity, but simply reduces the amount of wall charges to the discharge start voltage or less. FIG. 3 is a diagram showing a pulse width and a sustain voltage value at which the second discharge starts. In the region where the pulse width is wide, the applied voltage required to generate the second discharge is approximately 21.
It is around 0V. However, it can be seen that in the region where the pulse width is narrow, the self-erasing discharge is more likely to occur because the charged particles generated by the first discharge lower the firing voltage. For example, if the set pulse width is 3 μsec, 185
By applying a voltage of V or more, self-erasing discharge can be used.
Self-erasing discharge can be used at a voltage of 0 V or more. As described above, if the region in which charged particles by the first discharge can be used, that is, the left side of the self-erase start voltage curve is used, the discharge start voltage Vf is not a high voltage self-erase region conventionally used in FIG. A self-erasing discharge can be caused in a transition period before the state is reached. If a low-voltage self-erasing discharge using charged particles after the end of the first discharge is used, there is no possibility of causing unnecessary discharge with the W electrode and no increase in circuit loss.

In order to confirm the difference between the self-erasing discharge according to the present invention and the conventionally used self-erasing discharge,
The pulse width may be widened with the same driving voltage. For example, in this embodiment, the falling light emission observed when the Sp voltage is driven at 180 V and the pulse width is 1.6 μsec can no longer be observed if the pulse width is 4 μsec at the same voltage.

Further, the distinction from the narrow pulse sustaining discharge such as the Townsend system which has been conventionally proposed may be made by observing the light emission at the falling edge. In the above-described narrow pulse sustain discharge, discharge cannot occur again at the fall due to the concept that the pulse falls before the end of the discharge current (before the end of wall charge formation).

In the region of 1.6 μsec or less in FIG. 3, the second discharge has already occurred near the lower limit voltage of the maintenance margin, and it was not possible to independently generate only the first discharge. Since it is difficult to manufacture a panel in which the operating points of the cells do not vary, it is desirable to select a region where the second discharge occurs reliably over the entire margin. Although this condition slightly varies depending on not only the panel but also the sealing gas pressure and the gas type, a uniform result can be obtained in a discharge region usable as a PDP. From FIG. 3, it can be said that it is 1.6 μsec or less. This value can be confirmed as a critical point when observing whether or not the second discharge occurs near the lower limit of the margin.

FIG. 4 shows the relationship between the pulse width and the efficiency when the pulse interval (pause period) is changed by setting the pulse width to 1 μsec. The second discharge at the falling edge of the pulse is affected by the idle period, and in the state where there is almost no idle period, the second discharging at the falling overlaps with the discharging at the rising edge of the next pulse. Considering the discharge delay of the falling discharge, the longer the pause period is, the better, but a high voltage is required to maintain the discharge. Taking into account the statistical delay until the discharge occurs and the formation delay from the start to the end of the discharge, it can be said that 0.8 μsec or more is necessary. This value varies slightly depending on the cell structure as in FIG.
A uniform result can be obtained in the discharge region usable as DP. Note that this value can be obtained, for example, as a saturation point when the pause period is increased under a constant pulse width condition.

FIG. 5 is a diagram showing the relationship between the falling speed of the pulse and the luminous efficiency. Here, the falling speed is defined as the time required to change from the 90% voltage value of the pulse to the 10% voltage value. The second discharge at the falling of the pulse depends on the falling speed and needs to fall earlier than the statistical delay time of the discharge. If the second discharge occurs in the middle of the fall of the pulse, the applied voltage acts in the direction of lowering the effective voltage, so that the second discharge becomes smaller.
The second discharge cannot be used effectively. From FIG. 5, this value can be read as 300 nsec or less. This value also varies slightly depending on the cell structure, but almost the same result is obtained in a region usable as a PDP. The characteristic value can be obtained as a changing point by changing the falling speed.

FIG. 6 shows the relationship between the voltage and the efficiency when the frequency is changed based on the above findings. As shown in FIG. 19, when the voltage is low, the current density can be reduced and the efficiency can be improved. When the voltage is high, the effective voltage decreases due to self-erasing discharge, and the same effect as the low voltage can be expected. it can. It can be seen from the figure that the higher the frequency, the higher the efficiency at the same voltage. this is,
The lower self-erase start voltage means that the self-erase effect conventionally obtained at a high voltage is shifted to a lower voltage side. Further, even if the frequency is changed, the margin hardly changes, so that the operating point can be selected at the center of the margin and the effect of improving the luminous efficiency by the self-erasing discharge can be obtained. In addition, since a large amount of wall charge remains in cells that are difficult to discharge after self-erasing discharge, and a small amount of wall charge remains in cells that easily discharge, the first discharge when the next pulse is applied This has the effect of making the starting conditions uniform and stabilizing the discharge.

In selecting the driving conditions, the sustain discharge can be set to a condition utilizing the memory effect of charged particles. That is, there is a region where the discharge cannot be sustained if the idle period is set long under the conditions of the same voltage, the same pulse width, and the same falling speed. This is because the effect of reducing the discharge start voltage of the charged particles during the rest period was lost.
FIG. 3 shows the change in the second discharge start voltage caused by the first discharge at the rising edge, and this fact also means the change in the discharge start voltage given to the next sustain discharge by the sustain discharge. From the figure, this effect can be estimated to be about 4 μsec. If the memory effect of charged particles is used as in the case of the pulse memory in the DC type PDP, it is possible to maintain the voltage at a low voltage. Conversely, if the application of the pulse is stopped, the discharge cannot be sustained, so that the operation of erasing, which was conventionally required for stopping the discharge in the AC-type PDP, becomes unnecessary. Further, conventionally, it has been difficult to use the self-adjustment function of the self-erasing discharge to align operating points between a subfield to which a full-field lighting pulse is applied and a subfield to which no subfield is applied, but the second discharge is used. Thus, if this sustain pulse also used for erasing is used, the same self-erasing is used after the end of the sustain pulse and after the end of the full lighting pulse, so that an effect of replacing the full lighting pulse can be obtained.

In this embodiment, the "address / maintenance separation method" is used.
However, it goes without saying that the same effect can be obtained without using the address / sustain separation method. However, if the address / sustain separation method is used, the conditions of the sustain pulse (pulse width, pause period, fall speed) can be easily selected.

Embodiment 2 Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a voltage waveform (timing chart) showing a driving method of the plasma display panel according to the embodiment of the present invention, and is an enlarged view in a sustain period. The reset period and the address period are the same as in the first embodiment. In the figure, the sustain pulse applied to the positive side is lowered to the negative level at the fall. In the self-erasing discharge in the first embodiment, when the externally applied voltage is 0 V, the self-erasing discharge is performed again by an electric field generated by wall charges. Therefore, after the discharge is completed, wall charges of the opposite polarity are not formed, and wall charges of the same polarity remain. According to the present embodiment, the effect of the self-erasing discharge can be further obtained by superimposing the externally applied voltage on the direction of the electric field generated by the wall charges at the falling of the pulse. Here, the pulse superimposed on the self-erasing discharge is called a self-erasing auxiliary pulse. It is desirable that the voltage of the self-erase auxiliary pulse be higher, but wall charges of the opposite polarity must not be accumulated because of the side effect of lowering the margin. Preferably, the wall charge becomes 0 after the discharge of the self-erasing auxiliary pulse is completed.
The setting value is set to V.

FIG. 8 is a diagram showing a voltage waveform and a light emission waveform when a self-erasing auxiliary pulse is applied, and FIG. 9 is a Lissajous diagram at that time. This Lissajous diagram is, for example, AC-
It can be measured by connecting a measuring capacitor in series with the PDP. By taking the externally applied voltage on the horizontal axis and the amount of charge on the vertical axis, you can know how much charge moves before and after the end of discharge. be able to. It can be seen from the figure that the emission at the falling edge is stronger than that of the normal self-erasing discharge, and that the wall charge after the discharge is small. Since the area in the Lissajous figure is the power applied to the panel, in order to reduce the power applied per discharge and improve the luminous efficiency, which is the object of the present invention,
It is desirable to reduce the area of the Lissajous figure as much as possible. In FIG. 9, since the externally applied voltage is under the same condition, it is obvious that the self-erase assist pulse has an effect of further reducing the effective voltage. Note that the luminance decreases as the input power decreases, but the target luminance can be obtained by increasing the number of times of discharge of the sustain pulse (by increasing the average frequency).

FIG. 10 shows the relationship between the voltage and the luminous efficiency when a self-erasing auxiliary pulse is further applied under the sustain pulse condition of the maximum luminous efficiency obtained in the first embodiment. It can be seen from the comparison with FIG. 4 that an efficiency even higher than that of the drive using the self-erasing discharge can be obtained.

Embodiment 3 FIG. 11 is a diagram showing a state in which the self-erasing auxiliary pulse according to the second embodiment is applied to another electrode. According to the present embodiment, the efficiency of self-erasing discharge can be improved as in the second embodiment.

In the second embodiment, since the electrode to which the voltage is applied is lowered to the minus level, the falling speed of the pulse can be changed relatively easily, which is advantageous for discharge design such as reducing erroneous discharge. is there. Further, in the third embodiment, since the electrode opposite to the electrode to which the voltage is applied is at the positive level, the circuit configuration can be simplified without using a negative power supply.

Embodiment 4 FIG. FIG. 12 shows the fourth embodiment and explains the potential of the W electrode during the sustain period in the address / sustain separation method. If the potential of the W electrode is set to a fixed potential, the W electrode may discharge with the X electrode or the Y electrode during the sustain period depending on the set voltage value. If the self-erasing discharge is not caused at the falling edge of the pulse, even if the discharge occurs with the W electrode, the wall charges accumulate on the W electrode and become a masked state, so that the subsequent discharge is hardly affected. Conversely, when a self-erasing discharge occurs, the wall charges accumulated on the W electrode at the rising edge of the pulse disappear by the discharge at the falling edge of the pulse, so that the discharge with the W electrode continues. Therefore, in order to suppress discharge to the W electrode, the W electrode may be set to a floating state instead of a fixed potential. This can be easily made by, for example, turning off the gate signal of the FET in the circuit configuration shown in FIG. Of course, a pulse may be applied so as to take an intermediate potential between the X and Y electrodes.

In the present embodiment, all the times during the sustain period are floating. However, until the beginning of the sustain period (for example, several pulses), the potential is fixed to stabilize the discharge. Good.

[0054]

Since the present invention is configured as described above, it has the following effects.

According to the driving method of the plasma display panel of the first configuration of the present invention, the sustain discharge performed a specified number of times between the first and second electrodes to obtain an arbitrary luminance is performed mainly by an externally applied voltage. By using the first discharge and the second discharge mainly composed of wall charges, luminous efficiency can be improved.

According to the plasma display panel driving method of the second configuration of the present invention, the second discharge is generated at a low voltage by using the charged particles generated in the first discharge of the sustain discharge. be able to.

Further, according to the driving method of the plasma display panel according to the third configuration of the present invention, the sustain discharge can be maintained at a low voltage by sustaining the sustain discharge using charged particles.

According to the plasma display panel driving method of the fourth configuration of the present invention, by defining the pulse width of the sustain pulse to be 1.6 μsec or less, the charged particles generated by the first discharge can be discharged. The luminous efficiency can be improved by making better use of the second discharge.

Further, according to the driving method of the plasma display panel of the fifth configuration of the present invention, the second discharge is strengthened and the light emission is performed by specifying the sustain pulse and the pause period of the sustain pulse to be 0.8 μsec or more. Efficiency can be improved.

According to the plasma display panel driving method of the sixth aspect of the present invention, the fall of the sustain discharge pulse is specified to be 300 nsec or less, whereby the second discharge becomes strong and the luminous efficiency is improved. be able to.

According to the plasma display panel driving method of the seventh configuration of the present invention, the sustain discharge is composed of a first discharge mainly composed of an externally applied voltage and a second discharge mainly composed of wall charges. By applying the auxiliary pulse in a direction in which the second discharge is positively used until the wall charge does not reverse at the end of the second discharge, the second discharge can be strengthened and the luminous efficiency can be improved.

Further, according to the driving method of the plasma display panel of the eighth configuration of the present invention, the auxiliary discharge is formed to be negative with respect to the GND level at the fall of the sustain pulse, so that the second discharge is strengthened. The luminous efficiency can be improved.

According to the plasma display panel driving method of the ninth configuration of the present invention, the second electrode is formed positive with respect to the GND level by making the auxiliary pulse fall at the fall of the sustain pulse. And the luminous efficiency can be improved.

According to a tenth aspect of the present invention, there is provided a driving method for a plasma display panel.
In the driving method described in any one of (1) to (9), the sustain pulse during the sustain period is independent of the address period by separating the sustain period in which the selected cell is arbitrarily selected and the sustain period in which the selected cell is simultaneously discharged a specified number of times. Can be easily changed.

Further, according to the driving method of the plasma display panel of the eleventh configuration of the present invention, of the driving methods separated into the address period and the sustain period, the third electrode during the sustain period is in a floating state. The third electrode and the first or the second
Unnecessary discharge with the electrodes can be prevented.

According to the plasma display panel driving method of the twelfth configuration of the present invention, the first
By using the sustain pulse formed from the first discharge and the second discharge as the erase pulse, stable display can be performed without performing a special erase operation.

[Brief description of the drawings]

FIG. 1 is a voltage waveform diagram showing a method for driving a plasma display panel according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a voltage waveform and a light emission waveform during a sustain period in the method of driving the plasma display panel according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a pulse width and a sustain voltage value at which a self-erasing discharge starts.

FIG. 4 is a diagram showing a relationship between a quiescent period and luminous efficiency.

FIG. 5 is a diagram showing a relationship between a pulse falling speed and luminous efficiency.

FIG. 6 is a diagram showing the relationship between voltage and efficiency when the frequency is changed.

FIG. 7 is an enlarged view of a driving voltage waveform of a plasma display panel according to a second embodiment of the present invention and a sustain period.

FIG. 8 is a diagram showing a voltage waveform and a light emission waveform when a self-erasing assistance pulse is applied.

FIG. 9 is a Lissajous diagram when a self-erasing assistance pulse is applied.

FIG. 10 is a diagram illustrating a relationship between a voltage and a luminous efficiency when a self-erasing assist pulse is applied.

FIG. 11 is an enlarged view of a sustain period in a driving voltage waveform of the plasma display panel according to the third embodiment of the present invention.

FIG. 12 is a diagram showing a driving voltage waveform of the plasma display panel according to the fourth embodiment of the present invention.

FIG. 13 is a circuit configuration diagram of a W electrode of a plasma display panel for describing Embodiment 4 of the present invention.

FIG. 14 is a perspective view showing a structure of a surface discharge type AC-PDP.

FIG. 15 is a cross-sectional view of an AC-PDP cell.

FIG. 16 is a diagram showing voltage waveforms in one subfield of the conventional plasma display panel driving method disclosed in Japanese Patent Application Laid-Open No. 7-160218.

FIG. 17 is a diagram showing a relationship between current density and luminous efficiency.

FIG. 18 is a cross-sectional view of an AC-type battery disclosed in JP-A-3-219528.
FIG. 2 is a structural diagram of a PDP.

FIG. 19 is a diagram showing a relationship between an externally applied voltage and luminous efficiency.

FIG. 20 is a diagram showing voltage waveforms in the driving method disclosed in Japanese Patent Application Laid-Open No. 8-314405.

[Explanation of symbols]

Reference Signs List 1 plasma display panel or cell, 2 front glass substrate, 3 back glass substrate, 4 first row electrode (X electrode), 5 second row electrode (Y electrode), 6 dielectric layer, 7 MgO (magnesium oxide) , 8 row electrodes, 9
Phosphor layer, 10 barrier ribs, Pxp priming pulse (full write pulse), Awp address pulse, S
p1 to Sp4 sustain pulse, Scyp scan pulse.

Claims (12)

[Claims] 1. Each cell includes a first electrode and a second electrode covered with a dielectric, and a third electrode provided in a direction intersecting at least one of the first electrode and the second electrode. In a plasma display, a sustain discharge performed a specified number of times to obtain an arbitrary brightness between a first electrode and a second electrode is performed from a first discharge mainly composed of an externally applied voltage and a second discharge mainly composed of generated wall charges. A method for driving a plasma display panel, comprising: 2. The second discharge in the sustain discharge is a first discharge.
2. The driving method for a plasma display panel according to claim 1, wherein charged particles generated by said discharge are used. 3. The driving method of a plasma display panel according to claim 1, wherein said sustain discharge utilizes a memory effect of charged particles. 4. A driving method for a plasma display panel, wherein the pulse width of the sustain discharge pulse according to claim 2 is 1.6 μsec or less. 5. The method of driving a plasma display panel according to claim 2, wherein a pulse for obtaining the first discharge in the sustain discharge and a pause period of the pulse are set to 0.8 μsec or more. 6. The fall of the sustain discharge pulse is set to 3
6. The driving method of a plasma display panel according to claim 1, wherein the driving time is not more than 00 nsec. 7. Each cell includes a first electrode and a second electrode covered with a dielectric, and a third electrode provided in a direction intersecting at least one of the first electrode and the second electrode. For the plasma display, a sustain discharge performed a specified number of times to obtain an arbitrary brightness between the first and second electrodes is performed by a first discharge mainly composed of an externally applied voltage and a second discharge mainly composed of generated wall charges. In the method for driving a plasma display panel including discharge, an auxiliary pulse is applied in a direction in which the second discharge is positively used until the polarity of the remaining wall charge does not reverse at the end of the second discharge. Driving method for a plasma display panel. 8. The driving method of a plasma display panel according to claim 7, wherein the auxiliary pulse is formed to be negative with respect to the GND level at the fall of the sustain pulse. 9. The driving method for a plasma display panel according to claim 7, wherein the auxiliary pulse is formed so that the other electrode is positive with respect to the GND level at the fall of the sustain pulse. 10. The plasma display driving method according to claim 1, wherein an address period for arbitrarily selecting a cell to be displayed and a sustain period for discharging the selected cell at a specified number of times are separated. Item 10. A method for driving a plasma display panel according to any one of Items 9. 11. The driving method of a plasma display panel according to claim 10, wherein said sustaining period has a time during which said third electrode is in a floating state. 12. The driving of the plasma display panel according to claim 1, wherein a sustain pulse formed from the first discharge and the second discharge is used as an erase pulse. Method.