JPH0389563A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a parasitic capacitance based on wirings by allowing part of an n-type silicon epitaxial layer of a predetermined region to remain as an electrode lead layer and forming a silicon oxide film obtained by oxidizing the epitaxial layer substantially in the same thickness as that of the lead layer. CONSTITUTION:An SiO2 film and an SiN film are formed on the surface of a polysilicon 13, and so patterned as to allow them to remain only on the upper part of a deep groove by dry etching. Then, the polysilicon 13 is etched to allow it to remain only in the deep groove. After the SiN film remaining on the surface is removed by dry etching, and the surface is flattened by oxidizing. Then, an SiO2 film 26 and an SiN film 27 are formed on the surface, and desired regions of these films are patterned. With the remaining films 26, 27 as masks phosphorus is diffused to form an n<+>-type layer 15 to become a collector wall of an npn transistor and an n<+>-type layer 16 to become an electrode lead layer of a PIN photodiode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a light receiving element and an electronic element are monolithically formed on the same substrate.

[Conventional technology]

2. Description of the Related Art Optical receiving circuits are conventionally known in which a PIN photodiode is used as a light receiving element and an npn bipolar transistor is used as an electronic element for the signal processing circuit. However, in the conventional circuit, the PIN photodiode and the npn bipolar transistor are formed on separate chips, and are simply connected to each other by wiring on a hybrid IC substrate.

[Problem to be solved by the invention]

However, conventional configurations using hybrid ICs have problems such as large parasitic capacitance due to wiring and difficulty in automating the assembly process, so a monolithic configuration has been desired.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, a semiconductor device of the present invention is a semiconductor device in which a low concentration p-type silicon epitaxial layer is formed on a high concentration p-type silicon semiconductor substrate, and an n-type silicon epitaxial layer is further formed on the low concentration p-type silicon epitaxial layer. In the device, an n-type buried layer is formed in a predetermined surface layer portion of a low concentration p-type silicon epitaxial layer, so that a high concentration p-type semiconductor substrate is formed as a P layer and a low concentration silicon epitaxial layer is formed as one layer. A PIN photodiode is constructed in which an n-type buried layer is an N layer, and an n-type collector layer and a p-type collector layer are formed by doping impurities into an n-type silicon epitaxial layer in the vicinity of the PIN photodiode region.
An npn bipolar transistor is constituted by the silicon layer and the n-type emitter layer, and a part of the n-type silicon epitaxial layer in the PIN photodiode region is left as an electrode extraction layer, and at least the peripheral region of the electrode extraction layer is npn bipolar transistor. A silicon oxide film obtained by oxidizing a type silicon epitaxial layer is formed to have approximately the same thickness as the electrode lead layer.

[Effect]

A PIN photodiode and an npn bipolar transistor can coexist on the same substrate by forming an epitaxial layer with a two-layer structure consisting of a lightly doped p-type epitaxial layer and an n-type epitaxial layer on the highly doped p-type semiconductor substrate. In addition, an electrode extraction layer is created in the PIN photodiode region using the n-type epitaxial layer in which the npn bipolar transistor is formed, and the oxide film around it is approximately the same thickness as the electrode extraction layer, so the PIN photodiode (npn) The entire surface including the transistor and its intermediate region is flat.

〔Example〕

FIG. 1 is a partially sectional perspective view showing an embodiment of the semiconductor device of the present invention, and FIG. 2 is a process sectional view showing the manufacturing process thereof.

First, the manufacturing method will be explained with reference to FIG.

On a high concentration p-type semiconductor substrate 1 with an impurity concentration of about 10 to 1021/c113, an impurity concentration of 1012 to 0 is applied.
A low concentration p-type epitaxial layer 2 of approximately 1014/c113 is formed to a thickness of 30 to 50 μm.

Although not shown, an SiO□ film for preventing autodoping is formed on the back surface of the semiconductor substrate 1 (see FIG. 2(A)). Next, a 5LO2 film 3 is formed on the surface, and the SiO
Process the two films 3. Using the SiOZ film 3 as a mask, boron ions are implanted from above to form a p-well buried layer 4 for an npn transistor. The impurity concentration of this buried layer 4 is about 10 to 1016/cI113 (see FIG. 25(B)). As shown by the position of the p-well buried layer 4, approximately the right half of the figure is the npn transistor formation region, and the left half is the PIN photodiode formation region. Then, the SiO2 film 3 on the surface is processed again using photolithography technology, and the SiO2 film 3 after processing is
Antimony (Sb) is thermally diffused using the O2 film as a mask. As a result, the n-type buried layer 5 for the npn) transistor
And an n-type buried layer 6 for a PIN photodiode is formed.

The impurity concentration of the n-type buried layer 5.6 is 1019 to 1020/
clI3 (see Figure 2 (C)). FIG. 3 shows the profiles of the above-mentioned buried layers 4 to 6, where curve A is the profile of antimony and curve B is the profile of boron. Thereafter, the S io 2 film 3 on the surface is removed, and an n-type epitaxial layer 7 having a thickness of 26 m±0.2 μm is formed.

5 The impurity concentration is about 10 to 1018/cI113 (see FIG. 2(D)). This completes the buried diffusion and epitaxial growth steps.

Next, the separation process will be explained.

SiO3 film 8 and SiN film 9 are formed over the entire surface of n-type epitaxial layer 7. Then, a resist 10 is applied thereon, and the SiO2 film 8 and SiN film 9 in desired areas are removed by etching using photolithography. Thereafter, using the SiO2 film 8 and the SiN film 9 as masks, the n-type epitaxial layer 7 is removed by 0.1% from the surface.
Wet etching to a depth of 0.0 μm. 7
Shallow grooves are formed by anisotropic dry etching to a depth of .mu.m (see FIG. 2(E)). Here, the desired regions include an isolation region of an npn transistor, an isolation region between a p-type base layer and a collector layer to be provided in the future inside an npn transistor, a light receiving region of a PIN photodiode, and the like.

Next, a resist 11 is applied, and only the upper part of the groove provided in the isolation region is removed by photolithography. Then, anisotropic dry etching of 3.0 .mu.m is performed using the resist 11 as a mask to deepen the shallow trenches located in the isolation region.

Thereafter, boron ions are implanted while leaving the resist +11 to form a p 2 stopper layer at the bottom of each deep groove (see FIG. 2(F)). Next, resist 10
, 11 are removed, resist is applied again and boron ions are implanted using photolithography to form the p-tub 12. P tub 12 is formed to surround the PIN photodiode region and the npn transistor region, respectively. Then, remove the resist,
A SiO3 film and a SiN film are formed on the inner surface of the valley groove. Then, by anisotropic etching of SiN, S
The bottom SiN film is removed while leaving the iN film (see FIG. 2(G)). Subsequently, thermal oxidation is performed in an atmosphere of 6 atm and 1050°C. As a result, the portions not covered with the SiN film are oxidized.

The thickness of the oxide film obtained by this oxidation is about 1.5 μm, and almost completely fills the shallow trench. after that,
By depositing polysilicon 13 over the entire surface, even deep trenches are filled. Then, a SiO2 film and a SiN film are formed on the surface of the polysilicon 13, and patterned by dry etching so that they remain only in the upper part of the deep groove (see FIG. 2(H)). Next, polysilicon 13 is etched. This leaves polysilicon 13 only inside the deep trench. After removing the SiN film remaining on the surface by dry etching, oxidation is performed to flatten the surface (see FIG. 2 (1)).

Next, an SiO2 film 26 and a SiN film 27 are formed on the surface. Desired regions of these films are patterned using photolithography.

By diffusing phosphorus using the remaining SiO2 film 26 and SiN film 27 as a mask, an n layer 15 that will become the collector all of the npn transistor and an n layer 16 that will serve as the electrode extraction layer of the PIN photodiode are formed (the second (See figure (J)).

Note that in FIGS. 2(J) to 2(M), the polysilicon and SiN films in the deep grooves are omitted for simplicity. Subsequently, after oxidizing the opening of the SiN film, a mask 17 is formed in the emitter region, and boron ions are implanted to form an external base 18 (see FIG. 2(K)). Further, boron ions are implanted using photolithography to form the intrinsic base 19. Thereafter, a SiO2 film 2o is deposited and stacked by chemical vapor deposition (CVD) and heated to form a profile (see FIG. 2(L)).

Next, after removing the SiO2 film 20 and SiN film on the surface by dry etching, polysilicon 21 is deposited. Then, arsenic ions are implanted (see FIG. 2CM). After sonography, a SiO2 film is deposited by CVD and heated to form an emitter 22.

Note that the n-type epitaxial layer left below the base 19 becomes the collector 23. Then, the 5iO2 film and unnecessary polysilicon are removed by dry etching, and the SiO3 film is deposited again by CVD (see Figure 2 (N)).
.

The semiconductor device shown in FIG. 1 has the necessary electrodes formed after the above steps, and a PIN photodiode 31 and an npn transistor 32 are monolithically formed on the same substrate. The PIN photodiode 31 is a substrate PI in which the high concentration p-type semiconductor substrate 1 is a P layer, the low concentration p-type epitaxial layer 2 is one layer, and the n-type buried layer 6 is an N layer.
N photodiode. A cathode electrode 33 is provided on the n-type buried layer 6 via an electrode extraction layer 16, and an anode electrode (not shown) is provided on the back surface of the substrate 1. When light is incident with a reverse bias applied between the electrodes, carriers are generated in the depletion region of the lightly doped p-type epitaxial layer 2, and these carriers move due to the electric field in the depletion region and become a photocurrent. In addition, the electrode 34 on the p-tab layer
This serves as an anode electrode of the PIN photodiode together with the electrode on the back surface. By adding this electrode 34 as an anode electrode, parasitic resistance can be reduced more than when only the back surface electrode is used as the anode electrode.

As shown in the figure, the npn transistor 32 is provided with an emitter electrode 35, a base electrode 36, and a collector electrode 37. The p-type buried layer 4 is provided to prevent punch-through with surrounding elements. Further, a stopper layer 29 is provided around the bottom of the separation groove to more effectively prevent bunch-through.

In addition, in the PIN photodiode 31, an electrode extraction layer 16 is formed using the n-type epitaxial layer 7 to have the same height as the surface of the npn transistor 32, and around the electrode extraction layer 16 is formed by oxidizing the n-type epitaxial layer 7. A silicon oxide film is formed at the same height as the electrode lead layer 16. Therefore, PIN photodiode 31 and npn
The entire surface including the transistor 32 is flat, and wiring can be easily performed.

In this embodiment, the surface of the SiO2 film is also at the same height as the electrode extraction layer 16 in the central region serving as the light receiving region of the PIN photodiode 31, that is, the thickness of the SiO2 film is about 2 μm. However, the film thickness in this region is determined by taking into account the wavelength of the light to be received. For infrared light with a wavelength of 800 to 900 nm, S
The iO2 film may be as thick as 2 μm as in this example. However, in the ultraviolet region, for example, thin S of about 0.2 μm
502 membranes are desirable.

〔Effect of the invention〕

As explained above, according to the semiconductor device of the present invention, P
Since the IN photodiode and the npn bipolar transistor are monolithically formed on the same substrate,
This has the effect of reducing parasitic capacitance based on wiring. Therefore, when used in optical communication receiving circuits, etc., it is possible to operate at higher speeds than conventional circuits. Furthermore, there is no need for an assembly process like that required for hybrid ICs. Moreover, since the surface is flat, subsequent wiring can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional perspective view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process cross-sectional view showing a manufacturing method thereof, and FIG.
The figure is a graph showing the profile of the buried layer. 1...High concentration p-type semiconductor substrate, 2...Low concentration p-type epitaxial layer, 4...p-type buried layer, 5.6...n
Type buried layer, 7... N-type epitaxial layer, 12...
p+ tab, 16... electrode extraction layer, 18... external base, 19... intrinsic base, 22... emitter, 23
...Collector, 31...PIN photodiode, 3
2...npn transistor.

Claims (1)

[Scope of Claims] A semiconductor device in which a low concentration p-type silicon epitaxial layer is formed on a high concentration p-type silicon semiconductor substrate, and an n-type silicon epitaxial layer is further formed thereon, the low concentration p By forming an n-type buried layer in the surface layer of a predetermined region of the silicon epitaxial layer, the high concentration p-type semiconductor substrate can be used as a P layer, and the low concentration silicon epitaxial layer can be used as an I layer and the n-type buried layer. A PIN photodiode is configured with an N layer, and includes an n-type collector layer, a p-type base layer, and an n-type emitter layer formed by doping impurities into the n-type silicon epitaxial layer near the predetermined region. An npn bipolar transistor is configured, a part of the n-type silicon epitaxial layer in the predetermined region is left as an electrode extraction layer, and the n-type silicon epitaxial layer is oxidized at least in the peripheral region of the electrode extraction layer. A semiconductor device characterized in that a silicon oxide film obtained by the above-mentioned method is formed to have approximately the same thickness as the electrode lead layer.