JPH03205832A - Insulated-gate semiconductor device and manufacture thereof - Google Patents
Insulated-gate semiconductor device and manufacture thereofInfo
- Publication number
- JPH03205832A JPH03205832A JP2000559A JP55990A JPH03205832A JP H03205832 A JPH03205832 A JP H03205832A JP 2000559 A JP2000559 A JP 2000559A JP 55990 A JP55990 A JP 55990A JP H03205832 A JPH03205832 A JP H03205832A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- conductivity type
- well layer
- well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 230000015556 catabolic process Effects 0.000 abstract description 27
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 230000001939 inductive effect Effects 0.000 abstract 2
- 238000000034 method Methods 0.000 description 10
- 239000012535 impurity Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁ゲート形半導体装置とその製造方法に係り
，特にスイッチング電源等のＬ負荷回路に好適な破壊耐
量を向上した縦形バソーＭＯＳＦＥＴに関丁るものであ
る。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an insulated gate type semiconductor device and its manufacturing method, and particularly relates to a vertical bassaw MOSFET with improved breakdown resistance suitable for L-load circuits such as switching power supplies. It is something to decorate.
パワーＭＯＳＦＥＴの最も通常タイプとしてシリコンゲ
ートなＶスクに二重拡散によりチャネル長を自己整合的
に形威した縦形ＭＯＳＦＥＴがある。この縦形ＭＯＳＦ
ＥＴは第９図に示すようにたとえばｎ型シリコン基板１
をドレインとし、その表面にｐ型ウェル３を形成し，ウ
ェル表面の一部にｎ＋型ンース５を形成し、基板の上に
絶縁ゲート電優６を設けてゲート電極直下のソースドレ
イン間ｐ層表面をチャネル領域４とするものである。The most common type of power MOSFET is a vertical MOSFET in which the channel length is self-aligned by double diffusion in a silicon gate V-screen. This vertical MOSF
ET is, for example, an n-type silicon substrate 1 as shown in FIG.
is used as a drain, a p-type well 3 is formed on its surface, an n+ type source 5 is formed on a part of the well surface, an insulated gate electrode 6 is provided on the substrate, and a p-type layer is formed between the source and drain directly under the gate electrode. The surface is used as a channel region 4.
このよった縦杉パワーＭＯＳＦＥＴは、負荷がコイル（
配Ｈ）であることにより、必ずＬ負荷で実装される場合
が多い。特にスイッチング電源に使用丁る場合，第１０
図に示すように誘導起電力Ｅが生じてパワーＭＯＳＦＥ
ＴＱに大きい負荷がかかり、ＭＯＳ素子が破壊される（
プレークダウン）ｊる現象がある。このブレークダウン
はベースの深さ、ウェルの深さあるいは素子の形成され
たエビタキシャル層により影響する。In this twisted Tatesugi power MOSFET, the load is the coil (
H distribution), it is often always implemented with an L load. Especially when used in a switching power supply, the 10th
As shown in the figure, an induced electromotive force E is generated and the power MOSFE
A large load is applied to the TQ and the MOS device is destroyed (
There is a phenomenon called ``preakdown''. This breakdown is affected by the depth of the base, the depth of the well, or the epitaxial layer in which the device is formed.
このような縦形バワーＭＯＳＦＥＴにおげるＬ負荷耐量
の向上を図るためには、第９図を参照し，素子の降伏す
る場所（接合部）をチャネル領域４直下のＡ，Ｂ点から
ウェルの底部に近いＣ，Ｄ点に移丁ことである。たとえ
ば特開昭５９−１３２６７１等にも記載されて（・るよ
うに、ｐウェル層（全体）の濃度を高くする方法や，ｎ
チャネルＭＯＳ素子ではｎ＋眉（ソース）の直下部分を
ウェル層（ｐウェル）に近づける方法，ある（・はチャ
ネル層の一部に高濃度ｐ＋層を設げる方法が提案されて
いる。In order to improve the L load withstand capability of such a vertical power MOSFET, referring to FIG. Transfer the pages to points C and D near the bottom. For example, as described in JP-A-59-132671, etc., there is a method of increasing the concentration of the p-well layer (overall),
In a channel MOS device, a method has been proposed in which the part immediately below the n+ eyebrow (source) is brought close to the well layer (p well), and a method in which a high concentration p+ layer is provided in a part of the channel layer.
上記した従来技術において，ｐウェル濃度を上げた場合
、隣接するセルとの接合間隔が挾くなり，オン抵抗の増
大を招くことで好ましくな（・。In the above-mentioned conventional technology, if the p-well concentration is increased, the junction distance between adjacent cells becomes narrower, leading to an increase in on-resistance, which is undesirable (.
又、サブ層（ｎ基板）をウェルｐ層に近づけるというこ
とはエビタキシャル層（ｎ一層）の厚さが少なくなるこ
とになり、ドレイン・ソース間耐圧が小となり，ある耐
圧以上への素子の適用はできｆｘ ＜ ｆｘる。Also, bringing the sub-layer (n-substrate) closer to the well p-layer means that the thickness of the epitaxial layer (n-layer) becomes smaller, which reduces the drain-source breakdown voltage, making it difficult for the device to exceed a certain breakdown voltage. It is possible to apply fx < fx.
又、ｐ＋層をソース直下に設ける方法は、チャネルｐ一
層の濃度に影響することになり、ＭＯＳ特性が変ってく
る。Furthermore, the method of providing the p+ layer directly under the source affects the concentration of the channel p layer, changing the MOS characteristics.
上記のいずれの技術についても、降伏により、寄生バイ
ボーラトランジスタを動作させることでＭＯＳ素子を破
壊させるおそれがある。In any of the above techniques, breakdown may cause the parasitic bibolar transistor to operate, thereby destroying the MOS element.
本発明は上記の点にかんがみてたされたものであり、そ
の目的は、降伏電流による素子破壊を防止し、Ｌ負荷耐
量を向上させる縦形バフ−ＭＯＳＦＥＴを提供すること
にある。The present invention has been developed in view of the above points, and its object is to provide a vertical buff MOSFET that prevents element destruction due to breakdown current and improves L load withstand capability.
上記目的を達戒するために本発明による縦形ＭＯＳＦＥ
Ｔはウェル層の底部に基板と同じ導電型でより高濃度の
量を埋設することによりゲート近くで降伏が起る以前に
ウェル層底部で降伏が起るように構成するものである。In order to achieve the above object, a vertical MOSFE according to the present invention is used.
T is of the same conductivity type as the substrate and has a higher concentration buried in the bottom of the well layer, so that breakdown occurs at the bottom of the well layer before breakdown occurs near the gate.
ウェル層底部に基板と同じ導電型の高濃度埋込層を設げ
ることにより，降伏電流はウェル層底部を起点として流
れるようになるために寄生パイボーラトランジスタが動
作することなく、破壊耐量向上が図られる。By providing a highly doped buried layer of the same conductivity type as the substrate at the bottom of the well layer, breakdown current flows starting from the bottom of the well layer, preventing the parasitic pibora transistor from operating, improving breakdown resistance. is planned.
ウェル底部の降伏は底部接合近傍の基板濃度を不純物イ
オン打込法により局所的に高めて，電界強度を高めるこ
とにより達成できる。Breakdown at the bottom of the well can be achieved by locally increasing the substrate concentration near the bottom junction using impurity ion implantation to increase the electric field strength.
以下、本発明を適用したー実施例について図面を参照し
説明する。Embodiments to which the present invention is applied will be described below with reference to the drawings.
第１図は本発明の一実施例であるｎチャネル縦形パワー
ＭＯＳＦＥＴの１セルの模型断面図である。FIG. 1 is a schematic cross-sectional view of one cell of an n-channel vertical power MOSFET, which is an embodiment of the present invention.
１はｎ一半導体基板（エビタキシャルＳｉ基板）でドレ
イン部となる。２はドレインｉｌＥｆｆｌ取出しｎ＋層
である。1 is an n-semiconductor substrate (evitaxial Si substrate) which becomes a drain portion. 2 is a drain ilEffl extraction n+ layer.
３はｐウェル層であってその周辺表面部４はチャネル領
域として使用される。3 is a p-well layer whose peripheral surface portion 4 is used as a channel region.
５はソースとなるｎ＋領域である。5 is an n+ region which becomes a source.
６は絶縁ゲート（多結晶シリコン）電砺である。6 is an insulated gate (polycrystalline silicon) conductor.
７はｎ埋込層でｐウェル層３底部とｎ一基板ｌとの間に
埋め込まれ基板１よりも高濃度に不純物がドープされて
いる。An n-buried layer 7 is buried between the bottom of the p-well layer 3 and the n-substrate 1, and is doped with impurities at a higher concentration than the substrate 1.
第２図は第１図のＡ−Ａ断面における不純物濃度プロフ
ァイルを示している。FIG. 2 shows an impurity concentration profile in the AA cross section of FIG. 1.
同図のようにｎ埋込層７の濃度をエビタキシャル層であ
るｎ一基板１のそれより高めることで電界を高め、ｐウ
ェル層とｎ一基板の他の接合部よりもプレークダウン（
降伏）が起りやすくするものである。As shown in the figure, by increasing the concentration of the n-buried layer 7 compared to that of the n-substrate 1, which is an epitaxial layer, the electric field is increased, and the breakdown (
(surrender) is more likely to occur.
第３図は太き（・負荷がかかった場合の降伏電流（太し
・矢印で示す）の流れる形態を示す。Figure 3 shows the form in which a breakdown current (indicated by a thick arrow) flows when a load is applied.
すなわち，通常は周辺表面に近（・接合部Ａ点，Ｂ点で
降伏が起るような場合、ｎ＋層５直下を降伏電流ＩＡが
流れてｎ ＋ ｐ ＋ ｎ寄生バイボーラトランジスタ
が動作して破壊してしまう。しかし、ｎ埋込層７の存在
することによってｎ埋込層７の界面のＣ点を起点とした
降伏電流ＩＢによれば素子を破壊に至らせることはない
。In other words, when breakdown occurs near the peripheral surface (junction points A and B), the breakdown current IA flows directly under the n+ layer 5, and the n+p+n parasitic bibolar transistor operates. However, due to the presence of the n-buried layer 7, the breakdown current IB starting from the point C at the interface of the n-buried layer 7 does not cause the element to be destroyed.
第４図は本発明の他の一実施例を示すものであり、ｎチ
ャネル縦形Ｍ０８ＦＥＴの１セルの縦断面図である。こ
のＭＯＳ素子はｐウェル３の周辺に接してこれにより低
濃度のｐ一層８を設げてチャネル領域としたものである
。FIG. 4 shows another embodiment of the present invention, and is a longitudinal sectional view of one cell of an n-channel vertical M08FET. In this MOS element, a low concentration p layer 8 is provided in contact with the periphery of the p well 3 to serve as a channel region.
この例において、ｐウェルの底部にｎ埋込層７を設げる
ことにより降伏電流を制御することができるとともに、
ｐウェル層３自体の濃度を比較的に高くすることができ
，ｎ一基板１の濃度が高いときに耐圧的に有利である。In this example, the breakdown current can be controlled by providing the n-buried layer 7 at the bottom of the p-well, and
The concentration of the p-well layer 3 itself can be made relatively high, which is advantageous in terms of breakdown voltage when the concentration of the n-substrate 1 is high.
第５図乃至第８図は本発明による縦形ＭＯＳＦＥＴの製
造方法の実施例を示す一部工程断面図である。5 to 8 are partial process sectional views showing an embodiment of the method for manufacturing a vertical MOSFET according to the present invention.
以下、各工程にそって説明する。Each step will be explained below.
（１） ｎ−ｎ＋基板１，２０表面にマスク材９によ
り＠（・リン等の不純物イオン打込みを行なう。この場
合，不純物濃度は基板のそれよりやや高度とし，かつ，
深い部分に埋め込まれるようにする（第５図）。(1) Impurity ions such as phosphorus are implanted into the surfaces of the n−n+ substrates 1 and 20 using the mask material 9. In this case, the impurity concentration is slightly higher than that of the substrate, and
Make sure that it is embedded deep (Figure 5).
（２）拡散により，基板１の深（・部分にｎ埋込層７を
形成する（第６図）。(2) An n-buried layer 7 is formed in the deep portion of the substrate 1 by diffusion (FIG. 6).
（３）新たに形成したマスク材１０を通してボロン不純
物のイオン打込み、拡散によりｐウェル３を形成する（
第７図）。(3) A p-well 3 is formed by ion implantation and diffusion of boron impurities through the newly formed mask material 10 (
Figure 7).
（４）基板表面上に絶縁膜（Ｓｉｎ，．膜）を介して多
結晶シリコン膜を形成し，これをパターニングして絶縁
ゲート電極６を形成する。このゲート［極をマスクに２
重拡散により、チャネル領域とｒｊるｐ一層８（第４図
を参照）及びソースｎ＋領域５を形成する。最後に表面
を絶縁膜（ ＳｉＯ＊ ） １ １で覆い，ソースｎ＋
層５とｐウェルに同時にコンタクトするスルーホールを
あげ、アルミニウムを蒸着してソース電極１２を形成す
る（第８図）。(4) A polycrystalline silicon film is formed on the surface of the substrate via an insulating film (Sin, . film), and is patterned to form an insulated gate electrode 6. This gate [2 with the pole as a mask
By heavy diffusion, a p-layer 8 (see FIG. 4) and a source n+ region 5 are formed which are connected to the channel region. Finally, the surface is covered with an insulating film (SiO*) 1 1, and the source n+
A through hole is made to simultaneously contact the layer 5 and the p-well, and aluminum is deposited to form the source electrode 12 (FIG. 8).
上記製造方法によれば、ｐウェル底部とｎ一基板との間
に降伏電流制御用のｎ埋込層を容易に形成することがで
き，それ以外に従来の二重拡散による縦形ＭＯＳＦＥＴ
プロセスそのままを利用することができる。According to the above manufacturing method, it is possible to easily form an n-buried layer for breakdown current control between the bottom of the p-well and the n-substrate, and in addition, it is possible to easily form an n-buried layer for controlling the breakdown current.
You can use the process as is.
本発明によればパワーＭＯＳＦＥＴにおいて、降伏電流
が寄生バイボーラトランジスタを動作させない経路をと
り流れることができ、破壊耐量を向上させることができ
る。すなわち、耐正の太きな低下を伴うことｆｘ ＜
Ｌ負荷耐量の向上が期待できる。According to the present invention, in a power MOSFET, a breakdown current can flow through a path that does not cause the parasitic bibolar transistor to operate, and breakdown resistance can be improved. In other words, there is a large decrease in resistance fx <
It is expected that the L load capacity will be improved.
また、破壊耐量を高める手段を素子に内在させることが
でき、外付ダイオードがなくてすみ、半導体装置の小形
化が期待できる。Furthermore, a means for increasing breakdown resistance can be built into the element, eliminating the need for an external diode, and making semiconductor devices more compact can be expected.
第１図は本発明の一実施例のパワーＭＯＳＦＥＴの縦断
面図である。
第２図は第１図のＡ−Ａ断面に対向する不純物濃度分布
図である。
第３図は第１図において降伏電流の流れる態様を示す断
面図である。
第４図は本発明の他の一実施例のパワーＭＯＳＦＥＴの
縦断面図である。
第５図乃至第８図は本発明κよるＭＯＳＦＥＴの製造方
法の一実施例を示す一部工程断面図である。
第９図は従来の縦形ＭＯＳＦＥＴの例を示す断面図であ
る。
第１０図はＭＯＳＦＥＴを用いたスイッチング回路の一
例を示す一部回路図である。
１・・・ｎ一基板（エビタキシャル・シリコン層）、３
・・・ｐウェル，５・・・ソースｎ＋領域、６・・・絶
縁ゲート，７・・・ｎ埋込層，８・・・ｐ−チャネル領
域。FIG. 1 is a longitudinal sectional view of a power MOSFET according to an embodiment of the present invention. FIG. 2 is an impurity concentration distribution diagram opposite to the AA cross section of FIG. FIG. 3 is a cross-sectional view showing how the breakdown current flows in FIG. 1. FIG. 4 is a longitudinal sectional view of a power MOSFET according to another embodiment of the present invention. 5 to 8 are partial process cross-sectional views showing an embodiment of a method for manufacturing a MOSFET according to the present invention. FIG. 9 is a sectional view showing an example of a conventional vertical MOSFET. FIG. 10 is a partial circuit diagram showing an example of a switching circuit using MOSFETs. 1...n-substrate (evitaxial silicon layer), 3
...p well, 5...source n+ region, 6...insulated gate, 7...n buried layer, 8...p- channel region.
Claims (1)
基板と逆の導電型のウェル層を形成し上記ウェル層表面
の一部に基板と同じ導電型の高濃度領域を形成してソー
スとし、基板の上に絶縁ゲート電極を設けてゲート電極
直下のソース・ドレイン間のウェル層表面をチャネル領
域とするとともに、上記ウェル層底部と基板との間に基
板と同じ導電型でより高濃度の埋込層を形成してなるこ
とを特徴とする絶縁ゲート形半導体装置。 ２、一導電型の半導体基板をドレインとし、その表面に
基板と逆の導電型のウェル層を形成し、ウェル層の周辺
に接してこれより低濃度の領域を形成し、ウェル層の表
面の一部に基板と同じ導電型の高濃度領域からなるソー
スを形成し、基板上に絶縁ゲートを設けて、ゲート電極
直下のソース・ドレイン間の上記低濃度領域表面をチャ
ネル領域とするとともに上記ウェル層の底部と基板との
間に基板と同じ導電型でより高い濃度の埋込層を形成し
たことを特徴とする絶縁ゲート形半導体装置。 ３、底面部に高濃度層を有する第１導電型低濃度半導体
基体の表面より深くより高い濃度の第１導電型ウェルを
形成し、第１導電型ウェルの一部にオーバーラップして
基体表面に第２導電型ウェルを形成し、基体上に絶縁ゲ
ートを設け、この絶縁ゲートを利用してチャネル領域の
ための低濃度第２導電型層及びソースのための高濃度第
１導電型層を形成することを特徴とする絶縁ゲート形半
導体装置の製造方法。[Claims] 1. A semiconductor substrate of one conductivity type is used as a drain, a well layer of a conductivity type opposite to that of the substrate is formed on the surface thereof, and a high concentration region of the same conductivity type as the substrate is formed on a part of the surface of the well layer. An insulated gate electrode is provided on the substrate, and the surface of the well layer between the source and drain directly under the gate electrode is used as a channel region, and the same conductivity as the substrate is formed between the bottom of the well layer and the substrate. An insulated gate type semiconductor device characterized by forming a buried layer with a higher concentration in a mold. 2. A semiconductor substrate of one conductivity type is used as a drain, a well layer of a conductivity type opposite to that of the substrate is formed on its surface, a region of lower concentration is formed in contact with the periphery of the well layer, and the surface of the well layer is A source consisting of a high concentration region of the same conductivity type as the substrate is formed in a part, an insulated gate is provided on the substrate, and the surface of the low concentration region between the source and drain directly under the gate electrode is used as a channel region, and the An insulated gate type semiconductor device characterized in that a buried layer having the same conductivity type as the substrate and having a higher concentration is formed between the bottom of the layer and the substrate. 3. A first conductivity type well with a higher concentration is formed deeper than the surface of the first conductivity type low concentration semiconductor substrate having a high concentration layer on the bottom surface, and overlaps a part of the first conductivity type well to form a layer on the substrate surface. A second conductivity type well is formed in the substrate, an insulated gate is provided on the substrate, and the insulated gate is used to form a low concentration second conductivity type layer for a channel region and a high concentration first conductivity type layer for a source. 1. A method of manufacturing an insulated gate type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000559A JPH03205832A (en) | 1990-01-08 | 1990-01-08 | Insulated-gate semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000559A JPH03205832A (en) | 1990-01-08 | 1990-01-08 | Insulated-gate semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03205832A true JPH03205832A (en) | 1991-09-09 |
Family
ID=11477082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000559A Pending JPH03205832A (en) | 1990-01-08 | 1990-01-08 | Insulated-gate semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03205832A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003101021A (en) * | 2001-09-20 | 2003-04-04 | Shindengen Electric Mfg Co Ltd | Field-effect transistor and method of manufacturing the same |
| JP2006511961A (en) * | 2002-12-20 | 2006-04-06 | クリー インコーポレイテッド | Vertical JFET Restricted Silicon Carbide Power Metal Oxide Semiconductor Field Effect Transistor and Method for Manufacturing Vertical JFET Restricted Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor |
| JP2007081436A (en) * | 1996-10-18 | 2007-03-29 | Hitachi Ltd | Semiconductor device and power converter using the same |
| EP1895595A2 (en) | 1996-10-18 | 2008-03-05 | Hitachi, Ltd. | Semiconductor device and electric power conversion apparatus therewith |
| EP2197025A1 (en) * | 2008-12-12 | 2010-06-16 | ABB Technology AG | Method for manufacturing a power semiconductor device |
| CN103839988A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Structure of EMPT-TI-IGBT device and preparation method thereof |
| CN103872115A (en) * | 2012-12-13 | 2014-06-18 | 中国科学院微电子研究所 | Reinforced micro-through IGBT |
| WO2014203317A1 (en) * | 2013-06-17 | 2014-12-24 | 株式会社日立製作所 | Semiconductor device and manufacturing method for same, as well as power conversion device |
-
1990
- 1990-01-08 JP JP2000559A patent/JPH03205832A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007081436A (en) * | 1996-10-18 | 2007-03-29 | Hitachi Ltd | Semiconductor device and power converter using the same |
| EP1895595A2 (en) | 1996-10-18 | 2008-03-05 | Hitachi, Ltd. | Semiconductor device and electric power conversion apparatus therewith |
| EP1895595A3 (en) * | 1996-10-18 | 2008-06-04 | Hitachi, Ltd. | Semiconductor device and electric power conversion apparatus therewith |
| JP2003101021A (en) * | 2001-09-20 | 2003-04-04 | Shindengen Electric Mfg Co Ltd | Field-effect transistor and method of manufacturing the same |
| JP2006511961A (en) * | 2002-12-20 | 2006-04-06 | クリー インコーポレイテッド | Vertical JFET Restricted Silicon Carbide Power Metal Oxide Semiconductor Field Effect Transistor and Method for Manufacturing Vertical JFET Restricted Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor |
| EP2197025A1 (en) * | 2008-12-12 | 2010-06-16 | ABB Technology AG | Method for manufacturing a power semiconductor device |
| JP2010141339A (en) * | 2008-12-12 | 2010-06-24 | Abb Technology Ag | Method for manufacturing semiconductor device |
| US8324062B2 (en) | 2008-12-12 | 2012-12-04 | Abb Technology Ag | Method for manufacturing a power semiconductor device |
| RU2510099C2 (en) * | 2008-12-12 | 2014-03-20 | Абб Текнолоджи Аг | Method to manufacture power semiconductor device |
| CN103839988A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Structure of EMPT-TI-IGBT device and preparation method thereof |
| CN103872115A (en) * | 2012-12-13 | 2014-06-18 | 中国科学院微电子研究所 | Reinforced micro-through IGBT |
| WO2014203317A1 (en) * | 2013-06-17 | 2014-12-24 | 株式会社日立製作所 | Semiconductor device and manufacturing method for same, as well as power conversion device |
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