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JPH0282125U - - Google Patents

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Publication number
JPH0282125U
JPH0282125U JP16142688U JP16142688U JPH0282125U JP H0282125 U JPH0282125 U JP H0282125U JP 16142688 U JP16142688 U JP 16142688U JP 16142688 U JP16142688 U JP 16142688U JP H0282125 U JPH0282125 U JP H0282125U
Authority
JP
Japan
Prior art keywords
level
output signal
input signal
control section
automatic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16142688U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16142688U priority Critical patent/JPH0282125U/ja
Publication of JPH0282125U publication Critical patent/JPH0282125U/ja
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の回路図、第2図は
第1図の回路における信号波形を示すタイムチヤ
ートであり、a,b,cは本考案にかかる入力、
利得、出力の各信号図、d及びeは従来における
利得、出力の各信号を示している。 1……入力端子、2……可変減衰器、3……増
幅器、4……出力端子、5……出力信号レベル検
出器、6……ALC制御部、7……入力信号検出
器、8……比較制御部。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a time chart showing signal waveforms in the circuit of FIG. 1, where a, b, and c are inputs according to the present invention;
In the gain and output signal diagrams, d and e indicate the conventional gain and output signals. DESCRIPTION OF SYMBOLS 1...Input terminal, 2...Variable attenuator, 3...Amplifier, 4...Output terminal, 5...Output signal level detector, 6...ALC control section, 7...Input signal detector, 8... ...Comparison control section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 出力信号のレベルを検出する出力信号レベル検
出器と、この出力信号レベル検出器の検出レベル
に基づいて利得を制御する自動レベル制御部とを
備える無線送信機において、前記入力信号のレベ
ルを検出する入力信号検出部と、この検出された
入力信号レベルを設定値と比較し、該検出レベル
が設定値以下のときに前記自動レベル制御部によ
る利得制御を抑制する比較制御部とを備えること
を特徴とする送信機の自動レベル制御回路。
Detecting the level of the input signal in a wireless transmitter comprising an output signal level detector that detects the level of the output signal, and an automatic level control section that controls the gain based on the detection level of the output signal level detector. It is characterized by comprising an input signal detection section and a comparison control section that compares the detected input signal level with a set value and suppresses gain control by the automatic level control section when the detected level is less than the set value. automatic level control circuit for the transmitter.
JP16142688U 1988-12-13 1988-12-13 Pending JPH0282125U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16142688U JPH0282125U (en) 1988-12-13 1988-12-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16142688U JPH0282125U (en) 1988-12-13 1988-12-13

Publications (1)

Publication Number Publication Date
JPH0282125U true JPH0282125U (en) 1990-06-25

Family

ID=31444351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16142688U Pending JPH0282125U (en) 1988-12-13 1988-12-13

Country Status (1)

Country Link
JP (1) JPH0282125U (en)

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