JPH02252294A - Manufacture of multilayer board - Google Patents
Manufacture of multilayer boardInfo
- Publication number
- JPH02252294A JPH02252294A JP7320789A JP7320789A JPH02252294A JP H02252294 A JPH02252294 A JP H02252294A JP 7320789 A JP7320789 A JP 7320789A JP 7320789 A JP7320789 A JP 7320789A JP H02252294 A JPH02252294 A JP H02252294A
- Authority
- JP
- Japan
- Prior art keywords
- electric circuit
- layer material
- prepreg
- bonding agent
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000463 material Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000853 adhesive Substances 0.000 claims description 12
- 230000001070 adhesive effect Effects 0.000 claims description 12
- 239000003795 chemical substances by application Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 abstract description 12
- 239000011347 resin Substances 0.000 abstract description 12
- 239000003822 epoxy resin Substances 0.000 abstract description 11
- 229920000647 polyepoxide Polymers 0.000 abstract description 11
- 125000001475 halogen functional group Chemical group 0.000 abstract description 7
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 abstract description 7
- 239000005011 phenolic resin Substances 0.000 abstract description 6
- 239000002904 solvent Substances 0.000 abstract description 6
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 abstract description 4
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 abstract description 2
- QTWJRLJHJPIABL-UHFFFAOYSA-N 2-methylphenol;3-methylphenol;4-methylphenol Chemical compound CC1=CC=C(O)C=C1.CC1=CC=CC(O)=C1.CC1=CC=CC=C1O QTWJRLJHJPIABL-UHFFFAOYSA-N 0.000 abstract description 2
- 229930003836 cresol Natural products 0.000 abstract description 2
- 229920003986 novolac Polymers 0.000 abstract description 2
- 229920001568 phenolic resin Polymers 0.000 abstract description 2
- 238000005498 polishing Methods 0.000 abstract description 2
- 229920003987 resole Polymers 0.000 abstract description 2
- 239000007767 bonding agent Substances 0.000 abstract 5
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 42
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 239000012790 adhesive layer Substances 0.000 description 8
- 239000011889 copper foil Substances 0.000 description 8
- 238000007788 roughening Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000009477 glass transition Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- UKLNMMHNWFDKNT-UHFFFAOYSA-M sodium chlorite Chemical compound [Na+].[O-]Cl=O UKLNMMHNWFDKNT-UHFFFAOYSA-M 0.000 description 2
- 229960002218 sodium chlorite Drugs 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000002966 varnish Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000010081 sangu Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、電子機器、電気機器、コンピューター、通
信機器などに用いられる多層板を製造する方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a multilayer board used in electronic equipment, electrical equipment, computers, communication equipment, etc.
従来の多層板は、たとえば、つぎのようにして製造され
ている。片面または両面銅張積ｒｒ／Ｉ坂の銅箔を所望
のパターンでエツチングして電路（回路）を形成したも
のを内層材とし、この内層材表面を粗化してから、また
は、粗化してさらに黒化処理してから、プリプレグを介
し、最外層に片面銅張積層板や銅箔を外層材として配設
し、一体化して多層板が得られる。前記粗化処理は、熟
練工の人がベルトサングーなどの機械的粗化処理装置を
用いて行っている。この粗化処理により、電路部分とプ
リプレグとの間にアンカー効果が得られ、接着性の向上
が図られる。前記黒化処理は、アルカリ性亜塩素酸ナト
リウム水溶液などで処理し、銅箔表面に黒色酸化銅被膜
を形成するものである、この黒色酸化銅被膜の働きで、
内層材とプリプレグとの接着性を高めている。Conventional multilayer boards are manufactured, for example, in the following manner. One-sided or double-sided copper clad RR/I slope copper foil is etched in a desired pattern to form an electric path (circuit), and the inner layer material is roughened or further roughened. After the blackening treatment, a single-sided copper-clad laminate or copper foil is provided as an outer layer material on the outermost layer via a prepreg, and is integrated to obtain a multilayer board. The roughening treatment is performed by a skilled worker using a mechanical roughening treatment device such as a belt sangu. This roughening treatment provides an anchor effect between the electric circuit portion and the prepreg, and improves adhesiveness. The blackening treatment is performed by treating with an alkaline sodium chlorite aqueous solution or the like to form a black copper oxide film on the surface of the copper foil.
Improves adhesion between inner layer material and prepreg.
前記粗化処理は、熟練工の存在が不可欠であるという問
題があり、しかも、電路を傷付ける危険が非常に大きい
という問題がある。The roughening treatment has the problem that the presence of a skilled worker is indispensable, and there is also a problem that there is a very large risk of damaging the electric circuit.
前記黒色酸化銅被膜は、いままでのパターン回路幅（た
とえば、電路間隔２．５鶴、電路面積的１２％）では接
着性が良いが、ファインパターン回路幅〔たとえば、電
路間隔２．５鶴が標準のところに、さらに、幅０．５鶴
の電路を１本または２本設けたりすると、電路間隔１ｆ
ｌ（電路面積約２７％）または０．５ｇｍ（電路面積約
４４％）になる〕では接着性が低下するという問題があ
る。この接着性の低下により、多層板にハローが発生し
、配線板としての信頼性を低下させる。The black copper oxide film has good adhesion with conventional pattern circuit widths (e.g., 2.5-wire spacing, 12% of the circuit area); If one or two electrical circuits with a width of 0.5 mm are added to the standard location, the electrical circuit spacing will be 1 f.
1 (approximately 27% of the circuit area) or 0.5 gm (approximately 44% of the circuit area)], there is a problem that the adhesiveness decreases. This decrease in adhesiveness causes a halo to occur in the multilayer board, reducing its reliability as a wiring board.
そこで、この発明は、ファインパターン回路幅であって
も、すなわち、電路面積が多くなっても層間接着性が良
く、したがって、耐ハロー性に優れた多層板を容易に製
造できる方法を提供することを課題とする。SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method for easily manufacturing a multilayer board that has good interlayer adhesion even when the circuit width is fine, that is, the area of the circuit increases, and therefore has excellent halo resistance. The task is to
上記課題を解決するために、この発明にかかる多層板の
製造法は、内層材と外層材とを、プリプレグを介して積
層一体化するにあたり、前記内層材および／または外層
材の電路形成面のうちの少なくとも電路部分と前記プリ
プレグとの間に接着剤層を介在させるようにすることを
特徴とする。In order to solve the above problems, the method for manufacturing a multilayer board according to the present invention is such that when an inner layer material and an outer layer material are laminated and integrated via a prepreg, the electric circuit forming surface of the inner layer material and/or the outer layer material is It is characterized in that an adhesive layer is interposed between at least the electric circuit portion and the prepreg.
前記内層材は、その片面または両面に電路が形成されて
おり同電路が絶縁層の上に形成されたもの、および／ま
たは、内部に１層以上の電路が形成されたものなどであ
り、特に限定はない。The inner layer material is one in which an electric path is formed on one or both sides and the electric path is formed on an insulating layer, and/or one in which one or more layers of electric path are formed inside. There are no limitations.
前記外層材は、片面に電路が形成された配線板、片面金
属箔張板、銅箔などの金属箔などが挙げられるが、これ
らに限定されない。前記片面に電路が形成された配線板
は、もう片面に銅箔などの金属箔が設けられていてもよ
い。Examples of the outer layer material include, but are not limited to, a wiring board with an electric path formed on one side, a metal foil-clad plate on one side, and a metal foil such as copper foil. The wiring board with the electric circuit formed on one side may have a metal foil such as copper foil on the other side.
前記電路は、銅箔など金属の薄層から形成されている必
要はなく、導電性を有する材料から形成されていれば特
に材料に限定はない。The electric path does not need to be formed from a thin layer of metal such as copper foil, and there is no particular limitation on the material as long as it is formed from a conductive material.
前記プリプレグは、繊維質基材に樹脂を含浸させてなる
ものである。前記繊維質基材としては、特に限定はない
が、たとえば、ガラス布が使用される。また、繊維質基
材に含浸される樹脂としては、たとえば、エポキシ樹脂
が使用される。同エポキシ樹脂には、積層板の分野など
で用いられている硬化剤およびその他の配合物が、必要
に応じて適宜配合されていてもよい。The prepreg is made by impregnating a fibrous base material with a resin. The fibrous base material is not particularly limited, but for example, glass cloth is used. Furthermore, as the resin impregnated into the fibrous base material, for example, epoxy resin is used. The epoxy resin may contain a curing agent and other compounds used in the field of laminates, etc., as appropriate.
前記内層材と外層材とを、プリプレグを介して積層一体
化するのであるが、この発明では、内層材および／また
は外層材の電路形成面のうちの少なくとも電路部分の上
に、および／または、プリプレグの少なくとも前記電路
部分に対面する部分の上に接着剤層を設けておくのであ
る。The inner layer material and the outer layer material are laminated and integrated via a prepreg, and in this invention, on at least the electric circuit portion of the electric circuit forming surface of the inner layer material and/or the outer layer material, and/or, An adhesive layer is provided on at least the portion of the prepreg facing the electric circuit portion.
前記接着剤としては、特に限定はないが、濡れの良い液
状の樹脂または樹脂ワニスが挙げられる。前記樹脂とし
ては、特に限定はないが、エポキシ樹脂、フェノール樹
脂、ブチラール樹脂、ポリイミドなどを含むものが好ま
しい。さらに好ましくは、エポキシ樹脂、フェノール樹
脂およびブチラール樹脂の３者をともに含む接着剤であ
る。エポキシ樹脂は耐熱性が高いがガラス転移温度がや
や低く、剥離状態が瞬間的であり、フェノール樹脂は、
耐熱性およびガラス転移温度がエポキシ樹脂とブチラー
ル樹脂との間であり、剥離状態が瞬間的であり、ブチラ
ール樹脂は、耐熱性およびガラス転移温度が低いが、剥
離状態が瞬間的ではない。このため、エポキシ樹脂、フ
ェノール樹脂およびブチラール樹脂の３者を必須成分と
する接着剤を用いると、電路とプリプレグとの間の接着
性改善により効果が高くなる。前記３者を必須成分とす
る接着剤は、配合割合に特に限定はないが、たとえば、
エポキシ樹脂（クレゾールノボラック型および／または
ビスフェノールＡ型が好ましい）、フェノール樹脂（レ
ゾール型が好ましい）およびブチラール樹脂を各々１／
３ずつの割合で添加し、溶剤で樹脂量を１５〜２５ｆｆ
ｉ量％に溶解させてなる接着剤が挙げられる。前記樹脂
ワニスとしては、たとえば、溶剤で樹脂量１５〜２５重
量％に溶解させたものが挙げられる。前記溶剤としては
、上記の樹脂に用いられうるちのであれば特に制限はな
い。接着剤の塗布量は、１００〜３００ｇ／ｒｒｒが好
ましい。また、接着剤層の厚みは、特に限定されない。The adhesive is not particularly limited, but includes liquid resins or resin varnishes with good wettability. The resin is not particularly limited, but preferably includes epoxy resin, phenol resin, butyral resin, polyimide, and the like. More preferred is an adhesive containing all three of epoxy resin, phenol resin, and butyral resin. Epoxy resin has high heat resistance, but its glass transition temperature is somewhat low and peeling is instantaneous, while phenolic resin has
The heat resistance and glass transition temperature are between those of epoxy resins and butyral resins, and the peeling state is instantaneous; butyral resin has low heat resistance and glass transition temperature, but the peeling state is not instantaneous. For this reason, when an adhesive containing the three essential components of epoxy resin, phenol resin, and butyral resin is used, the adhesiveness between the electric circuit and the prepreg is improved and the effect becomes higher. There are no particular limitations on the blending ratio of adhesives containing the above three as essential components, but for example,
Epoxy resin (preferably cresol novolac type and/or bisphenol A type), phenol resin (preferably resol type) and butyral resin are each
Add at a ratio of 3 to 3, and adjust the resin amount to 15 to 25ff with a solvent.
Examples include adhesives that are dissolved in i amount%. Examples of the resin varnish include those in which the resin amount is 15 to 25% by weight dissolved in a solvent. The solvent is not particularly limited as long as it can be used for the above resin. The amount of adhesive applied is preferably 100 to 300 g/rrr. Further, the thickness of the adhesive layer is not particularly limited.
内層材および／または外層材の電路形成面の電路部分な
いしは全体の上に、および／または、プリプレグの面の
少なくとも前記電路部分に向かい会う部分の上に接着剤
層を設け、内層材の片面または両面に１枚以上（好まし
くは１〜３枚）のプリプレグを重ね合わせ、さらに、外
層材を重ね合わせて、無圧下でまたは適宜の加圧下で、
適宜の温度で、適宜の時間積層一体化する。このときの
温度は、たとえば、プリプレグおよび接着剤の樹脂の硬
化する温度が選択される。An adhesive layer is provided on the electric circuit portion or the entire electric circuit forming surface of the inner layer material and/or the outer layer material, and/or on at least the portion of the prepreg surface facing the electric circuit portion, and an adhesive layer is provided on one side of the inner layer material or Layer one or more prepregs (preferably 1 to 3 sheets) on both sides, and then layer the outer layer material, under no pressure or under appropriate pressure,
The layers are laminated and integrated at an appropriate temperature and for an appropriate time. The temperature at this time is selected, for example, at a temperature at which the prepreg and adhesive resin are cured.
プリプレグの溶融樹脂が電路表面に流出して電路表面に
接着するよりも、前記液状の接着剤を電路上に塗布した
りしたものの方が接着性が大きい。これは、液状の接着
剤の濡れが良いためであると考えられる。The adhesion is greater when the liquid adhesive is applied onto the circuit surface, rather than when the molten resin of the prepreg flows onto the surface of the circuit and adheres to the surface of the circuit. This is thought to be due to the good wettability of the liquid adhesive.
内層材および／または外層材に形成された電路と、プリ
プレグとの間に接着剤層を介在させることにより、前記
電路が上記のようなファインパターン回路幅であっても
接着性の低下が防がれる。By interposing an adhesive layer between the electric circuit formed in the inner layer material and/or the outer layer material and the prepreg, a decrease in adhesiveness can be prevented even if the electric circuit has a fine pattern circuit width as described above. It will be done.
これにより、ハローが起こりにくくなり、多層板の信頼
性の低下を防ぐことができる。また、粗化のための研磨
を行わないので、電路の破損が起こりに（い。Thereby, halo is less likely to occur, and a decrease in reliability of the multilayer board can be prevented. Also, since no polishing is performed for roughening, damage to the electrical circuits is less likely to occur.
以下に、この発明の具体的な実施例および比較例を示す
が、この発明は下記実施例に限定されない。Specific examples and comparative examples of the present invention are shown below, but the present invention is not limited to the following examples.
一実施例−
厚み１龍の両面銅張ガラス布エポキシ樹脂積層板の両面
の銅箔（厚み３５μ）が所望のパターン（ただし、ファ
インパターン電路幅０．５ ｍ、電路間１龍間隔とした
）で残るようにしてエツチングし、電路を形成した。こ
の電路形成板を内層材として用いた。この内層材の電路
形成面全体に対する電路面積は、２７％であった。One Example - Copper foil (thickness: 35 μm) on both sides of a double-sided copper-clad glass cloth epoxy resin laminate with a thickness of 1 layer was formed into a desired pattern (however, the fine pattern circuit width was 0.5 m, and the distance between the circuits was 1 layer). I etched it so that it remained, and formed an electric path. This circuit forming board was used as an inner layer material. The area of the electric circuit with respect to the entire electric circuit forming surface of this inner layer material was 27%.
内層材の電路面（粗化処理せず）のみに下記配合の接着
剤をスクリーン印刷法により２００ ｇ／ｄで塗布して
乾燥させ、接着剤層（厚み２０ｐ■）を形成した。内層
材の表裏に厚み０．１ ｗのガラス布エポキシ樹脂プリ
プレグをそれぞれ２枚ずつ重ね合わせ、さらに両外側か
ら厚み０．０３５ｍの銅箔を重ね合わせた。この積層体
を４０ ｋｇ／ｃｆｆｌ、 １６５℃で６０分間積層成
形して４層回路プリント配線板（多層板）を得た。An adhesive having the following composition was applied by screen printing at a rate of 200 g/d only to the circuit surface of the inner layer material (without roughening treatment) and dried to form an adhesive layer (thickness: 20p). Two sheets of glass cloth epoxy resin prepreg with a thickness of 0.1 w were stacked on each of the front and back sides of the inner layer material, and copper foils with a thickness of 0.035 m were stacked on both outsides. This laminate was laminated and molded at 40 kg/cffl at 165° C. for 60 minutes to obtain a four-layer circuit printed wiring board (multilayer board).
の Ａ （会）
一比較例１−
前記実施例において、内層材をアルカリ性亜塩素酸ナト
リウム水溶液に３分間浸漬し、同内層材表面を黒化処理
し、接着剤を用いずに、ただちに、実施例と同じプリプ
レグを表裏にそれぞれ２枚ずつ重ね合わせたこと以外は
、実施例と同様にして４層回路プリント配線板（多層板
）を得た。Comparative Example 1 - In the above example, the inner layer material was immersed in an alkaline sodium chlorite aqueous solution for 3 minutes to blacken the surface of the inner layer material, and immediately carried out without using an adhesive. A four-layer circuit printed wiring board (multilayer board) was obtained in the same manner as in the example except that two sheets of the same prepreg as in the example were stacked on each side.
−比較例２−
前記実施例において、熟練工の人により内層材をベルト
サングーに内層材の電路形成面を軽く接触させることに
より粗化処理し、接着剤を用いずに、ただちに、実施例
と同じプリプレグを表裏にそれぞれ２枚ずつ重ね合わせ
たこと以外は、実施例と同様にして４層回路プリント配
線板（多層板）を得た。- Comparative Example 2 - In the above example, the inner layer material was roughened by a skilled worker by lightly contacting the electric circuit forming surface of the inner layer material with a belt sanguo, and immediately without using an adhesive, the inner layer material was roughened as in the example example. A four-layer circuit printed wiring board (multilayer board) was obtained in the same manner as in the example except that two sheets of the same prepreg were stacked on each side.
実施例および比較例でそれぞれ得られた多層板の性能を
第１表に示した。ハロー性は、多層板をドリル加工（６
００００ｒｐｎ＋、送り速度５０μ／ｒｅｖ、）で穴あ
けを行い、通常の化学銅めっき液を用いためっき液処理
後の水溶液のしみ込み性をみた。Table 1 shows the performance of the multilayer plates obtained in Examples and Comparative Examples. Halo properties are obtained by drilling a multilayer board (6
Holes were drilled at a feed rate of 0000 rpm+ and a feed rate of 50 μ/rev, and the permeability of the aqueous solution after treatment with a plating solution using an ordinary chemical copper plating solution was examined.
第 １ 表
第１表かられかるように、実施例で得られた多層板は、
比較例で得られたものに比べて、層間接着性が強く、ハ
ロー性が良好である。Table 1 As can be seen from Table 1, the multilayer board obtained in the example was:
The interlayer adhesion is stronger and the halo property is better than that obtained in the comparative example.
この発明にかかる多層板の製造法は、以上に述べたよう
に、内層材および／または外層材の電路形成面のうちの
少なくとも電路部分と前記プリプレグとの間に接着剤層
を介在させるようにすることを特徴とする。したがって
、この製造法によれば、ファインパターン回路幅であっ
ても層間接着性が良く、したがって、耐ハロー性に優れ
た多層板が得られる。As described above, the method for manufacturing a multilayer board according to the present invention includes interposing an adhesive layer between at least the electric circuit portion of the electric circuit forming surface of the inner layer material and/or the outer layer material and the prepreg. It is characterized by Therefore, according to this manufacturing method, a multilayer board with good interlayer adhesion and excellent halo resistance even with a fine pattern circuit width can be obtained.
代□理人 弁理士 松 本 武 彦Representative Patent Attorney Takehiko Matsumoto
Claims (1)
化する多層板の製造法において、前記内層材および／ま
たは外層材の電路形成面のうちの少なくとも電路部分と
前記プリプレグとの間に接着剤層を介在させるようにす
ることを特徴とする多層板の製造法。1. In a method for manufacturing a multilayer board in which an inner layer material and an outer layer material are laminated and integrated via a prepreg, adhesive is formed between at least the electric circuit portion of the electric circuit forming surface of the inner layer material and/or the outer layer material and the prepreg. A method for manufacturing a multilayer board, characterized by interposing a layer of agent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7320789A JPH02252294A (en) | 1989-03-25 | 1989-03-25 | Manufacture of multilayer board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7320789A JPH02252294A (en) | 1989-03-25 | 1989-03-25 | Manufacture of multilayer board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02252294A true JPH02252294A (en) | 1990-10-11 |
Family
ID=13511474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7320789A Pending JPH02252294A (en) | 1989-03-25 | 1989-03-25 | Manufacture of multilayer board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02252294A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04234782A (en) * | 1991-01-01 | 1992-08-24 | Ricos:Kk | Song text synchronous display device |
| JP2008306201A (en) * | 2008-07-22 | 2008-12-18 | Ibiden Co Ltd | Multilayer printed wiring board and manufacturing method therefor |
| US7504719B2 (en) * | 1998-09-28 | 2009-03-17 | Ibiden Co., Ltd. | Printed wiring board having a roughened surface formed on a metal layer, and method for producing the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54162166A (en) * | 1978-06-13 | 1979-12-22 | Fujitsu Ltd | Method of producing multiilayer printed circuit board |
| JPS6062193A (en) * | 1983-09-14 | 1985-04-10 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
| JPS6062194A (en) * | 1983-09-14 | 1985-04-10 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
| JPS61135738A (en) * | 1984-12-07 | 1986-06-23 | 東芝ケミカル株式会社 | Multilayer board |
| JPS6377737A (en) * | 1986-09-19 | 1988-04-07 | 松下電工株式会社 | Composite metallic-foil lined laminated board |
-
1989
- 1989-03-25 JP JP7320789A patent/JPH02252294A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54162166A (en) * | 1978-06-13 | 1979-12-22 | Fujitsu Ltd | Method of producing multiilayer printed circuit board |
| JPS6062193A (en) * | 1983-09-14 | 1985-04-10 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
| JPS6062194A (en) * | 1983-09-14 | 1985-04-10 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
| JPS61135738A (en) * | 1984-12-07 | 1986-06-23 | 東芝ケミカル株式会社 | Multilayer board |
| JPS6377737A (en) * | 1986-09-19 | 1988-04-07 | 松下電工株式会社 | Composite metallic-foil lined laminated board |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04234782A (en) * | 1991-01-01 | 1992-08-24 | Ricos:Kk | Song text synchronous display device |
| US7504719B2 (en) * | 1998-09-28 | 2009-03-17 | Ibiden Co., Ltd. | Printed wiring board having a roughened surface formed on a metal layer, and method for producing the same |
| US7535095B1 (en) | 1998-09-28 | 2009-05-19 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
| US7994433B2 (en) | 1998-09-28 | 2011-08-09 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
| US8006377B2 (en) | 1998-09-28 | 2011-08-30 | Ibiden Co., Ltd. | Method for producing a printed wiring board |
| US8018045B2 (en) | 1998-09-28 | 2011-09-13 | Ibiden Co., Ltd. | Printed circuit board |
| US8020291B2 (en) | 1998-09-28 | 2011-09-20 | Ibiden Co., Ltd. | Method of manufacturing a printed wiring board |
| US8030577B2 (en) | 1998-09-28 | 2011-10-04 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
| US8093507B2 (en) | 1998-09-28 | 2012-01-10 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
| US8533943B2 (en) | 1998-09-28 | 2013-09-17 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
| JP2008306201A (en) * | 2008-07-22 | 2008-12-18 | Ibiden Co Ltd | Multilayer printed wiring board and manufacturing method therefor |
| JP4553402B2 (en) * | 2008-07-22 | 2010-09-29 | イビデン株式会社 | Manufacturing method of multilayer printed wiring board |
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