JPH0224395B2 - - Google Patents
Info
- Publication number
- JPH0224395B2 JPH0224395B2 JP59148270A JP14827084A JPH0224395B2 JP H0224395 B2 JPH0224395 B2 JP H0224395B2 JP 59148270 A JP59148270 A JP 59148270A JP 14827084 A JP14827084 A JP 14827084A JP H0224395 B2 JPH0224395 B2 JP H0224395B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- core wiring
- wiring board
- metal core
- lead terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000011810 insulating material Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 2
- 238000004080 punching Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 abstract description 4
- 239000004033 plastic Substances 0.000 abstract description 4
- 229920003023 plastic Polymers 0.000 abstract description 4
- 229910000906 Bronze Inorganic materials 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010974 bronze Substances 0.000 abstract description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052742 iron Inorganic materials 0.000 abstract description 2
- 239000012778 molding material Substances 0.000 abstract description 2
- 238000007639 printing Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 229920000642 polymer Polymers 0.000 abstract 1
- 238000007650 screen-printing Methods 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002650 laminated plastic Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はハイブリツドIC等の製造に利用する
メタルコア配線基板、殊に多数のリードを有する
所謂DIP域はSIP型ICを製造するに適した配線基
板に関する。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a metal core wiring board used for manufacturing hybrid ICs, etc., and in particular, a so-called DIP area having a large number of leads is suitable for manufacturing SIP type ICs. Regarding the board.
（従来技術）
従来ハイブリツドIC等の基板としてはセラミ
クス板域はプラスチツクスの積層板を使用するの
が一般的であつたが前者は基板自体も高価である
上又該基板上に形成する導体パターンも銀−パウ
ジウム・ペーストを必要とする等高価なものであ
つた。又配線密度向上の為基板両面を使用する場
合にはスルーホールを必要とするがこの加工はか
なりめんどうなものであつた。(Prior art) Conventionally, as a substrate for hybrid ICs, it has been common to use a plastic laminate in the ceramic plate area, but in the former case, not only is the substrate itself expensive, but also the conductor pattern formed on the substrate is expensive. However, they were also expensive, requiring silver-pasdium paste. Furthermore, when using both sides of the board to increase wiring density, through holes are required, but this process is quite troublesome.
一方、後者即ちプラスチツクス積層基板には上
述の如き問題はないがいずれもリード端子を接続
固定する工程が必要であり相当の工数を要するも
のであつた。 On the other hand, although the latter, that is, a plastic laminated board, does not have the above-mentioned problems, both require a process of connecting and fixing lead terminals, which requires a considerable number of man-hours.
（発明の目的）
本発明は上述した如き従来のハイブリツドIC
等に用いる基板の加工々程及びコスト上の欠陥を
除去することを目的とする。(Object of the Invention) The present invention is directed to the conventional hybrid IC as described above.
The purpose is to eliminate defects in processing and cost of substrates used for such applications.
（発明の概要）
上述の目的を達成する為本発明に係るメタルコ
ア配線基板は以下の如き構成をとる。即ち、エツ
チング等の手法によつて導体薄板をリード端子を
含む所要の形状に成形し該導体基板表面を絶縁物
質で被覆した後該被覆上に導体パターンを形成し
たものである。(Summary of the Invention) In order to achieve the above-mentioned object, a metal core wiring board according to the present invention has the following configuration. That is, a conductor thin plate is formed into a desired shape including lead terminals by a method such as etching, the surface of the conductor substrate is coated with an insulating material, and a conductor pattern is formed on the coating.
（発明の実施例）
以下本発明を図面に示す実施例に基づいて詳細
に説明する。(Embodiments of the Invention) The present invention will be described in detail below based on embodiments shown in the drawings.
第１図及び第２図は夫々本発明に係るメタルコ
ア配線基板の斜視図及び断面図である。 1 and 2 are a perspective view and a sectional view, respectively, of a metal core wiring board according to the present invention.
本図に於いて１は基板のコアとなる導体薄板で
あつて該薄板１の側縁にリード端子となる突条
２，２，…及び３，３，…を後述する手法によつ
て前記薄板１と電気的に絶縁した状態にて形成し
これらを一体的に絶縁被覆４にて固定する。然る
後に前記被覆４表面に導体パターン５，５，…を
印刷等の手法で形成し更に該パターン５，５，…
の所要の位置に電子部品を接続する為のハンダ・
ペースト６，６，…を付着せしめ最后にこれを所
要の形状、例えば前記リード端子２，２，…及び
３，３，…が並例する所謂DIP型となるようコの
字形に加工したものである。 In this figure, reference numeral 1 denotes a thin conductive plate that becomes the core of the board, and protrusions 2, 2, . . . and 3, 3, . 1 and are formed in a state of being electrically insulated from each other, and these are integrally fixed with an insulating coating 4. Thereafter, conductor patterns 5, 5, ... are formed on the surface of the coating 4 by printing or the like, and the patterns 5, 5, ...
solder to connect electronic components to the required positions of
The pastes 6, 6, . . . are adhered and finally processed into a desired shape, for example, into a U-shape so that the lead terminals 2, 2, . . . and 3, 3, . be.
上述の如きメタルコア配線基板は例えば第３図
に示す工程を採用することによつて容易に製造可
能である。即ち、第３図ａに示す如く所要の厚さ
の鉄、銅域はリン青銅板等の導体薄板１を用意し
その表面にフオトレジスト７を塗布するかドライ
フイルムを貼着し（同図ｂ）、これを所要のマス
クを用いて露光した後感光部を除去し（同図ｃ）
然る後にエツチングを行う（同図ｄ）。この際前
記リード端子２，２，…が基板１と分離しないよ
う適当なリードフレーム８にて接続しておき（同
図d′）次の絶縁物質４被覆工程（同図ｅ）終了後
前記図d′の一点鎖線部Ｂ及びＣで前記リードフレ
ーム８を切り離せばよい。 The metal core wiring board as described above can be easily manufactured by employing the process shown in FIG. 3, for example. That is, as shown in Fig. 3a, a conductor thin plate 1 such as a phosphor bronze plate is prepared for the iron and copper area of the required thickness, and a photoresist 7 is applied to the surface of the conductor plate 1, or a dry film is attached (Fig. 3b). ), and after exposing it to light using the required mask, the exposed area was removed (see figure c).
After that, etching is performed (d in the same figure). At this time, the lead terminals 2, 2, ... are connected with a suitable lead frame 8 so as not to be separated from the substrate 1 (d' in the figure). The lead frame 8 may be separated at the dashed-dotted line portions B and C of d'.
前記絶縁物質４としては接着性のある高分子誘
電体物質を適宜選択しこれを塗布するかスクリー
ン印刷すればよいであろう。 As the insulating material 4, an adhesive polymeric dielectric material may be appropriately selected and coated or screen printed.
次いで前記絶縁被覆４表面に導体インクを用い
て所望のパターン５を印刷すると共に前記パター
ン５上所要の位置にハンダペースト６を印刷し
（同図ｆ）、前記基板１両側縁を屈曲してDIP状と
なし（同図ｇ）メタルコア配線基板を完成する。
このようにして製造した配線基板上に所要の電子
部品９を接続し（同図ｈ）、これを一体的にプラ
スチツクス等のモールド材１０でモールドすれば
DIP型ハイブリツドICが完成する（同図ｉ）。尚、
前記ｇに示した屈曲工程とｈに示した電子部品９
の装着工程とは逆にしてもよいことは自明であり
設計に応じて適宜工程を交換することができる。 Next, a desired pattern 5 is printed on the surface of the insulating coating 4 using conductive ink, and a solder paste 6 is printed at a required position on the pattern 5 (see f in the same figure), and both sides of the substrate 1 are bent and DIP Complete the metal core wiring board (g).
The required electronic components 9 are connected to the wiring board manufactured in this way (h in the same figure), and this is integrally molded with a molding material 10 such as plastic.
The DIP type hybrid IC is completed (Figure i). still,
The bending process shown in g and the electronic component 9 shown in h
It is obvious that the mounting process may be reversed, and the process can be changed as appropriate depending on the design.
以上、本発明の基本的な構成について説明した
が本発明に係るメタルコア配線基板は電子部品の
実装面積を増大する為以下の如くして両面実装を
可能ならしめることもできる。 The basic configuration of the present invention has been described above, but the metal core wiring board according to the present invention can also be made double-sided mounting possible in the following manner in order to increase the mounting area of electronic components.
第４図はその一実施例を示す基板製造工程図で
あるが、両面実装を行う場合には一般にスルーホ
ールを必要とするので導体コア１の両面にフオト
レジスト７を付着せしめ（同図ａ，ｂ）所要パタ
ーンのマスクを介しての感光工程（同図ｃ）の後
エツチングによつてスルーホール１１，１１，…
を設け（同図ｄ）、前記基板１両面を絶縁物質４
で被覆した後（同図ｅ）、前記絶縁被覆４上に導
電ペースト５を印刷して所要の導電パターンを形
成すると同時に前記スルーホール１１，１１，…
をも導電ペーストで埋め基板両面の導通を確保す
る（同図ｆ）よう構成すればよい。 FIG. 4 is a board manufacturing process diagram showing an example of this. When performing double-sided mounting, through holes are generally required, so photoresist 7 is attached to both sides of the conductor core 1 (a, b) Through-holes 11, 11, . . . are formed by etching after the exposure step (c in the same figure) through a mask with a desired pattern.
(d in the same figure), and an insulating material 4 is provided on both sides of the substrate 1.
(FIG. 6(e)), conductive paste 5 is printed on the insulating coating 4 to form a required conductive pattern, and at the same time the through holes 11, 11, . . .
The structure may be such that it is also filled with a conductive paste to ensure conduction on both sides of the substrate (FIG. 3(f)).
更に図示は省略するが前記リード端子２，２，
…或は３，３，…の少なくとも一本を前記導体基
板１と切り離すことなく作成すれば該リード端子
を介して導体基板の接地を容易ならしめることが
できる。 Furthermore, although not shown, the lead terminals 2, 2,
Alternatively, if at least one of the lead terminals 3, 3, .
尚、上述の実施例に於いてはDIP型の基板につ
いてのみ説明したが本発明をリード端子が単列の
SIP型に適用可能であることも自明であろう。 In the above embodiment, only a DIP type board was described, but the present invention can also be applied to a single row of lead terminals.
It is also obvious that this method can be applied to the SIP type.
（発明の効果）
本発明は以上説明した如く構成するので従来の
セラミクス基板或はプラスチツクス積層基板の如
く別個にリード端子を接続固定する工程を必要と
しないから製造コストを低減することが可能であ
るのみならずセラミクス基板の如く高価な材料を
使用する必要がなくスルーホール等の加工も簡単
であるので総合的に安価な配線基板を提供するこ
とが可能となるからハイブリツドIC等を安価に
製造する上で著しい効果を発揮する。(Effects of the Invention) Since the present invention is constructed as described above, there is no need for a separate step of connecting and fixing lead terminals as in conventional ceramic substrates or plastic laminated substrates, so manufacturing costs can be reduced. Not only that, but there is no need to use expensive materials such as ceramic substrates, and processing of through holes etc. is easy, making it possible to provide an overall inexpensive wiring board, making it possible to manufacture hybrid ICs etc. at low cost. It has a remarkable effect on
第１図及び第２図は夫々本発明に係るメタルコ
ア配線基板の一実施例を示す斜視図及びＡ−Ａ断
面図、第３図ａ乃至ｄはその製造工程の一実施例
を示す図、第４図ａ乃至ｉは本発明に係る他のメ
タルコア配線基板の製造工程を示す図である。
１……導体基板、２及び３……リード端子、４
……絶縁被覆、５……導体パターン。
1 and 2 are a perspective view and an A-A sectional view showing an embodiment of the metal core wiring board according to the present invention, respectively, and FIGS. 3a to 3d are diagrams showing an embodiment of the manufacturing process thereof, and FIGS. 4a to 4i are diagrams showing the manufacturing process of another metal core wiring board according to the present invention. 1... Conductor board, 2 and 3... Lead terminal, 4
...Insulating coating, 5...Conductor pattern.
Claims (1)
し該被覆を利用して前記導体基板端縁に該基板と
電気的に絶縁したリードを所望の数だけ整列固定
せしめると共に前記被覆表面に所望の配線パター
ンを付着し該配線パターンと前記リードとを電気
的に接続したことを特徴とするメタルコア配線基
板。 ２ 前記導体基板の両面所要部分を絶縁物質にて
被覆すると共に前記基板に所要のスルーホールを
設け該スルーホールを介して前記基板両面の絶縁
被覆上に設けた配線パターンを接続することによ
つて基板両面に電子部品を実装し得るようにした
ことを特徴とする特許請求の範囲１記載のメタル
コア配線基板。 ３ 前記基板端縁に整列するリードが前記基板素
材の端縁部の打抜き或はエツチング等の加工々程
によつて前記基板と一体的に形成されたことを特
徴とする特許請求の範囲１又は２記載のメタルコ
ア配線基板。 ４ 前記リードの少なくとも一と前記導体基板と
の電気的接続を保持せしめることによつてこのリ
ードを介して前記導体基板を接地し得るようにし
たことを特徴とする特許請求の範囲１、２又は３
記載のメタルコア配線基板。[Scope of Claims] 1. Covering a required portion of the surface of the conductor substrate with an insulating material, and using the coating to align and fix a desired number of leads electrically insulated from the substrate to the edge of the conductor substrate, and A metal core wiring board characterized in that a desired wiring pattern is attached to the coating surface and the wiring pattern and the lead are electrically connected. 2. By coating required portions of both sides of the conductive substrate with an insulating material, and providing necessary through holes in the substrate, connecting wiring patterns provided on the insulating coatings on both sides of the substrate through the through holes. The metal core wiring board according to claim 1, characterized in that electronic components can be mounted on both sides of the board. 3. Claim 1 or 3, characterized in that the leads aligned with the edge of the substrate are formed integrally with the substrate by a process such as punching or etching the edge of the substrate material. 2. The metal core wiring board described in 2. 4. Claims 1, 2 or 4, characterized in that by maintaining an electrical connection between at least one of the leads and the conductor substrate, the conductor substrate can be grounded via this lead. 3
Metal core wiring board as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14827084A JPS6127665A (en) | 1984-07-17 | 1984-07-17 | Metal-core wiring substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14827084A JPS6127665A (en) | 1984-07-17 | 1984-07-17 | Metal-core wiring substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6127665A JPS6127665A (en) | 1986-02-07 |
| JPH0224395B2 true JPH0224395B2 (en) | 1990-05-29 |
Family
ID=15449008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14827084A Granted JPS6127665A (en) | 1984-07-17 | 1984-07-17 | Metal-core wiring substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6127665A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6222497A (en) * | 1985-07-22 | 1987-01-30 | 東洋通信機株式会社 | Metal core wiring board |
| CH691020A5 (en) * | 1996-01-15 | 2001-03-30 | Fela Holding Ag | A process for the production of injection-molded three-dimensional circuit moldings. |
| KR101231296B1 (en) | 2006-09-25 | 2013-02-07 | 엘지이노텍 주식회사 | Intelligent power module |
| JP5455468B2 (en) * | 2009-06-30 | 2014-03-26 | 矢崎総業株式会社 | Metal core substrate base material and metal core substrate manufacturing method using the metal core substrate base material |
-
1984
- 1984-07-17 JP JP14827084A patent/JPS6127665A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6127665A (en) | 1986-02-07 |
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