JPH02102594A - Hybrid integrated circuit substrate - Google Patents
Hybrid integrated circuit substrateInfo
- Publication number
- JPH02102594A JPH02102594A JP25625988A JP25625988A JPH02102594A JP H02102594 A JPH02102594 A JP H02102594A JP 25625988 A JP25625988 A JP 25625988A JP 25625988 A JP25625988 A JP 25625988A JP H02102594 A JPH02102594 A JP H02102594A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- integrated circuit
- circuit board
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 32
- 229910000679 solder Inorganic materials 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 2
- 230000000149 penetrating effect Effects 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000012528 membrane Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000006059 cover glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Combinations Of Printed Boards (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路の基板に関し、特に直接プリント
基板等への半田付けを行うリードレス構造の混成集積回
路基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit board, and more particularly to a leadless hybrid integrated circuit board that can be directly soldered to a printed circuit board or the like.
近年、電気機器の軽量化、薄型化に伴い、これらの機器
に使用される混成集積回路装置にも小型化、薄型化が要
求されてきている。このため、混成集積回路用の基板を
実装する形態も、基板に外部端子用リードフレームを取
り付けてプリント基板等に実装する構造から、混成集積
回路基板にもけた電極ランドを直接プリント基板等に実
装する、所謂リードレス構造のものが採用されている。In recent years, as electrical equipment has become lighter and thinner, hybrid integrated circuit devices used in these equipment have also been required to be smaller and thinner. For this reason, the method of mounting a hybrid integrated circuit board has changed from a structure in which a lead frame for external terminals is attached to the board and mounted on a printed circuit board, etc., to a structure in which electrode lands on the hybrid integrated circuit board are directly mounted on a printed circuit board, etc. A so-called leadless structure is used.
例えば、第4図はその一例であり、絶縁基板1の表面、
裏面に夫々形成した膜導体2,3は抵抗体5と共に所要
の回路を構成し、かつ絶縁基板1の端部に設けたスルー
ホール4によって相互に導通されている。そして、絶縁
基板1の表面、裏面は夫々絶縁膜6で被覆しているが、
端部寄りの箇所では絶縁膜6を除いて各膜導体2.3を
露呈させ、ここを外部引出し電極として構成している。For example, FIG. 4 shows an example, in which the surface of the insulating substrate 1,
The film conductors 2 and 3 formed on the back surface constitute a required circuit together with the resistor 5, and are electrically connected to each other through a through hole 4 provided at the end of the insulating substrate 1. The front and back surfaces of the insulating substrate 1 are each covered with an insulating film 6.
At a location near the end, each film conductor 2.3 is exposed except for the insulating film 6, and is configured as an external lead electrode.
このように構成した混成集積回路基板は、第5図のよう
にプリント基板11に設けた導体パターン12上に混成
集積回路基板を載置し、半田13を用いて導体パターン
12と外部引出し電極としての膜導体2,3及びスルー
ホール4を接続することで実装が行われる。The hybrid integrated circuit board constructed in this way is constructed by placing the hybrid integrated circuit board on the conductor pattern 12 provided on the printed circuit board 11 as shown in FIG. Mounting is performed by connecting the membrane conductors 2 and 3 and through holes 4 of the .
上述した従来の混成集積回路基板では、絶縁基板1の裏
面に露呈されている膜導体3がプリント基板11の表面
に近接した状態で配置されることになるため、実装用の
半田13が絶縁基板1とプリント基板11の隙間を毛細
管現象によって横方向に広がり、隣接する膜導体3を短
絡してしまうという問題がある。特に、最近の混成集積
回路の多ピン化に伴って外部引出し電極としての膜導体
3の配列ピッチが小さくなると、隣接する膜導体3間で
の半田短絡不良が著しく多くなり、電子機器の組立歩留
り及び信頼性を低下させる原因となる。In the conventional hybrid integrated circuit board described above, the film conductor 3 exposed on the back surface of the insulating substrate 1 is placed close to the surface of the printed circuit board 11, so the solder 13 for mounting is applied to the insulating substrate. There is a problem in that the gap between the film conductor 1 and the printed circuit board 11 expands laterally due to capillary action, shorting out adjacent film conductors 3. In particular, as the arrangement pitch of membrane conductors 3 as external lead-out electrodes becomes smaller due to the recent increase in the number of pins in hybrid integrated circuits, the number of solder short circuits between adjacent membrane conductors 3 increases significantly, and the assembly yield of electronic devices decreases. and cause a decrease in reliability.
本発明は隣接する電極ランドの半田による短絡を防止し
た混成集積回路基板を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit board that prevents short circuits caused by solder between adjacent electrode lands.
本発明の混成集積回路基板は、絶縁基板の表面及び裏面
に夫々膜導体の一部で構成される外部引出し電極のうち
、プリント基板に対向する側の面に形成された外部引出
し電極を絶縁膜で被覆した構成としている。In the hybrid integrated circuit board of the present invention, the external lead electrodes formed on the surface facing the printed circuit board among the external lead electrodes formed of part of the film conductor on the front and back surfaces of the insulating substrate, respectively, are connected to the insulating film. The structure is coated with
上述した構成では、絶縁基板の実装用プリント基板に対
向する側の面に形成した外部引出し電極が絶縁膜が被覆
されるので、絶縁基板とプリント基板との間に侵入する
半田によって外部引出し電極が短絡されることが防止で
きる。In the above configuration, the external lead electrode formed on the surface of the insulating board facing the mounting printed circuit board is covered with an insulating film, so that the external lead electrode is covered by the solder that enters between the insulating board and the printed circuit board. This can prevent short circuits.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.
厚さ1.0−のアルミナセラミックの′I7!A縁基板
1の表面及び裏面に夫々膜導体2,3を所要パターンに
形成し、かつ厚膜抵抗5を配設して厚膜回路を構成して
いる。これら表面、裏面の各膜導体2゜3は、絶縁基板
1の側面に設けた直径0.3mmのスルーホール4によ
って相互に電気接続している。'I7 of alumina ceramic with a thickness of 1.0-! Film conductors 2 and 3 are formed in required patterns on the front and back surfaces of the A-edge substrate 1, respectively, and a thick film resistor 5 is arranged to form a thick film circuit. These film conductors 2 and 3 on the front and back surfaces are electrically connected to each other through a through hole 4 with a diameter of 0.3 mm provided on the side surface of the insulating substrate 1.
そして、前記膜導体2,3及び厚膜抵抗5は絶縁性カバ
ーガラスからなる絶縁膜6によって被覆し、かつその端
部においては絶縁膜6を部分的に除去して外部引出し電
極を形成している。しかしながら、ここでは絶縁基板1
の側面及び表面の一部の絶縁膜6を除去して膜導体2と
スルーホール4とを露呈しているが、裏面の絶縁膜6は
除去しておらず、裏面側の膜導体3は露呈させないよう
に構成している。The film conductors 2, 3 and the thick film resistor 5 are covered with an insulating film 6 made of an insulating cover glass, and the insulating film 6 is partially removed at the ends thereof to form external extraction electrodes. There is. However, here, the insulating substrate 1
Although part of the insulating film 6 on the side surface and the front surface is removed to expose the film conductor 2 and the through hole 4, the insulating film 6 on the back side is not removed, and the film conductor 3 on the back side is exposed. It is configured so that it does not.
このように構成した混成集積回路基板は、第2図のよう
に導体パターン12を形成したプリント基板11上に載
せ、混成集積回路基板の側面のスルーホール4の箇所に
おいて半田13により導体パターン12と接続している
。そして、この構成ではプリント基板11に対向する混
成集積回路基板の裏面側では、外部引出し電極を構成す
る膜導体3が絶縁膜6により被覆されているため、半田
13がプリント基板11との間の隙間内に侵入すること
はなく、侵入した場合でも裏面の膜導体3に接触するこ
とはない。これにより、隣接する膜導体3間が微細な場
合でも、これらの間での短絡を防止することができる。The hybrid integrated circuit board thus constructed is placed on a printed circuit board 11 on which a conductive pattern 12 is formed as shown in FIG. Connected. In this configuration, on the back side of the hybrid integrated circuit board facing the printed circuit board 11, the film conductor 3 constituting the external lead electrode is covered with the insulating film 6, so that the solder 13 is connected to the printed circuit board 11. It does not enter the gap, and even if it does, it does not come into contact with the membrane conductor 3 on the back surface. Thereby, even if the distance between adjacent film conductors 3 is minute, short circuits between them can be prevented.
第3図は本発明の他の実施例の縦断面図であり、第1図
と同−又は均等な部分には同一符号を付しである。この
実施例では、絶縁基板1の表面、裏面に夫々形成した膜
導体2.3をスルーホール4或いはスルーホール7で相
互に接続するとともに、これらを絶縁性の半田レジスト
膜6Aによって被覆している。この場合でも側面及び表
面ではレジスト膜6Aを一部除去しているが、裏面では
レジスト膜6Aを除去しておらず、外部引出し電極とし
ての膜導体3を被覆している。FIG. 3 is a longitudinal sectional view of another embodiment of the present invention, in which the same or equivalent parts as in FIG. 1 are given the same reference numerals. In this embodiment, film conductors 2.3 formed on the front and back surfaces of an insulating substrate 1 are connected to each other through a through hole 4 or a through hole 7, and these are covered with an insulating solder resist film 6A. . In this case as well, a portion of the resist film 6A is removed from the side surface and the front surface, but the resist film 6A is not removed from the back surface, and the film conductor 3 serving as the external extraction electrode is covered.
この構成においても、第1図及び第2図と同様に半田に
よる隣接膜導体間の短絡を防止できる。In this configuration as well, short circuits between adjacent film conductors due to solder can be prevented as in FIGS. 1 and 2.
以上説明したように本発明は、絶縁基板に設けた膜導体
の一部で構成される外部引出し電極のうち、プリント基
板に対向する側の面の外部引出し電極を絶縁膜で被覆し
ているので、混成集積回路基板をプリント基板に実装す
る際の半田が絶縁基板とプリント基板との間に侵入して
隣接する外部引出し電極を短絡することが防止でき、信
頼性の高い実装構造を得ることができる。As explained above, the present invention covers the external lead electrode on the side facing the printed circuit board with an insulating film, among the external lead electrodes formed of a part of the film conductor provided on the insulated substrate. When mounting a hybrid integrated circuit board on a printed circuit board, it is possible to prevent solder from entering between the insulating board and the printed circuit board and short-circuiting adjacent external lead-out electrodes, making it possible to obtain a highly reliable mounting structure. can.
第1図は本発明の一実施例の縦断面図、第2図は実装状
態を示す縦断面図、第3図は本発明の他の実施例の縦断
面図、第4図は従来の混成集積回路基板の縦断面図、第
5図は従来の実装状態を示す縦断面図である。
1・・・絶縁基板、2・・・表面膜導体、3・・・裏面
膜導体、4・・・スルーホール、5・・・厚膜抵抗、6
・・・絶縁膜、6A・・・半田レジスト、7・・・スル
ーホール、11・・・プリント基板、12・・・導体パ
ターン、13・・・半田。
第2
第3FIG. 1 is a longitudinal sectional view of one embodiment of the present invention, FIG. 2 is a longitudinal sectional view showing the mounting state, FIG. 3 is a longitudinal sectional view of another embodiment of the invention, and FIG. 4 is a conventional hybrid FIG. 5 is a vertical cross-sectional view of the integrated circuit board showing a conventional mounting state. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Surface film conductor, 3... Back film conductor, 4... Through hole, 5... Thick film resistor, 6
...Insulating film, 6A...Solder resist, 7...Through hole, 11...Printed circuit board, 12...Conductor pattern, 13...Solder. 2nd 3rd
Claims (1)
外部引出し電極として構成し、この外部引出し電極を実
装用プリント基板に半田付けする混成集積回路基板にお
いて、前記プリント基板に対向する側の面に構成された
外部引出し電極を絶縁膜で被覆したことを特徴とする混
成集積回路基板。1. In a hybrid integrated circuit board in which part of the film conductor formed on the front and back surfaces of an insulating substrate is configured as an external lead-out electrode, and this external lead-out electrode is soldered to a printed circuit board for mounting, the surface facing the printed board What is claimed is: 1. A hybrid integrated circuit board, characterized in that an external lead-out electrode configured in the following manner is covered with an insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25625988A JPH02102594A (en) | 1988-10-12 | 1988-10-12 | Hybrid integrated circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25625988A JPH02102594A (en) | 1988-10-12 | 1988-10-12 | Hybrid integrated circuit substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02102594A true JPH02102594A (en) | 1990-04-16 |
Family
ID=17290155
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25625988A Pending JPH02102594A (en) | 1988-10-12 | 1988-10-12 | Hybrid integrated circuit substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02102594A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0537111A (en) * | 1991-07-31 | 1993-02-12 | Marantz Japan Inc | Mounting structure of hybrid ic |
WO2001022501A1 (en) * | 1999-09-21 | 2001-03-29 | Osram Opto Semiconductors Gmbh & Co. Ohg | Electronic component and coating agent |
-
1988
- 1988-10-12 JP JP25625988A patent/JPH02102594A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0537111A (en) * | 1991-07-31 | 1993-02-12 | Marantz Japan Inc | Mounting structure of hybrid ic |
WO2001022501A1 (en) * | 1999-09-21 | 2001-03-29 | Osram Opto Semiconductors Gmbh & Co. Ohg | Electronic component and coating agent |
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