JPH01278755A - Lead frame and resin-sealed semiconductor device using the same - Google Patents
Lead frame and resin-sealed semiconductor device using the sameInfo
- Publication number
- JPH01278755A JPH01278755A JP63109450A JP10945088A JPH01278755A JP H01278755 A JPH01278755 A JP H01278755A JP 63109450 A JP63109450 A JP 63109450A JP 10945088 A JP10945088 A JP 10945088A JP H01278755 A JPH01278755 A JP H01278755A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- sealing resin
- semiconductor device
- groove parts
- supporting part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229920005989 resin Polymers 0.000 abstract description 33
- 239000011347 resin Substances 0.000 abstract description 33
- 238000007789 sealing Methods 0.000 abstract description 30
- 238000000034 method Methods 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 abstract description 2
- 238000010008 shearing Methods 0.000 abstract 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical class [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、大面積半導体チップを搭載する樹脂封止型の
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a resin-sealed semiconductor device mounted with a large-area semiconductor chip.
従来の技術
従来の半導体チップ搭載の樹脂封圧型半導体装置は、金
もしくは銀で１μｍ程度にメツキされた鉄−ニッケル合
金や銅などからなるリードフレームの基板支持部に半導
体チップを金−シリコン共晶や銀ペーストで固着し、そ
の後に基板支持部の周囲を取り巻くように配置されたイ
ンナーリードと半導体チップ上面の周辺部に配置された
ボンディングパノドとを金属ワイヤー（金や銅）でワイ
ヤーボンディングしてインナーリードと半導体チップを
接続していた。なお、インナーリード先端部も基板支持
部と同様に金もしくは銀で１μ？ｎ程度メツキしている
。このようにして組付けたものを１７０〜１８０’ｃ程
度の温度に加熱された成形金型にセットして、エポキシ
ノボランク系の封止樹脂を曲記金型に注入し、封止樹脂
が硬化した後にこれを金型から取り出し、リードフレー
ムのアウターリードをフォーミングおよびメツキするこ
とで、半導体チップを搭載した樹脂封止型半導体装置を
製造している。Conventional technology A conventional resin-sealed semiconductor device mounted with a semiconductor chip is a semiconductor chip mounted on a substrate supporting part of a lead frame made of iron-nickel alloy or copper plated with gold or silver to a thickness of about 1 μm using gold-silicon eutectic. After that, wire bonding is performed using a metal wire (gold or copper) between the inner leads placed around the substrate support and the bonding panod placed around the top surface of the semiconductor chip. The inner leads were connected to the semiconductor chip. In addition, the tip of the inner lead is also made of gold or silver with a thickness of 1μ, similar to the substrate support part. It is plated by about n. The assembly assembled in this way is set in a molding mold heated to a temperature of about 170 to 180'C, and an epoxy novolanc type sealing resin is injected into the mold. After curing, the resin is removed from the mold, and the outer leads of the lead frame are formed and plated to produce a resin-sealed semiconductor device equipped with a semiconductor chip.
発明が解決しようとする課題
大面積半導体チップ搭載の樹脂封止型半導体装置では、
ワイヤーボンドが終った半導体チップを１７０〜１８０
℃の温度の金型にセットし、そこへ封止用のエポキシノ
ボランク系の樹脂を注入し、硬化後、これを金型から取
り出すが、その際、半導体装置は室温（２２３°Ｃ）に
降温される。しかし、大面積半導体チップを搭載した樹
脂封止型の半導体装置はこの温度変化によって封止樹脂
と基板支持部の熱膨張係数の差により封止樹脂と基板支
持部の間に剥離を生じる。著しいものでは剥１！ＩＩ箇
所の両端で封止樹脂に亀裂を生じ、この状態で半導体装
置に冷熱サイクルをかけると、亀裂は半導体装置の表面
に向って進行する。また上記のような封止樹脂と基板支
持部の剥離が生じると、この箇所に水分漏えい経路から
進入した水が溜まり、急徹な温度上昇では水の水蒸気化
による体積膨張で半導体装置に致命的な亀裂を生じるな
どの問題がある。Problems to be Solved by the Invention In resin-sealed semiconductor devices equipped with large-area semiconductor chips,
170-180 semiconductor chips after wire bonding
The semiconductor device is placed in a mold at a temperature of 30°F (°C), and an epoxy novolanque resin for sealing is injected into it, and after it hardens, it is taken out of the mold. The temperature will drop. However, in a resin-sealed semiconductor device mounted with a large-area semiconductor chip, this temperature change causes separation between the sealing resin and the substrate support due to a difference in thermal expansion coefficient between the sealing resin and the substrate support. If it is significant, it will be removed! A crack is generated in the sealing resin at both ends of the point II, and when the semiconductor device is subjected to a cooling/heating cycle in this state, the crack progresses toward the surface of the semiconductor device. In addition, if the sealing resin and the substrate support part separate as described above, water that has entered from the water leakage path will accumulate in this area, and if the temperature rises rapidly, the volume expansion due to water evaporation will be fatal to the semiconductor device. There are problems such as the formation of cracks.
本発明は上記問題を解決するもので、封止樹脂と基板支
持部の間に剥離を生じることのない半導体装置を提供す
ることを目的とするものである。The present invention solves the above problem, and aims to provide a semiconductor device in which peeling does not occur between the sealing resin and the substrate support.
課題を解決するための手段
上記問題を解決するために本発明のリードフレームは、
基板支持部の裏面に蛇行状パターンの溝部が形成された
ものである。また本発明の樹脂封止型半導体装置は上記
リードフレームを用いて樹脂封止を行うものである。Means for Solving the Problems In order to solve the above problems, the lead frame of the present invention has the following features:
A meandering pattern of grooves is formed on the back surface of the substrate support. Further, the resin-sealed semiconductor device of the present invention performs resin sealing using the above lead frame.
作用
上記構成により、大面積半導体チップＭ載のリードフレ
ームを金型にセットし、この金型の中に封止樹脂を注入
すると、基板支持部の裏面に形成された溝部に前記封止
樹脂が流入する。この際に、溝部の形状は蛇行状パター
ンであるため、封止樹脂封入時の溝部への気体の巻き込
みは無い。この溝部に流入した封止樹脂は基板支持部の
溝部に係合して互いのスリップを防ぎ、熱収縮時に発生
する剪断応力の集中化を分散させる。これにより、半導
体装置の封止樹脂箇所の亀裂や、封止樹脂と基板支持部
の剥離は防止され、亀裂や剥離箇所に水が溜まることは
ない。したがって、大面積半導体チップの薄型、小型化
された高信頼性半導体装置を得ることができる。Effect With the above configuration, when the lead frame on which the large-area semiconductor chip M is mounted is set in the mold and the sealing resin is injected into the mold, the sealing resin is poured into the groove formed on the back surface of the substrate support. Inflow. At this time, since the shape of the groove is a meandering pattern, no gas is drawn into the groove when the sealing resin is filled. The sealing resin that has flowed into the groove engages with the groove of the substrate support to prevent mutual slippage and disperse the concentration of shear stress that occurs during thermal contraction. This prevents cracks in the sealing resin portion of the semiconductor device and peeling of the sealing resin from the substrate support, and prevents water from accumulating in the cracks and peeled portions. Therefore, it is possible to obtain a highly reliable semiconductor device having a large area semiconductor chip, which is thinner and smaller in size.
実施例 以下、本発明の一実施例を図面に基づき説明する。Example Hereinafter, one embodiment of the present invention will be described based on the drawings.
第１図（ａ）〜（Ｃ）は本発明の一実施例を示す樹脂封
止型デュアルインラインパッケージの半導体装置の製造
工程の概略断面図、第２図（ａ）〜（Ｃ）はそれぞれ同
半導体装置のリードフレームの基板支持部裏面の蛇行状
パターン例を示す下面図である。第１図（Ｃ）において
、１は大面積の半導体チップ、２はこの半導体チップｌ
を搭載するリードフレームの基板支持部で、この基板支
持部２の裏面には、たとえば第２図（ａ）に示すように
、蛇行状パターンの溝部３が、その福が０．１−１．５
ｍ 、床さは基板支持部２の板厚Ａ１０〜９０％の範囲
となるように形成されている。半導体チップ１の上面周
辺部にはボンデインクバッド４が設けられ、このボンデ
インクバッド４は基板支持部２の周囲を取り巻くように
配置されたリードフレームのインナーリード５に金線ま
たは銅線からなるワイヤ６で接続されている。FIGS. 1(a) to (C) are schematic cross-sectional views of the manufacturing process of a resin-sealed dual in-line package semiconductor device showing one embodiment of the present invention, and FIGS. 2(a) to (C) are the same. FIG. 3 is a bottom view showing an example of a meandering pattern on the back surface of a substrate support portion of a lead frame of a semiconductor device. In FIG. 1(C), 1 is a large-area semiconductor chip, and 2 is this semiconductor chip l.
As shown in FIG. 2(a), on the back surface of the substrate support portion 2 of the lead frame on which the lead frame is mounted, there is a groove portion 3 in a serpentine pattern with a width of 0.1-1. 5
m, the floor thickness is formed to be in the range of 10 to 90% of the board thickness A of the substrate support part 2. A bonding ink pad 4 is provided on the upper surface of the semiconductor chip 1, and the bonding ink pad 4 is formed of a gold or copper wire and attached to an inner lead 5 of a lead frame arranged around the substrate support 2. They are connected by wire 6.
７は半導体チップ１．基板支持部２およびワイヤ６など
を埋め込んだたとえばエポキシ系樹脂からなる封止樹脂
で、樹脂封入時に基板支持部２の溝部３に入り込んで形
成された突部８が基板支持部２の溝部３と係合している
。7 is a semiconductor chip 1. With a sealing resin made of, for example, epoxy resin, in which the substrate support 2 and wires 6 are embedded, the protrusion 8 formed by entering the groove 3 of the substrate support 2 during resin encapsulation is connected to the groove 3 of the substrate support 2. engaged.
次に、この半導体装置の製造方法について説明する。Next, a method for manufacturing this semiconductor device will be explained.
先ず、鉄−ニッケル（４２Ｎｖｔ％）合金板や銅−錫合
金板の加工により基板支持部２．インナーリード５など
を有するリードフレームを形成し、このリードフレーム
の基板支持部２の上に大面積半導体チップｌを、第１図
（ａ）に示すように、ダイボンドする。ボンド法は金−
シリコン共晶法、銀ペースト法のどちらでもよく、前者
の場合は４００〜４８０’Ｃの還元雰囲気中で行い、後
者の場合は冨温で接着して、さらに１５０〜３００°Ｃ
の空気または窒素雰囲気中で銀ペーストの硬化を行う。First, a substrate support part 2 is formed by processing an iron-nickel (42Nvt%) alloy plate or a copper-tin alloy plate. A lead frame having inner leads 5 and the like is formed, and a large area semiconductor chip 1 is die-bonded onto the substrate support portion 2 of this lead frame as shown in FIG. 1(a). Bond method is gold-
Either the silicon eutectic method or the silver paste method may be used; the former is carried out in a reducing atmosphere at 400 to 480'C, and the latter is bonded at a temperature of 150 to 300'C.
Curing of the silver paste is carried out in an air or nitrogen atmosphere.
グイボンド後、第１図（１〕）に示すように、ワイヤ６
で大面積半導体チップ１のポンディングパッド４とイン
ナーリード５の間を電気的に接続する。次いで、第１図
（Ｃ）で示すように、通常の封止樹脂７で成形する。封
止樹脂７として上述のエポキシ系樹脂を用いる場合の成
形特温度は１７０〜１８０°Ｃ程度である。成形の際、
基板支持部２の裏面に設けた溝部３には封止樹脂７が侵
入して突部８が形成される。この場合に溝部３の形状は
、点でなく線で構成され、しかも蛇行状のパターンであ
るため、気体を溝部３の中に巻き込まず、気体が残るこ
とはない。これにより封止樹脂７の突部８は基板支持部
２の溝部３に確実に係合する。After bonding, as shown in Figure 1 (1), the wire 6
The bonding pads 4 of the large area semiconductor chip 1 and the inner leads 5 are electrically connected. Next, as shown in FIG. 1(C), it is molded with a normal sealing resin 7. When the above-mentioned epoxy resin is used as the sealing resin 7, the special molding temperature is about 170 to 180°C. During molding,
The sealing resin 7 enters the groove portion 3 provided on the back surface of the substrate support portion 2, and a protrusion 8 is formed. In this case, the shape of the groove 3 is not a dot but a line and has a meandering pattern, so that gas is not drawn into the groove 3 and no gas remains. Thereby, the protrusion 8 of the sealing resin 7 reliably engages with the groove 3 of the substrate support section 2.
このように、封止樹脂７の突部８が基板支持部２の溝部
３に係合して互いのスリップを防ぎ、熱収縮時に発生す
る剪断応力の集中化を分散させる。In this way, the protrusions 8 of the sealing resin 7 engage with the grooves 3 of the substrate support 2 to prevent mutual slippage and disperse the concentration of shear stress that occurs during thermal contraction.
これにより半導体装置の封止樹脂箇所の亀裂や、封止樹
脂７と基板支持部２との剥離は防止される。This prevents cracks in the sealing resin portion of the semiconductor device and separation between the sealing resin 7 and the substrate support portion 2.
なお、基板支持部２の溝部３の蛇行状パターンは第２図
（ａ）に示すような形状に限るものではなく、第２図（
ｂ）または（Ｃ）に示すような形状のものでもよく、こ
れらの溝部３′、３〃によっても同様の効果が得られる
。Note that the meandering pattern of the groove portion 3 of the substrate support portion 2 is not limited to the shape shown in FIG. 2(a);
It may be of the shape shown in b) or (C), and the same effect can be obtained with these grooves 3', 3.
発明の効果
以上、本発明によれば、基板支持部と封止樹脂境界面で
の剥離防止効果により
○パッケージの耐湿性、耐熱衝撃性が向上するＯ薄型、
小型パッケージの信頼性が向上するなどの効果が得られ
る。As described above, according to the present invention, the moisture resistance and thermal shock resistance of the package are improved due to the effect of preventing peeling at the interface between the substrate support part and the sealing resin.
Effects such as improved reliability of small packages can be obtained.
第１図（ａ）〜（Ｃ）は本発明の一実施例を示す半導体
装置の製造工程の概略断面図、第２図（ａ）〜（Ｃ）は
それぞれ同半導体装置の基板支持部裏面に投げた溝部の
蛇行状パターン例の形状を示す下面図である。
１・・・半導体チップ、２・・・基板支持部、３ 、３
’、 ３”・・・溝部、７・・・封止樹脂、８・・・突
部。FIGS. 1(a) to (C) are schematic cross-sectional views of the manufacturing process of a semiconductor device showing one embodiment of the present invention, and FIGS. It is a bottom view which shows the shape of the example of the meandering pattern of the thrown groove part. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Substrate support part, 3, 3
', 3''...Groove portion, 7...Sealing resin, 8...Protrusion.
Claims (1)
れたリードフレーム。 ２、請求項１記載のリードフレームを用いてなる樹脂封
止型半導体装置。[Claims] 1. A lead frame in which a meandering pattern of grooves is formed on the back surface of a substrate support. 2. A resin-sealed semiconductor device using the lead frame according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63109450A JPH01278755A (en) | 1988-05-02 | 1988-05-02 | Lead frame and resin-sealed semiconductor device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63109450A JPH01278755A (en) | 1988-05-02 | 1988-05-02 | Lead frame and resin-sealed semiconductor device using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01278755A true JPH01278755A (en) | 1989-11-09 |
Family
ID=14510546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63109450A Pending JPH01278755A (en) | 1988-05-02 | 1988-05-02 | Lead frame and resin-sealed semiconductor device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01278755A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
| US5776796A (en) * | 1994-05-19 | 1998-07-07 | Tessera, Inc. | Method of encapsulating a semiconductor package |
| US5915170A (en) * | 1994-09-20 | 1999-06-22 | Tessera, Inc. | Multiple part compliant interface for packaging of a semiconductor chip and method therefor |
| US6046076A (en) * | 1994-12-29 | 2000-04-04 | Tessera, Inc. | Vacuum dispense method for dispensing an encapsulant and machine therefor |
| US6169328B1 (en) | 1994-09-20 | 2001-01-02 | Tessera, Inc | Semiconductor chip assembly |
| US6214640B1 (en) | 1999-02-10 | 2001-04-10 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages |
| US6232152B1 (en) | 1994-05-19 | 2001-05-15 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures |
| US6303985B1 (en) * | 1998-11-12 | 2001-10-16 | Micron Technology, Inc. | Semiconductor lead frame and package with stiffened mounting paddle |
| US6359335B1 (en) | 1994-05-19 | 2002-03-19 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures |
| US6686015B2 (en) | 1996-12-13 | 2004-02-03 | Tessera, Inc. | Transferable resilient element for packaging of a semiconductor chip and method therefor |
| US6870272B2 (en) | 1994-09-20 | 2005-03-22 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
| US7112879B2 (en) | 1995-10-31 | 2006-09-26 | Tessera, Inc. | Microelectronic assemblies having compliant layers |
| US7215010B2 (en) * | 2000-03-03 | 2007-05-08 | Infineon Technologies Ag | Device for packing electronic components using injection molding technology |
| US7665101B2 (en) * | 2005-06-20 | 2010-02-16 | Sanyo Electric Co., Ltd. | Optical pickup apparatus |
| USRE43404E1 (en) | 1996-03-07 | 2012-05-22 | Tessera, Inc. | Methods for providing void-free layer for semiconductor assemblies |
| JP2021092414A (en) * | 2019-12-09 | 2021-06-17 | 金川 典代 | Crack extraction method |
-
1988
- 1988-05-02 JP JP63109450A patent/JPH01278755A/en active Pending
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| US6232152B1 (en) | 1994-05-19 | 2001-05-15 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures |
| US5776796A (en) * | 1994-05-19 | 1998-07-07 | Tessera, Inc. | Method of encapsulating a semiconductor package |
| US6359335B1 (en) | 1994-05-19 | 2002-03-19 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures |
| US6133639A (en) * | 1994-09-20 | 2000-10-17 | Tessera, Inc. | Compliant interface for semiconductor chip and method therefor |
| US6521480B1 (en) | 1994-09-20 | 2003-02-18 | Tessera, Inc. | Method for making a semiconductor chip package |
| US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
| US6169328B1 (en) | 1994-09-20 | 2001-01-02 | Tessera, Inc | Semiconductor chip assembly |
| US6870272B2 (en) | 1994-09-20 | 2005-03-22 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
| US6723584B2 (en) | 1994-09-20 | 2004-04-20 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
| US6525429B1 (en) | 1994-09-20 | 2003-02-25 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
| US5915170A (en) * | 1994-09-20 | 1999-06-22 | Tessera, Inc. | Multiple part compliant interface for packaging of a semiconductor chip and method therefor |
| US6046076A (en) * | 1994-12-29 | 2000-04-04 | Tessera, Inc. | Vacuum dispense method for dispensing an encapsulant and machine therefor |
| US6126428A (en) * | 1994-12-29 | 2000-10-03 | Tessera, Inc. | Vacuum dispense apparatus for dispensing an encapsulant |
| US7112879B2 (en) | 1995-10-31 | 2006-09-26 | Tessera, Inc. | Microelectronic assemblies having compliant layers |
| USRE43404E1 (en) | 1996-03-07 | 2012-05-22 | Tessera, Inc. | Methods for providing void-free layer for semiconductor assemblies |
| US6686015B2 (en) | 1996-12-13 | 2004-02-03 | Tessera, Inc. | Transferable resilient element for packaging of a semiconductor chip and method therefor |
| US6303985B1 (en) * | 1998-11-12 | 2001-10-16 | Micron Technology, Inc. | Semiconductor lead frame and package with stiffened mounting paddle |
| US6214640B1 (en) | 1999-02-10 | 2001-04-10 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages |
| US7215010B2 (en) * | 2000-03-03 | 2007-05-08 | Infineon Technologies Ag | Device for packing electronic components using injection molding technology |
| US7665101B2 (en) * | 2005-06-20 | 2010-02-16 | Sanyo Electric Co., Ltd. | Optical pickup apparatus |
| US7934226B2 (en) | 2005-06-20 | 2011-04-26 | Sanyo Electric Co., Ltd. | Optical pickup apparatus |
| JP2021092414A (en) * | 2019-12-09 | 2021-06-17 | 金川 典代 | Crack extraction method |
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