JPH01259554A - Manufacture of bipolar mos hybrid semiconductor device - Google Patents

Abstract

PURPOSE:To improve characteristics of a bipolar transistor without deteriorating those of a MOS transistor, by forming the bipolar transistor above a buried layer formed by diffusion of impurity with a large diffusion coefficient and by forming a MOS transistor above the buried layer formed by diffusion of impurity with a small diffusion coefficient. CONSTITUTION:A right-side impurity layer 202 is formed on an Si substrate 101 by arsenic with a relatively large diffusion coefficient and a left-side impurity layer 203 is formed by antimony with a small diffusion coefficient. Then, the thickness of a part 103a above a buried layer 202 in a P-type Si layer 103 becomes thinner than that of the part 103b above a buried layer 203a. Then, a bipolar transistor is formed on the right side and a MOS transistor is formed on the left side to enable the thickness of an N well 104a in the bipolar transistor to be thinner while maintaining the thickness of an N well 104b in the MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a bipolar/MO5 hybrid semiconductor device.

(Prior Art) A conventional method for manufacturing Bi-CMO3 (bipolar CMO3) will be described.

In FIG. 2(a), 1 is a P-type Si semiconductor substrate. An N-type impurity such as antimony is diffused into a region on the surface of the substrate 1 where an element is to be formed, thereby forming an N+ region 2. 1 N
Region 2 is a region that will become a buried layer in the future.

Next, as shown in FIG. 3B, a P-shaped t-layer 3 is formed on the substrate 1 by epitaxial growth.

At this time, the N 2 region 2 is diffused and expanded vertically and horizontally as shown in FIG. 2B due to the thermal process of epitaxial growth, and becomes diffused N 2 regions (buried layers) 2 a and 2 b.

These diffused N+ regions a and 2b are further enlarged by a subsequent thermal process.

Thereafter, as shown in FIG. 2C, a bipolar transistor is formed on the right side, and a MOS transistor is formed on the left side. That is, in forming the right bipolar transistor, an N well 4 is formed above the diffused N+ region (buried layer) 2b, and a P well (not shown) is also formed in some cases. A collector N" 5, a base P" 7, a base P 6 and an emitter N 8 are formed in the N well 4.

Furthermore, the MOS transistor on the left side is a P-channel MO3 transistor in the case shown in the figure, but this MO3+
- When forming a transistor, an N well 4 is formed above the diffused N+ region (buried layer) 2a. 20 N well 4 with gate oxide film 10, poly-Si gate electrode 11 and P
+ Source/drain 9 is formed. Thereafter, contact holes, AΩ wiring, etc. are formed for the left and right transistors (not shown) in the same manner as for general-purpose LSIs.

In addition, in the same figure (C), 12 represents a field oxide film.

(Problems to be Solved by the Invention) Generally, in the conventional Bi-transistor (bipolar transistor) shown on the right side of FIG. 2, in order to maintain the desired performance, it is necessary to N
It is necessary to make the thickness of the intermediate region 4a sandwiched between the + region buried layer) 2b and the base P-7 smaller than a certain value. In order to further improve the performance of the Bi-transistor, it is necessary to make the thickness of the intermediate region 4 as small as possible within a range that maintains the breakdown voltage of the Bi-transistor.

However, reducing the thickness of the intermediate region (collector) 4a in the Bi-transistor on the right side of FIG. 2 naturally means that the thickness of the N well 4 in the MOS transistor on the left side also becomes thinner. When the N-well 4 becomes thinner in the left MOS transistor in this way,
The depletion layer reaches the buried layer (N'') 2a, and the dependence on the substrate voltage at the threshold becomes extremely poor.

The present invention has been made in view of the above, and its purpose is to:
An object of the present invention is to provide a method for manufacturing a bipolar-MO5 hybrid semiconductor device that can improve the characteristics of a bipolar transistor without causing deterioration in the characteristics of a MOS transistor.

Moreover, as can be seen from FIG. 2(C), the buried layers 2b, 2 on the bipolar transistor side and the MOS transistor side
a are constructed with equal thickness. For this reason, it is practically difficult to reduce the thickness of only the buried layer 2b on the bipolar transistor side to reduce the thickness of the intermediate region 4a, thereby increasing the withstand voltage of the bipolar transistor. .

The present invention has been made in view of the above, and its purpose is to:
An object of the present invention is to provide a method for manufacturing a bipolar/MO3O3 mixed semiconductor device that can improve the withstand voltage of a bipolar transistor.

[Structure of the invention]

(Means for Solving the Problems) A first method for manufacturing a bipolar/MOS hybrid semiconductor device of the present invention is to form an impurity layer by diffusing impurities into a region where an element is to be formed on the surface of a semiconductor substrate, and further to form an impurity layer in the semiconductor substrate. forming a semiconductor film layer on a substrate and diffusing impurities in the impurity layer into the semiconductor substrate and the semiconductor film layer to form a buried layer; In the method for manufacturing a bipolar/MOS hybrid semiconductor device, in which a bipolar transistor is formed in the semiconductor film layer and a MOS transistor is formed in the semiconductor film layer above another of the buried layers, the impurity has a diffusion coefficient. Using two different types of impurities, a bipolar transistor is formed above the buried layer based on an impurity with a large diffusion coefficient, and a MOS transistor is formed above the buried layer based on an impurity with a small diffusion coefficient. .

Furthermore, in the second manufacturing method of the present invention, an impurity layer is formed by diffusing an impurity into a region where an element is to be formed on the surface of a semiconductor substrate, and a semiconductor film layer is further formed on the semiconductor substrate, and the impurity layer is an impurity is diffused into the semiconductor substrate and the semiconductor film layer to form a buried layer, a bipolar transistor is formed in the semiconductor film layer above some of the buried layers, and a bipolar transistor is formed in the semiconductor film layer above some of the buried layers; In a method for manufacturing a bipolar/MOS hybrid semiconductor device in which a MOS transistor is formed in the semiconductor film layer above another, two types of impurities with different diffusion coefficients are used as the impurity, and an impurity with a small diffusion coefficient is used as the impurity. A bipolar transistor is formed above the buried layer based on the impurity, and a MOS transistor is formed above the buried layer based on the impurity having a large diffusion coefficient.

(Function) In the first method of the present invention, the buried layer formed by diffusion of an impurity with a large diffusion coefficient deeply digs into the semiconductor film layer, thereby making the semiconductor film layer thin. Therefore, when a bipolar transistor is formed in this semiconductor film layer, the distance between the buried layer and the bipolar transistor (collector thickness) becomes small. This improves the characteristics of the bipolar transistor. on the other hand,
The amount of penetration of the buried layer formed by the diffusion of impurities with a small diffusion coefficient into the semiconductor film layer is smaller than that in the case of the bipolar transistor. This makes the semiconductor film layer thicker than in the case of a bipolar transistor. When a MOS transistor is formed in this semiconductor film layer, the distance between the buried layer and the MOS transistor is larger than that of a bipolar transistor. This prevents the characteristics of the MOS transistor from deteriorating.

In the second method of the present invention, the buried layer formed by diffusion of impurities with a small diffusion coefficient only penetrates into the semiconductor film layer to a small extent, thereby making the semiconductor film layer thick.

Therefore, when a bipolar transistor is formed in this semiconductor film layer, the distance between the buried layer and the bipolar transistor (collector thickness) becomes large. This increases the breakdown voltage of the bipolar transistor.

(Example) A method according to an example of the present invention will be described with reference to FIGS. 1(a) to 1(c).

In FIG. 1(a), 101 is a P-type Si substrate. N 2 impurity is added to a region on the surface of this St substrate 101 where an element is to be formed by means such as ion implantation or diffusion to form impurity layers 202 and 203 that will become a buried layer N 2 in the future. As the N+ impurity, arsenic having a relatively large diffusion coefficient and antimony having a relatively small diffusion coefficient are used. The impurity layer 202 on the right side is formed using the arsenic, and the impurity layer 203 on the left side is formed using antimony.

Next, as shown in FIG. 6(b), the substrate 1 is
For example, a P-type Si layer 103 is formed on 01 by epitaxial growth. Due to the thermal process at this time, arsenic and antimony, which are impurities in the impurity layers 202 and 203, are diffused vertically and horizontally, and the N+ diffusion region (buried layer) 20
2a and 203a are formed. In its diffusion, arsenic diffuses more than antimony. Therefore, the buried layer 202a formed by arsenic diffusion becomes larger than the buried layer 203a formed by antimony diffusion.

As a result, the buried layer 202 in the P-shaped t-layer 103
The thickness of the upper portion 103a is thinner than the thickness of the upper portion 103b of the buried layer 203a. The difference in thickness between the upper portions 103a and 103b becomes larger due to the diffusion of arsenic and antimony in the subsequent thermal process.

Next, as shown in FIG. 2C, a Bi-transistor is formed on the right side and a MOS transistor is formed on the left side in the same manner as in the conventional case of FIG. 2C. That is, in forming the right bipolar transistor, an N well 104A is formed above the diffused N+ region (buried layer) 202a, and a P well (not shown) is also formed in some cases.

The N well 104A has a collector N 105, a base P-107, a base P''106 and an emitter N''108.
form. Also, the MOS transistor on the left side is a P-channel MOS transistor in the case shown in the figure, but
In forming this MOS transistor, an N well 104B is formed above the diffused N+ region (buried layer) 203a.

In this N well 104B, a gate oxide film 110, a poly-Si
A gate electrode 111 and a P source/drain 109 are formed. Thereafter, contact holes, AΩ wiring, etc. are formed for the left and right transistors (not shown) in the same manner as for general-purpose LSIs. In addition, in the same figure (C), 112 indicates a field oxide film.

According to the above embodiment, as can be seen from FIG. 1(c),
While keeping the thickness of the intermediate region 104b of the N-well (collector) 104B in the left MOS transistor thick, the N-well (
The thickness of the intermediate region 104a of the collector) 104A can be made thinner. Thereby, the characteristics of the Bi-transistor on the right side can be improved without causing deterioration in the characteristics of the MOS transistor on the left side.

Contrary to the above embodiment, as can be seen from FIG. 1(a),
The diffusion coefficient of N impurity in the impurity layer 202 is
It is possible to use a smaller N+ impurity than that of 03. As a result, the thickness of the buried layer on the bipolar transistor side becomes thinner, the buried layer becomes farther from the surface, and the collector N- layer becomes thicker. As a result, M
OS transistors can increase the withstand voltage of bipolar transistors while maintaining the same characteristics as conventional ones.

〔Effect of the invention〕

According to the first method of the present invention, a bipolar transistor is formed above a buried layer formed by diffusion of an impurity with a large diffusion coefficient, and a MOS transistor is formed above a buried layer formed by diffusion of an impurity with a small diffusion coefficient. By forming such a structure, the characteristics of the bipolar transistor can be improved without deteriorating the characteristics of the MOS transistor.

According to the second method of the present invention, a bipolar transistor is formed above a buried layer formed by diffusion of an impurity with a small diffusion coefficient, and a MOS transistor is formed above a buried layer formed by diffusion of an impurity with a large diffusion coefficient. By forming such a structure, the withstand voltage of the bipolar transistor can be increased without deteriorating the characteristics of the MOS transistor.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention, and FIG. 2 is a process cross-sectional view for explaining a conventional manufacturing method. 101... Semiconductor substrate, 202, 203... Impurity region, 103... Semiconductor film layer, 202a, 203a.
...Embedded layer.

Claims (1)

[Claims] 1. An impurity layer is formed by diffusing an impurity into a region where an element is to be formed on the surface of a semiconductor substrate, and a semiconductor film layer is further formed on the semiconductor substrate, and the impurities in the impurity layer are a semiconductor substrate and the semiconductor film layer to form a buried layer, a bipolar transistor being formed in the semiconductor film layer above some of the buried layers and above another of the buried layers; In the method of manufacturing a bipolar/MOS hybrid semiconductor device in which a MOS transistor is formed in the semiconductor film layer, two types of impurities with different diffusion coefficients are used as the impurity, and the buried layer is based on the impurity with a large diffusion coefficient. A method for manufacturing a bipolar/MOS mixed semiconductor device, characterized in that a bipolar transistor is formed above the buried layer and a MOS transistor is formed above the buried layer based on an impurity having a small diffusion coefficient. 2. Diffusing an impurity into a region where an element is to be formed on the surface of a semiconductor substrate to form an impurity layer, further forming a semiconductor film layer on the semiconductor substrate, and dispersing the impurities in the impurity layer into the semiconductor substrate and the semiconductor film. a bipolar transistor in the semiconductor film layer above some of the buried layers and in the semiconductor film layer above other of the buried layers; In a method of manufacturing a bipolar/MOS hybrid semiconductor device in which a MOS transistor is formed in a semiconductor device, two types of impurities with different diffusion coefficients are used as the impurity, and a bipolar transistor is formed above the buried layer based on the impurity with a small diffusion coefficient. A method for manufacturing a bipolar/MOS mixed semiconductor device, characterized in that a MOS transistor is formed above the buried layer based on an impurity having a large diffusion coefficient.