JPH01218009A - Crystal growing method - Google Patents
Crystal growing methodInfo
- Publication number
- JPH01218009A JPH01218009A JP4472988A JP4472988A JPH01218009A JP H01218009 A JPH01218009 A JP H01218009A JP 4472988 A JP4472988 A JP 4472988A JP 4472988 A JP4472988 A JP 4472988A JP H01218009 A JPH01218009 A JP H01218009A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- gaas
- grown
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000013078 crystal Substances 0.000 title claims description 12
- 238000000034 method Methods 0.000 title abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000000927 vapour-phase epitaxy Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 33
- 239000004065 semiconductor Substances 0.000 claims description 18
- 150000001875 compounds Chemical class 0.000 claims description 14
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 11
- 238000002109 crystal growth method Methods 0.000 claims description 6
- 239000002344 surface layer Substances 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 35
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Landscapes
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
■族生導体の基板上に化合物半導体を所定の厚さに結晶
成長する方法に関し、
■族生導体と化合物半導体の熱膨張率の差により発生す
る基板の反り及び成長層のクラックの低減を目的とし、
先ず上記所定の厚さより薄く成長しその成長層に溝を形
成して該成長層を複数の島状になし、しかる後、気相エ
ピタキシー法または分子線エピタキシー法により成長を
継続するように構成し、また、予め上記基板の表面に溝
を形成して表面層を複数の島状になし、しかる後、気相
エピタキシー法または分子線エピタキシー法により成長
を行うように構成する。[Detailed Description of the Invention] [Summary] Regarding a method for crystal-growing a compound semiconductor to a predetermined thickness on a substrate of a group III conductor, the substrate For the purpose of reducing warpage and cracks in the grown layer, first, the grown layer is grown to a thickness thinner than the predetermined thickness, grooves are formed in the grown layer to form a plurality of islands, and then vapor phase epitaxy or The structure is configured to continue growth by molecular beam epitaxy, and grooves are formed in advance on the surface of the substrate to form a surface layer into a plurality of islands, and then by vapor phase epitaxy or molecular beam epitaxy. Configure to grow.
本発明は、■族生導体の基板上に化合物半導体を所定の
厚さに結晶成長する方法にに関する。The present invention relates to a method for crystal-growing a compound semiconductor to a predetermined thickness on a substrate of a group (III) raw conductor.
化合物半導体は、例えばGaAsがトランジスタを高速
化させるといった具合に、半導体装置の素子形成に用い
て素子に優れた特性を付与することができる。Compound semiconductors can be used to form elements of semiconductor devices and can impart excellent characteristics to the elements, such as GaAs increasing the speed of transistors.
しかしながら化合物半導体の基板(ウェーハ)は、■族
生導体例えばSiの基板に比べて大型化が遅れており然
も強度が弱いため、半導体装置の生産効率向上を阻害し
ている。However, compound semiconductor substrates (wafers) are slower to grow in size than substrates made of group II raw conductors, such as Si, and are weaker in strength, which hinders improvements in the production efficiency of semiconductor devices.
そこで、■族生導体の基板上に化合物半導体を結晶成長
して、例えばSi基板上にGaAsを結晶成長して、G
aAs素子を形成する基板を大型化・強度増大化するこ
とが検討されている。Therefore, a compound semiconductor is grown as a crystal on a substrate of a group Ⅰ raw conductor, and for example, GaAs is grown as a crystal on a Si substrate.
Consideration is being given to increasing the size and strength of the substrate on which the aAs element is formed.
Si基板上にGaAsを結晶成長させる場合、SiとG
aAsの格子定数にずれがあるため適宜のバッファ層を
介在させて格子整合させるという複雑なことを行ってい
たが、その後、Si基板上にGaAsを直接結晶成長さ
せることが可能になってきた〔参考文献:“Si基板上
へのGaAsの成長技術”狭山、他、沖電気研究開発、
昭62年4月、第134号、 Vol、54゜No、2
. p57 )。When growing GaAs crystals on a Si substrate, Si and G
Due to the difference in the lattice constant of aAs, it was necessary to interpose an appropriate buffer layer to achieve lattice matching, which was complicated, but it has since become possible to directly grow GaAs crystals on Si substrates. Reference: “Growth technology of GaAs on Si substrate” by Sayama et al., Oki Electric Research and Development,
April 1988, No. 134, Vol. 54° No. 2
.. p57).
その場合、StとGaAsの格子不整合の影響により成
長層に多量の転位が発生する。しかし、成長層を厚くし
てくると表面側で転位が減少する〔参考文献:Grow
th and characterization o
f Ga/Geepilayers grown on
St 5ubstrates by molecul
arbeam epitaxy(分子線エピタキシーに
よるSi基板上のGa/Ge層の成長と特性)’ P、
5heldon、他、J。In that case, a large number of dislocations occur in the grown layer due to the influence of lattice mismatch between St and GaAs. However, as the growth layer becomes thicker, dislocations decrease on the surface side [Reference: Grow
th and characterization o
f Ga/Geepilayers grown on
St 5ubstrates by molecule
Arbeam epitaxy (Growth and properties of Ga/Ge layer on Si substrate by molecular beam epitaxy)'P,
5heldon, et al., J.
Appl、 Phys、 58(11)、 I Dec
、 1985. p4186)。Appl, Phys, 58(11), I Dec
, 1985. p4186).
その状況は第3図側断面図の図(a)に示される。The situation is shown in the side sectional view (a) of FIG.
同図において、1はSi基板、2は成長したGaAs層
、3は転位である。そして、GaAs素子2は、厚さを
4μ−程度以上にすると形成する素子に悪影響を与えな
い程度に表面側の転位が微少になる。In the figure, 1 is a Si substrate, 2 is a grown GaAs layer, and 3 is a dislocation. When the thickness of the GaAs element 2 is increased to about 4 .mu.m or more, dislocations on the surface side become so small that they do not adversely affect the formed element.
しかしながら、基板lを大型にし且つGaAs層2を上
記のように厚くした場合には、成長を終えて基板1を取
り出した際に、第3図(b)に示すように、基板1に反
りが発生し甚だしくはGaAs層2にクランク4が発生
する。However, when the substrate 1 is made large and the GaAs layer 2 is made thick as described above, when the substrate 1 is taken out after growth, the substrate 1 is warped as shown in FIG. 3(b). This may even cause a crank 4 to occur in the GaAs layer 2.
それは、成長が高温でなされること、GaAsの熱膨張
率(6,8X 10−’ / ℃)がStのそれ(2,
8X 10−” /℃)と大きく異なっていること、の
ため基板1が常温に復した際にGaAs層2に面方向の
引張り応力が発生し、然も、厚いGaAs層2が大型基
板1の全域に渡り繋がっていることから、その応力が基
板1の全域に繋がり基板lを湾曲させるに至らせるため
である。This is because the growth takes place at high temperatures, and the thermal expansion coefficient of GaAs (6,8 x 10-'/°C) is similar to that of St (2,8 x 10-'/°C).
8X 10-"/°C), so when the substrate 1 returns to room temperature, tensile stress occurs in the GaAs layer 2 in the plane direction, and the thick GaAs layer 2 This is because the stress is connected to the entire area of the substrate 1 and causes the substrate 1 to curve.
この現象は、Si基板上にGaAsを結晶成長した場合
に限られず、■族生導体の基板上に化合物半導体を結晶
成長した場合に共通する。This phenomenon is not limited to the case where GaAs is grown on a Si substrate, but is common when a compound semiconductor is grown on a substrate of a group III conductor.
そして、この基板の反りは、素子を形成する後工程に支
障を来し、また成長層のクランクは素子不良の原因とな
る。This warping of the substrate causes trouble in the subsequent process of forming the device, and the cranking of the growth layer causes device failure.
そこで本発明は、上述した基板の反り及び成長層のクラ
ンクを低減させる結晶成長方法の提供を目的とする。Therefore, an object of the present invention is to provide a crystal growth method that reduces the above-mentioned warping of the substrate and cranking of the grown layer.
上記目的は、■族生導体の基板上に化合物半導体を所定
の厚さに結晶成長するに際して、先ず上記所定の厚さよ
り薄く成長しその成長層に溝を形成して該成長層を複数
の島状になし、しかる後、気相エピタキシー法または分
子線エピタキシー法により成長を継続する本発明の結晶
成長方法によって達成され、また、予め上記基板の表面
に溝を形成して表面層を複数の島状になし、しかる後、
気相エピタキシー法または分子線エピタキシー法により
成長を行う本発明の結晶成長方法によって達成される。The above purpose is to first grow thinner crystals of a compound semiconductor to a predetermined thickness on a substrate of a group III conductor, and then form grooves in the grown layer to form a plurality of islands. This is achieved by the crystal growth method of the present invention in which the crystal growth is continued using a vapor phase epitaxy method or a molecular beam epitaxy method. After that,
This is achieved by the crystal growth method of the present invention in which growth is performed by vapor phase epitaxy or molecular beam epitaxy.
このようにして成長した成長層は、上記溝の部分で分断
されて繋がる範囲が上記島状の領域に限られる。The growth layer grown in this way is separated by the grooves and connected only in the island-like regions.
このため、■族生導体と化合物半導体の熱膨張率の差に
より成長層に発生する先に述べた応力はその繋がりが島
状領域の間で分断されるので、基板を大型にし成長層を
厚くしても、基板に発生する反りは微少となる。またこ
れに伴い、先に述べたクラックは島状領域に発生し難く
なる。For this reason, the above-mentioned stress generated in the growth layer due to the difference in thermal expansion coefficient between the group III raw conductor and the compound semiconductor is severed between the island-like regions, so the substrate is made larger and the growth layer is made thicker. However, the warpage that occurs on the substrate will be minimal. In addition, as a result, the cracks described above are less likely to occur in the island-like regions.
かくして、素子を形成する後工程に支障を来す基板の反
りを除去することができ、また島状領域を素子形成領域
に合わせることにより、素子不良の原因となるクランク
の発生を防止することができる。In this way, it is possible to eliminate the warpage of the substrate that interferes with the post-process of forming elements, and by aligning the island-shaped area with the element forming area, it is possible to prevent the occurrence of cranks that cause element defects. can.
以下本発明による結晶成長方法の実施例について第1図
及び第2図を用いて説明する。第1図は第1の実施例を
示す工程順側断面図(a)〜(C1と平面図(d)、第
2図は第2の実施例を示す工程順側断面図(al (b
lと平面図(el、である。Examples of the crystal growth method according to the present invention will be described below with reference to FIGS. 1 and 2. Fig. 1 is a side sectional view (a) to (C1) showing the first embodiment in the order of steps and a plan view (d), and Fig. 2 is a side sectional view in the order of steps (al (b) showing the second embodiment
l and a plan view (el).
第1の実施例を示す第1図において、先ず〔図fa)参
照〕、SiウェーハなるSt基板ll上に通常の方法で
GaAsを結晶成長して厚さ約1μ霧のGaAs層12
aを形成する。基板11の大きさは例えば5!ンである
。In FIG. 1 showing the first embodiment, first [see FIG. FA], GaAs is crystal-grown on a St substrate 11, which is a Si wafer, by a conventional method to form a GaAs layer 12 with a thickness of about 1 μm.
form a. For example, the size of the board 11 is 5! It is.
次いで〔図(bl参照〕、レジストマスク15を用いた
エツチングによりGaA、J112aに溝16を形成し
て、GaAs層12aを図(dlに示すように複数の島
状にする。Next, as shown in the figure (bl), grooves 16 are formed in the GaA layer 112a by etching using a resist mask 15, so that the GaAs layer 12a has a plurality of island shapes as shown in the figure (dl).
島状領域の各々は後工程における素子形成の領域に合わ
せて例えば約5mm角であり、溝15の幅は例えば約1
0μmである。Each of the island-like regions is, for example, approximately 5 mm square to match the area for forming elements in a subsequent process, and the width of the groove 15 is, for example, approximately 1 mm square.
It is 0 μm.
次いでc図(C1参照〕、レジストマスク15を除去し
た後、気相エピタキシー法例えばMOCVD法により、
または分子線エピタキシー法(MBE法)によりGaA
sの結晶成長を継続し、厚さ約3μmのGaAs1i1
2bを形成して所望の成長を完了する。GaAs層12
aと12bが合わさってSt基板ll上の厚さ約4pr
sのGaAs1i12となる。Next, as shown in FIG. c (see C1), after removing the resist mask 15, the vapor phase epitaxy method, for example, MOCVD method, is performed.
Or GaA by molecular beam epitaxy method (MBE method)
Continuing the crystal growth of s, GaAs1i1 with a thickness of about 3 μm
2b to complete the desired growth. GaAs layer 12
The combined thickness of a and 12b is about 4pr on the St substrate ll.
s GaAs1i12.
GaAs層12は、GaAs層12bの成長により溝1
6の部分が繋がっているように見えるが、その成長が気
相エピタキシー法または分子線エピタキシー法によるた
め、溝16の部分で分断されて繋がる範囲が上記島状の
領域となっている。The GaAs layer 12 has grooves 1 formed by the growth of the GaAs layer 12b.
Although the portions 6 appear to be connected, because the growth is by vapor phase epitaxy or molecular beam epitaxy, the ranges that are separated by the grooves 16 and connected become the island-like regions.
そして、GaAs層12の成長を終えた基板11は、先
に述べたように常温状態になっても反りが殆ど認められ
ず、その反りの大きさは高々数μm程度である。また、
GaAs1i12の各島状領域は、第3図で説明した転
位3がGaAsN2の場合と同様に分布して表面側に殆
ど認められず、然も第3図で説明したクランク4の存在
が認められない。The substrate 11 on which the GaAs layer 12 has been grown shows almost no warpage even at room temperature, and the size of the warpage is at most several micrometers. Also,
In each island region of GaAs1i12, the dislocations 3 explained in Fig. 3 are distributed in the same way as in the case of GaAsN2, and are hardly observed on the surface side, and the existence of the crank 4 explained in Fig. 3 is not observed. .
第2の実施例を示す第2図において、先ず〔図ta+a
l〕、SiウェーハなるSi基板21の表面に、レジス
トマスク25を用いたエツチングにより深さ1〜3μm
程度の溝26を形成して、基板21の表面層を図(C1
に示すように複数の島状にする。基板21の大きさは例
えば5エンであり、島状領域の各々は後工程における素
子形成の領域に合わせて例えば約5o+m角であり、溝
26の幅は例えば約10μ鴎である。In Fig. 2 showing the second embodiment, first [Fig.
1], the surface of the Si substrate 21 (Si wafer) is etched to a depth of 1 to 3 μm using a resist mask 25.
The surface layer of the substrate 21 is formed by forming grooves 26 of approximately
Make it into multiple islands as shown. The size of the substrate 21 is, for example, 5 mm, each of the island regions is, for example, about 5 square meters to match the area for forming elements in a subsequent process, and the width of the groove 26 is, for example, about 10 micrometers.
次いで〔図(bl参照〕、レジストマスク25を除去し
た後、気相エピタキシー法例えばMOCVD法により、
または分子線エピタキシー法によりGaAsを結晶成長
し、厚さ約4μ−のGaAsN22を形成して所望の成
長を完了する。Next, after removing the resist mask 25 [see figure (bl)], a vapor phase epitaxy method such as MOCVD method is performed.
Alternatively, GaAs is crystal grown by molecular beam epitaxy to form GaAsN22 with a thickness of about 4 .mu.m to complete the desired growth.
GaAs層22は、第1の実施例におけるGaAs1i
12と同様に、溝26の部分で分断されて繋がる範囲が
上記島状の領域となっている。The GaAs layer 22 is GaAs1i in the first embodiment.
12, the range that is separated and connected by the groove 26 is the island-shaped region.
そして、GaAs層22の成長を終えた基板21は、第
1の実施例の場合と同様に常温状態になっても反りが殆
ど認められず、その反りの大きさは高々数μ−程度であ
る。また、GaAs層22の各島状領域は、第3図で説
明した転位3がGaAs層2の場合と同様に分布して表
面側に殆ど認められず、然も第3図で説明したクラック
4の存在が認められない。The substrate 21 on which the GaAs layer 22 has been grown shows almost no warpage even at room temperature, as in the case of the first embodiment, and the size of the warpage is approximately several microns at most. . Furthermore, in each island region of the GaAs layer 22, the dislocations 3 explained in FIG. existence is not recognized.
なお、以上の実施例はS+基板上にGaAsを所定の厚
さに結晶成長した場合であるが、本発明の方法が■族生
導体の基板上にmv族またはIIVI族化合物半導体を
結晶成長した場合に有効であることは、上述の説明から
容易に類推されよう。Note that the above example is a case in which GaAs is crystal-grown to a predetermined thickness on an S+ substrate, but the method of the present invention is also applicable to crystal growth of an MV group or III group compound semiconductor on a substrate of a group (III) conductor. It can be easily inferred from the above explanation that it is effective in some cases.
以上説明したように本発明の構成によれば、■族生導体
の基板上に化合物半導体を所定の厚さに結晶成長する方
法において、■族生導体と化合物半導体の熱膨張率の差
により発生する基板の反り及び成長層のクラックを低減
させることができて、例えば化合物半導体素子の安定し
た生産効率向上を可能にさせる効果がある。As explained above, according to the configuration of the present invention, in the method of crystal-growing a compound semiconductor to a predetermined thickness on a substrate of a group III raw conductor, the It is possible to reduce warpage of the substrate and cracks in the grown layer, and has the effect of making it possible to stably improve the production efficiency of, for example, compound semiconductor devices.
第1図は第1の実施例を示す工程順側断面図と平面図、
第2図は第2の実施例を示す工程順側断面図と平面図、
第3図は従来の問題を示す側断面図、
である。
図において、
1 、11、21はSt基暑反、
2.12.12a 、 12b 、22はGaAs層(
成長層)、3は転位、
4はクラック、
15.25はレジストマスク、
16.26は溝、
である。
某1 K
第2の大苑イク・IE示すL希呈111灸倶・1断面図
と平面ば籠第 2 図Fig. 1 is a side sectional view and plan view in the order of steps showing the first embodiment, Fig. 2 is a sectional side view and plan view in the order of steps showing the second embodiment, and Fig. 3 is the side showing the conventional problem. This is a cross-sectional view. In the figure, 1, 11, and 21 are St-based heat resistors, and 2.12.12a, 12b, and 22 are GaAs layers (
growth layer), 3 is a dislocation, 4 is a crack, 15.25 is a resist mask, and 16.26 is a groove. A certain 1 K 2nd Daien Iku・IE shows L rare 111 moxibustion 1 sectional view and plane basket 2nd figure
Claims (1)
結晶成長するに際して、先ず上記所定の厚さより薄く成
長しその成長層に溝を形成して該成長層を複数の島状に
なし、しかる後、気相エピタキシー法または分子線エピ
タキシー法により成長を継続することを特徴とする結晶
成長方法。 2)IV族半導体の基板上に化合物半導体を結晶成長する
に際して、予め上記基板の表面に溝を形成して表面層を
複数の島状になし、しかる後、気相エピタキシー法また
は分子線エピタキシー法により成長を行うことを特徴と
する結晶成長方法。[Claims] 1) When crystal-growing a compound semiconductor to a predetermined thickness on a group IV semiconductor substrate, first, the compound semiconductor is grown thinner than the predetermined thickness, and a groove is formed in the grown layer to separate the grown layer. A crystal growth method characterized by forming a plurality of islands in the form of crystals and then continuing to grow them by vapor phase epitaxy or molecular beam epitaxy. 2) When crystal-growing a compound semiconductor on a group IV semiconductor substrate, grooves are formed in advance on the surface of the substrate to form a surface layer in the form of multiple islands, and then vapor phase epitaxy or molecular beam epitaxy is performed. A crystal growth method characterized by performing crystal growth.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4472988A JPH01218009A (en) | 1988-02-26 | 1988-02-26 | Crystal growing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4472988A JPH01218009A (en) | 1988-02-26 | 1988-02-26 | Crystal growing method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01218009A true JPH01218009A (en) | 1989-08-31 |
Family
ID=12699532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4472988A Pending JPH01218009A (en) | 1988-02-26 | 1988-02-26 | Crystal growing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01218009A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01243512A (en) * | 1988-03-25 | 1989-09-28 | Nippon Telegr & Teleph Corp <Ntt> | Formation of compound semiconductor epitaxial layer |
JP2011114160A (en) * | 2009-11-26 | 2011-06-09 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device and method of manufacturing the semiconductor substrate |
JP2011129828A (en) * | 2009-12-21 | 2011-06-30 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device, and method of manufacturing semiconductor substrate |
US10192739B2 (en) | 2011-06-30 | 2019-01-29 | Siltronic Ag | Layered semiconductor substrate with reduced bow having a group III nitride layer and method for manufacturing it |
-
1988
- 1988-02-26 JP JP4472988A patent/JPH01218009A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01243512A (en) * | 1988-03-25 | 1989-09-28 | Nippon Telegr & Teleph Corp <Ntt> | Formation of compound semiconductor epitaxial layer |
JP2011114160A (en) * | 2009-11-26 | 2011-06-09 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device and method of manufacturing the semiconductor substrate |
JP2011129828A (en) * | 2009-12-21 | 2011-06-30 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device, and method of manufacturing semiconductor substrate |
US10192739B2 (en) | 2011-06-30 | 2019-01-29 | Siltronic Ag | Layered semiconductor substrate with reduced bow having a group III nitride layer and method for manufacturing it |
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