JPH01201759A - Dma controller - Google Patents

Abstract

PURPOSE:To attain high speed data transfer by extracting control information required for a subsequent transfer cycle by means of a programmable logic array in one transfer cycle. CONSTITUTION:A data handler 16 transfers data of a system data bus 18, a system address bus 19 and an internal data bus 17, and the data handler 16 is controlled by a micro instruction outputted from a micro sequencer 14. The programmable logic array (PLA) 11 for gate control receives a transfer mode from a transfer mode register 10, and a transfer address and the number of bytes from an arithmetic and logic unit 11, judges the misalignment of the address and the like, extracts information required for the subsequent transfer cycle and gives information to the micro sequencer 14 and the handler 16. The micro sequencer 14 and the PLA 11 can execute a parallel processing.

Description

[Detailed Description of the Invention] [Summary] In a DMA IIl'm device, especially a data processing device having a CPU, the storage device and the input/output device are CP between
Regarding the DMA control device that controls DMA that directly transfers data at high speed without going through the LJ, it reduces the burden of condition judgment by microprograms, prevents the expansion of random logic hardware, and improves the bit length of data transfer. The purpose of DMA IIJ is to control data transfer using DMA, with the aim of enabling high-speed data transfer even when the
The control device has a micro-sequencer that controls each part of the DMA Ill IXI device in units of system clock cycles during the current one transfer cycle by a microprogram, and a micro-sequencer that controls the control information necessary for the next one transfer cycle. 1 corresponding to number of system clock cycles
Programmable logic output during transfer cycle
and is configured to control data transfer by a microprogram of the microsequencer and random logic of the programmable logic array.

[Industrial application field]

The present invention is a DMA (Direct Memory Access) control device, particularly a data processing device having a CPLJ (Central Processing@w), in which a storage device and an input/output device are CPU between
The present invention relates to a DMA control device that controls a DMA that directly transfers data at high speed without using a DMA controller.

(Prior Art) A conventional DMA control device performs data transfer by DMA using a microprogram or random logic.
It was 111. However, in conventional DMA, the bit length of data transfer is as small as, for example, 8.16 bits, so controlling the address and determining which byte to access is relatively simple.

Therefore, the problems of a decrease in transfer speed when a microprogram is used for DMA control and an increase in hardware (amount of material) when random logic is used are not particularly serious problems.

However, in recent DMAs, the bit length of data transfer has become thicker (for example, 32 bits).As a result, address control, byte 1IJill, and the IIIwJ signal used to control these Controlling the generated output has become extremely complex.For this reason, when considering the combination of boat size, operand size, misalignment, etc., the bit length is 32t'y.17) DMA control
Le DMA111i11 units! ! In case (7), more than 4000 combinations of data transfers are possible. Here, the boat size means the physical bit length of the peripheral input/output device, and the operand size means the logical bit length of the peripheral input/output device.

[Problem that the invention seeks to solve]

Therefore, when the bit length of data transfer is large, for example 32 bits, if a microprogram is used for DMA control, the number of program steps will be large because the condition judgment is complicated, and the data transfer will take time. The problem was that the speed decreased. On the other hand, D.M.
If random logic were used for A III Ill, the hardware would be extremely large-scale, and there would also be a problem in that it would be extremely difficult to correct the logic if there was an error in the logic design.

Therefore, the present invention reduces the burden of condition judgment by microprograms, prevents the hardware of random logic from increasing in size, and enables high-speed data transfer even when the bit length of data transfer is large. M
The purpose is to provide A Ill ¥1 equipment.

(Means for Solving the Problems) FIG. 1 is a 1111 diagram showing the principle of the present invention. In the same figure, 1
is a microsequencer, and 2 is a programmable logic array.

(Operation) The microsequencer 1 controls each part of the DMA1lli!l@fa in units of one system clock cycle during the current one transfer cycle using the microprogram. Necessary control information is output during one transfer cycle corresponding to a predetermined number of system clock cycles.DMA
The data transfer is performed by the microprogram of the microsequencer 1 and the random logic of the programmable logic array 2.

Therefore, the burden of condition judgment by the microprogram is reduced, the scale of random logic hardware is prevented from increasing, and high-speed data transfer is possible even when the bit length of data transfer is large.

〔Example〕

FIG. 2 shows an embodiment of the device of the present invention. In the same figure, 10
is the transfer mode register, and 11 is the gate control PLA (
programmable logic array), 12 is a request handler, 13 is an OR circuit, 14 is a micro sequencer, 15 is an ALU (arithmetic logic operation 1!1lF), 16
1 is a data handler, 17 is an internal data bus, 1B is a system data bus, and 19 is a system address bus.

The transfer mode register 10 is for registering transfer modes such as burst, single, dual, cycle steal, etc., and is connected to the system data bus 18.

In addition to the transfer mode from the transfer mode register 10, the PLAll is supplied with the lower two pits of the transfer address and the lower three pits of the byte count from the ALU 15.

The output of PLAll is supplied to the microsequencer 14 and internal data bus 17, as will be described later.

The request handler 12 is supplied with a transfer request from outside the DMA control device, determines the priority of the transfer request, activates the internal processing of the DMA1JII device, and notifies each part of the DMA control device of the transfer request. . The request handler 12 supplies the off circuit 13 and the microsequencer 14 with a transfer request signal TREQX for starting the internal processing. Note that the request handler 12 is, for example, DMAllll1ll! A processing request 0R-EQX other than transfer such as a 7-vote request from outside the device is supplied to the microsequencer 14.

A microprogram is stored in the microsequencer 14, and various microinstructions are sent to the OR circuit and ALU1.
5 and the data handler 16 to supply PLAAll, AL
tsm U15 and data handler 16. Note that the microphone 0 sequencer 14 is also supplied with conditions for defining a transfer mode.

ALU 15 outputs the next transfer address and byte count. Since the user arbitrarily instructs in advance how many bytes to transfer, when one transfer is completed, the ALU 15 updates the byte count and calculates how many bytes remain to be transferred. ALU 15 is connected to internal data bus 17.

The data handler 16 controls data exchange with the system bus, and generates hold requests for the CPU (not shown). This data handler 16 includes a system data bus 18 and a system address bus 19.
and an internal data bus 17.

Next, the operation of the main parts of this embodiment will be explained.

PLAll is the lower 2 of the transfer address from ALU15
Based on the bit and the lower three pits of the byte count, it is determined whether the address to be transferred is misaligned. P.L.
The 3-pit gate information Go-02 and 3-pit byte controls BCO to BC3 output by All are signals used as information for rearranging data (assembly, disassembly, etc.) in the byte swapper in the data handler 16. It is. The 1-bit next side NEXTS output by the PLAll is a signal indicating whether the primary transfer is a source transfer process or a destination transfer process.

Next side NEXTS is micro sequencer 14
It is also supplied to the data handler 16 via the internal data bus 17.

1-bit continue C0N output by PLAll
T is a signal instructing to perform the process currently being performed again. Although the user issues only one transfer request, there are cases where two transfers between the source and the destination are required within the DMA control device, so the above-mentioned continue C0NT becomes necessary. Each 1-bit byte count offset BCOFF output by PLAll
SET and address offset ADROFFSET are
This is offset information consisting of a byte count addition/subtraction value used when performing addition/subtraction within the ALL 115 and information for calculating the next transfer address. PLAl 1
The 1-bit FINAL outputted by is a signal indicating that the current transfer is the last transfer. If the address to be transferred is misaligned, there is no guarantee that the transfer will be completed in one transfer cycle, so FINAL is supplied to the microsequencer to instruct the end of the transfer.

Of the signals output by PLAll, the final (FIN)
AL) is supplied only to the microsequencer.

FIG. 3 shows the operation timing of the main parts of this embodiment. 3(a) shows the timing of the system clock CLK, FIG. 3(b) shows the timing of the processing of the PLAll, FIG. 3(C) shows the processing of the microsequencer 14, and FIG. 3(d) shows the timing of the processing of the data handler 16. Show each. Here, for convenience, it is assumed that one transfer cycle (one bus cycle) corresponds to three system clock cycles.

Therefore, PLAll basically outputs 1IlIII information necessary for the next transfer in units of 1 transfer cycle, with exceptions such as FINAL indicating current information. On the other hand, the microsequencer 14 determines in each system clock cycle how to use the internal data bus 17 during the current transfer (i.e., how to use the internal data bus 17 during the current transfer cycle).
111 Controls each part of @Yi). Additionally, data handler 16 performs data transfers to and from a source or destination during one transfer cycle.

Generally, when performing data transfer using DMA, information such as a transfer address and transfer mode for performing the transfer is first written, and then the transfer is executed. Therefore, information on how to perform the transfer can be predicted in advance. Therefore, in this embodiment, PLAII is provided to predict the information necessary for the next transfer in units of one transfer cycle, and the burden of condition judgment by the microprogram in the microsequencer 14 is reduced. High-speed data transfer is possible even when

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

According to the present invention, there is a micro-sequencer that controls each part of the DMAIII device in units of one system clock cycle during one current transfer cycle by a microprogram, and a micro-sequencer that controls each part of the DMA III device in units of one system clock cycle during one current transfer cycle, and a micro-sequencer that controls each part of the DMA III device in units of one system clock cycle during the current one transfer cycle, and a micro-sequencer that controls each part of the DMA III device in units of one system clock cycle during one current transfer cycle. Since it is equipped with a programmable logic array that outputs information for 1Jtllll during one transfer cycle corresponding to a predetermined number of system clock cycles, it reduces the burden of condition judgment by microprograms and reduces the need for random logic hardware. It is possible to prevent scale-up, and to perform high-speed data transfer even when the data transfer pit length is large, and is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block system diagram showing one embodiment of the device of the present invention, and FIG. 3 is a timing chart explaining the operation of the embodiment of FIG. In the figure, 1 is a microsequencer, 2 is a programmable logic array, 10 is a transfer mode register, and 11 is a PLA. 12 is a request handler, 13 is an OR circuit, 14 is a micro sequencer, and 15 is an ALU. 16 is a data handler, 17 is an internal data bus, 18 is a system data bus, and 19 is a system address bus. Patent applicant: Fujitsu Ltd. Fujitsu Microcomputer Systems Ltd.

Claims (1)

[Scope of Claims] (1) In a DMA control device that controls data transfer by DMA, a micro sequencer (1 ), and a programmable logic array (2) that outputs control information necessary for the next one transfer cycle during one transfer cycle corresponding to a predetermined number of system clock cycles, and a microprogram of the microsequencer. and a DMA control device that controls data transfer by random logic of the programmable logic array. (2) The programmable logic array (2) stores information (GO to G2,
2. The DMA control device according to claim 1, wherein the DMA control device outputs the signals BCO to BC3). 3. The programmable logic array (2) includes:
3. The DMA control device according to claim 1, wherein the DMA control device outputs information (NEXTS) instructing whether the next transfer is a source transfer process or a destination transfer process. (A) The programmable logic array (2) outputs information (CONT) instructing to perform the process currently being performed again. DMA described in any one of these
Control device. (5) The programmable logic array (2) includes at least information (
5. The DMA control device according to any one of claims 1 to 4, wherein the DMA control device outputs a signal (BCOFFSET, ADROFFSET). (6) The programmable logic array (2) outputs information (FINAL) indicating that the transfer currently being performed is the last transfer. DMA control device according to any one of Item 5.