JPH0982938A - Simulation method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high precision analysis of prediction or the like of characteristics change of narrow channel effect or the like, by correcting the device simulation results in the two-dimensional device simulation by multiplying an extracted correlation coefficient, and outputting the corrected device simulation results. SOLUTION: Firstly, sectional structure in the two directions of an MOS transistor, i.e., an A-A' section and a B-B' section along the channel length direction are extracted. Secondly, the form of a bird's beak 41 of an element isolation film 38 and the concentration file of channel stopper regions 39, 34 are extracted. On the basis of the extracted data, a correlation coefficient of electric characteristics is extracted from a correlation data base. Thirdly, two-dimensional device simulation is performed by using the A-A' section, and ampere-volt (I-V) characteristic is calculated. By multiplying the obtained I-V characteristic by the correlation coefficient, correction for adding three- dimensional effect is performed. The results after the correction are outputted.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to, for example, a MOSFE.
The present invention relates to a simulation method used when designing a semiconductor device such as T.

[0002]

2. Description of the Related Art Two-dimensional device simulators are currently widely used in device design, but the need for analysis in three-dimensional space is increasing with the miniaturization of VLSI devices.
In particular, the minimum MOS transistor used in recent VLSI devices has both a channel length and a channel width that are miniaturized to the submicron order, and various characteristics change due to the narrow channel effect. For this reason,
A three-dimensional device simulator is indispensable for analyzing such devices.

An example of analysis of a semiconductor device using such a three-dimensional device simulation is described in, for example, "Latest semiconductor process / device simulation technology" (Realize Co., P357-). However, as described in this document, in the conventional three-dimensional device simulation, the increase in the calculation time and the memory amount due to the increase in the number of grid points is the biggest problem. Among them, in order to reduce the calculation time, vectorization is performed using a super computer, and attempts are also made to implement the matrix solution method by hardware by assembling the processors in an array, but reducing the amount of memory. There is no effective way to do it.

Further, for example, "SMART; 3D process / device integrated simulator on supercomputer" (SDM87-76 communication technique) shows the result of 3D device simulation using a supercomputer. The need is indicated along with the model and device model. In particular, on page 21 of this document, as a simple model, the LOCOS method
Parameter related to the shape of the bird's beak of the element isolation film formed by (Local Oxidation of Silicon) (θ)
A pseudo three-dimensional process model in which the drain current changes by is shown.

[0005]

However, the simple model shown in the above-mentioned document (SDM87-76 communication technique) has the electrical characteristics other than the drain current (threshold voltage Vt).
h, avalanche breakdown voltage, etc.), and it is also possible to analyze the influence of the concentration profile (concentration distribution) of the channel stop region on the above electrical characteristics, which is sometimes a factor that cannot be ignored. There wasn't. Therefore, an object of the present invention is to perform analysis such as prediction of characteristic change such as narrow channel effect in a two-dimensional device simulation without requiring a large amount of calculation time and a memory amount unlike the conventional three-dimensional device simulation. It is to provide a semiconductor device simulation method that can be performed with higher accuracy.

[0006]

According to a first aspect of the present invention, a cross-section structure extracting step of extracting a cross-section structure of a semiconductor device in two directions and a concentration profile of a bird's beak shape and a channel stop region are extracted from the extracted cross-section structure. And a correlation extraction step of extracting a correlation coefficient representing the correlation between the bird's beak shape and concentration profile and the electrical characteristics of the transistor, and a step of performing a two-dimensional device simulation based on the cross-sectional structure of the semiconductor device in one direction. The step of performing a correction by multiplying the device simulation result by the two-dimensional device simulation by the extracted correlation coefficient and outputting the corrected device simulation result can achieve the above object. In the present invention, the correlation coefficient between the bird's beag shape and concentration profile and the electrical characteristics of the transistor is extracted as a correction term, and this is multiplied by the result of the two-dimensional device simulation based on the unidirectional sectional structure of the semiconductor device.
As a result, it is possible to predict a characteristic change such as a narrow channel effect with a certain degree of accuracy (accuracy considering a pseudo three-dimensional effect) only by performing a two-dimensional simulation without performing a three-dimensional device simulation.

According to a second aspect of the present invention, in the method for simulating a semiconductor device according to the first aspect, the step of extracting a sectional structure creates a two-dimensional sectional structure based on the device shape and concentration profile extracted by actual measurement. By doing so, the above object is achieved. In the present invention, 2
The three-dimensional cross-sectional structure is created based on the device shape and concentration profile extracted by actual measurement.

According to a third aspect of the present invention, in the method for simulating a semiconductor device according to the first aspect, the correlation extraction step includes a bird's beag shape and its length for each electrical characteristic, and a shape of a concentration profile of a channel stop region. The above-mentioned object is achieved by extracting a correlation coefficient using a correlation database that stores changes in characteristics due to concentration and concentration. In the present invention, how the respective electrical characteristics change depending on the shape of bird's beak, the length of bird's beak, and the shape and concentration of the concentration profile of the channel stop region is made into a database, and the correlation coefficient is obtained based on this database. Therefore, the simulation accuracy is improved.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will now be described in detail with reference to FIGS. FIG. 1 shows a semiconductor device simulation method according to an embodiment of the present invention. Here, a case where a MOS transistor as shown in FIGS. 2 to 4 is targeted will be described. 2 is a plan view showing the layout of each layer of the MOS transistor, and FIG.
2 is a cross-sectional view in the channel length direction (section AA ′), and FIG. 3 is a cross-sectional view in the channel width direction in FIG. 2 (BB ′)
Cross section).

First, the MO to be simulated
The structure of the S transistor will be briefly described. As shown in FIGS. 2 and 3, this MOS transistor includes a gate electrode 33 formed on a silicon substrate 31 via a gate oxide film 32 made of a silicon oxide film, and insulating film sidewalls 34 formed on both sides thereof. , 35 and the gate electrode 33
An impurity diffusion region 36 as a source / drain region formed in the surface region of the silicon substrate 31 in a self-aligning manner with
37 and. Further, as shown in FIG. 4, each element active region is separated by an element isolation film 38 made of a silicon oxide film. Below the element isolation film 38, channel stopper regions 39 and 40, which are high-concentration impurity regions for preventing unintended formation of an inversion layer and suppressing surface leak current, are formed.

Next, a device simulation method for such a MOS transistor will be described. In FIG. 1, first, the cross-sectional structures of the MOS transistor in two directions, that is, the AA ′ cross section (FIG. 3) and the BB ′ cross section (FIG. 4) along the channel length direction are extracted (step 11). . Here, the A-A 'cross section is for performing a two-dimensional simulation of a normal MOS transistor, and the BB' cross section is the shape of the bird's beak 41 at the end of the element isolation film 38 that affects the channel and the channel. This is for extracting the density profile of the stopper regions 39, 40. As a method of extracting these sectional structures, S
The extraction method based on the actual device such as IMS (Secondary Ion Mass Spectrometry) and SEM (Scanning Electron Microscope) photograph, and the result of the two-dimensional process simulator such as "SUPREM-4" The method used may be considered.

Next, the shape of the bird's beak 41 of the element isolation film 38 and the concentration profile (10) of the channel stopper regions 39, 40 are extracted from the BB 'cross section (FIG. 4) (step 12). Then, the correlation coefficient of the electrical characteristic is extracted from the correlation database 21 based on these extracted data (step 13). The correlation database 21 is
The shape and length of the bird's beak 41 and the shape and spread of the concentration profile of the channel stop region depend on the electrical characteristics (threshold voltage Vt
h, drain current, avalanche breakdown breakdown voltage, etc.) and the correlation with them are stored as a database.

Next, using the cross section AA '(FIG. 3),
A three-dimensional device simulation is performed to calculate an IV characteristic (current-voltage characteristic) (step 14). The IV characteristic thus obtained is multiplied by the correlation coefficient obtained in step 13 to perform correction for adding a three-dimensional effect. Then, the corrected result is output (step 1
5).

Next, a specific example of simulating the electrical characteristics of the semiconductor device by such a simulation method will be described. The first is a simulation of the threshold voltage Vth. Threshold voltage V
The th may change due to the influence of the concentration distribution of the channel stopper regions 39 and 40. For example, in the case of an NMOS transistor, if the impurities (boron (B)) in the channel stopper regions 39 and 40 are excessively diffused, the concentration of the channel region is affected and Vth rises. Therefore, the concentration and spread of the channel stopper region are correlated with Vth and made into a database in the database 21.
A final threshold voltage can be obtained by performing a correction to add Vth, which is a three-dimensional effect, to the Vth obtained by the two-dimensional device simulation based on the −A ′ cross section.

The second is a simulation of the drain current in the bird's beak shape. When considering the drain current (current flowing from the drain to the source) such as the Vd-Id characteristic, the effective value of the transistor width (Wef
f) needs to be decided. Therefore, in this case, the bird's beak shape of the element isolation film 38 and the channel stopper region 3 are formed.
A database 21 is prepared in the database 21 to show how the concentration profiles 9 and 40 affect the effective value of the transistor width. For example, document SD
FIG. 5 of M87-76 "SMART: 3D process / device integrated simulator on supercomputer"
As shown in (3), there is a certain correlation between the bird's beak angle of the element isolation film and the change in drain current. W
Once eff is determined, the drain current can be obtained by multiplying Weff by the current value per unit width obtained by the two-dimensional device simulation based on the AA ′ cross section.

The third is a simulation of the avalanche breakdown breakdown voltage. As shown in the above document, there is a difference in the avalanche breakdown breakdown voltage between the two-dimensional model and the three-dimensional model. This is because the effect of the actual parasitic bipolar operation caused by the substrate current flowing into the channel stopper region is smaller than the result obtained by the two-dimensional device simulation based on the AA ′ cross section, and therefore the avalanche breakdown breakdown voltage is high. Because it will rise.

Therefore, the correlation between the carrier generation due to the impact ionization which causes the substrate current and the bird's beak shape and the concentration of the channel stopper region is stored in the database 21.
By making a database in, and determining the effective value of the substrate current involved in avalanche breakdown,
The avalanche breakdown breakdown voltage is derived in consideration of the three-dimensional effect. As described above, by deriving the correlation coefficient according to the desired electrical characteristics and reflecting the correlation coefficient in the result of the two-dimensional device simulation, the pseudo 3
Dimensional device simulation can be performed.

Although the bird's beak of the MOS transistor has been described in the present embodiment, the present invention is not limited to this and can be applied to a bipolar transistor.

[0019]

According to the invention described in claim 1, the normal 2
Since the result of the three-dimensional device simulation is corrected, the three-dimensional effect can be predicted from the two-dimensional simulation without performing the three-dimensional device simulation. Therefore, a three-dimensional effect can be acquired with a short calculation time and a small memory amount.

According to the second aspect of the invention, since the device cross-sectional structure is created based on the actual measurement,
It becomes possible to perform a more accurate simulation.

According to the third aspect of the present invention, the data describing the correlation between the bird's beak shape and the concentration distribution of the channel stopper region and the electrical characteristics necessary for obtaining the correction coefficient for each electrical characteristic is stored in a database in advance. Since it is stored, the correction coefficient (correlation coefficient) can be derived efficiently and accurately.

[Brief description of drawings]

FIG. 1 is a flowchart showing a semiconductor device simulation method according to an embodiment of the present invention.

FIG. 2 is a target of the simulation method of FIG.
It is a top view showing the plane composition of an S transistor.

FIG. 3 is a cross-sectional view showing a cross-sectional structure taken along the line AA ′ in FIG.

FIG. 4 is a cross-sectional view showing a cross-sectional structure taken along the line BB ′ in FIG.

[Explanation of symbols]

 21 Correlation Database 31 Silicon Substrate 32 Gate Insulating Film 33 Gate Electrodes 36, 37 Impurity Diffusion Layer (Source / Drain Region) 38 Element Separation Film 39, 40 Channel Stopper Region 41 Bird's Beak

Claims (3)

[Claims] 1. A cross-section structure extraction step of extracting a cross-section structure of a semiconductor device in two directions; a step of extracting a bird's beagh shape and a concentration profile of a channel stop region from the extracted cross-section structure; A correlation extraction step of extracting a correlation coefficient that represents a correlation with electrical characteristics, a step of performing a two-dimensional device simulation based on a cross-sectional structure of a semiconductor device in one direction, and a device simulation result obtained by the two-dimensional device simulation. And a step of performing correction by multiplying the extracted correlation coefficient and outputting the corrected device simulation result. 2. The cross-section structure extraction step creates a two-dimensional cross-section structure based on the device shape and concentration profile extracted by actual measurement.
A method for simulating the described semiconductor device. 3. The correlation extraction step uses the correlation database that stores the bird's beak shape and its length for each electrical characteristic, and the shape of the concentration profile of the channel stop region and the characteristic change due to the concentration to obtain the correlation coefficient. The semiconductor device simulation method according to claim 1, wherein the simulation is performed.