JPH0982807A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the movement of a parasitic bipolar, to restrain a junction leak current, and to suppress the deterioration of reliability of an insulating film by a method wherein a heavily doped well layer of carrier density distribution having the highest concentration is formed deeper than the well layer on the surface side of a semiconductor substrate, with crystal defects included in the well layer. SOLUTION: A plurality of well layers 2a, 2b, 3a, 3b, 4a and 4b are formed on the main surface side of a semiconductor substrate 1. Heavily doped well layers 2b, 3b and 4b, having the carrier density distribution of highest concentrations 5, 6 and 7, are formed deeper than the well layers 2a, 3a and 4a on the surface side of the semiconductor substrate. A layer, having a crystal defect 8, is formed at least in a kind of well layer. As a result, the diffusion into the well layer of minority carrier from the side of the substrate 1 can be prevented, and the leak current of source/drain junction can be decreased. Also, a parasitic bipolar action and a soft error can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to suppression of parasitic bipolar operation which causes malfunction of a semiconductor device, suppression of junction leak current which increases power consumption of the semiconductor device, and reliability of an insulating film which deteriorates the life of the semiconductor device. The present invention relates to a high-quality and highly reliable semiconductor device that realizes the suppression of deterioration of the characteristics.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device has been disclosed in JP-A-61-206219.
As described in Japanese Patent Laid-Open Publication No. 2004-242242, there are two types of conductive type well layers, and elements are formed near the surface of the well layers. Thereby, the bias condition for the device can be set for each well. Further, a conventional semiconductor device is disclosed in
As described in Japanese Patent Laid-Open No. 2-305469, one of well layers of two types of conductivity type is surrounded by a shield layer of different conductivity type (also referred to as a well), and each well layer is provided in the vicinity of the surface. The element was formed. By forming this shield layer, the bias condition for each well can be set more freely. Furthermore, the conventional semiconductor device has a plurality of types of well layers in which the carrier concentration distribution of the well layers is retrograde, as described in Japanese Patent Laid-Open No. 63-64360, and the element is provided near the surface of each well layer. Had formed. By making the carrier concentration distribution of the well layer retrograde, the parasitic bipolar operation and the soft error can be suppressed.

[0003]

The well layer of the above conventional semiconductor device is formed so as not to include crystal defects in order to eliminate adverse effects on the elements formed on the surface of the well layer. However, due to the relationship between the characteristics of the semiconductor substrate and the thermal history of the semiconductor device manufacturing process, uncontrolled crystal defects remain in the well layer. In addition, crystal defects that cannot be controlled due to damage or contamination during the semiconductor device manufacturing process were formed in the well layer. However, the number of crystal defects in these well layers did not occur so much as to affect the characteristics of the element formed on the surface of the well layer. However, due to the influence of this uncontrollable crystal defect, there are problems that the manufacturing yield of the semiconductor device is reduced and the reduction of power consumption of the semiconductor device cannot be controlled. Further, there is a problem in that the characteristics of the insulating film forming the element change due to the influence of the crystal defect, and thus the semiconductor device may become inoperable during use.

It is an object of the present invention to suppress parasitic bipolar operation that causes malfunction of a semiconductor device, suppress junction leakage current that increases power consumption of the semiconductor device, and deteriorate reliability of an insulating film that deteriorates the life of the semiconductor device. It is to provide a high-quality and highly reliable semiconductor device by suppressing the above.

[0005]

To achieve the above object, a plurality of well layers 2a, 2b, 3a, 3b, 4a, 4b are formed on the main surface side of a semiconductor substrate 1 as shown in FIG. , The well layers 2b, 3b, 4b of high carrier concentration distribution having the maximum concentrations 5, 6, 7 are formed in a portion deeper than the well layers 2a, 3a, 4a on the surface side of the semiconductor substrate. Then, a layer having crystal defects 8 is formed in at least one type of well layer.

Here, the high-concentration well layers 2b, 3b, 4b having the carrier concentration distributions having the maximum concentrations 5, 6, 7 in the above-mentioned semiconductor substrate, and the crystal defects 8 in at least one kind of the well layers. The layer has a layer and the depth of the crystal defect 8 is made deeper than the maximum carrier concentration 5, 6, 7 of the well layer when the surface of each well layer is used as a reference.

Further, the depth of the crystal defect layer of each well layer is made different. Further, the well layer 2 having a carrier concentration distribution having a maximum concentration of 5, 6 and 7 in the above semiconductor substrate.
b, 3b, 4b, crystal defects 8 in a plurality of types of well layers
And the distance from the depth of the crystal defect 8 to the depth of the maximum carrier concentration 5, 6, 7 of the well layer is set to the first well layer 2b and the other well layers 3b, 4b other than the first well layer 2b. Change with.

Further, the maximum concentration in the semiconductor substrate is 5,
Well layers 2b, 3b having a carrier concentration distribution of 6, 7
4b has a layer having crystal defects 8 in a plurality of types of well layers, and the maximum carrier concentration of the well layer 2b is 5 from the depth of the layer having crystal defects 8 in the well layers 2a and 2b where information is stored. From the depth of the layer having crystal defects 8 in the well layers 3a, 3b, 4a, 4b of the information processing portion to the maximum carrier concentration 6, 7 of the well layers 3a, 4a. Make it shorter than the distance.

Further, the well layers 2b, 3 having a carrier concentration distribution having a maximum concentration of 5, 6, 7 in the above semiconductor substrate.
In b and 4b, at least one type of well layer has a layer having a crystal defect 8 so that the crystal defect 8 does not exist at a portion where the well layers having different conductivity types are in contact with each other.

L is formed on the surface of various well layers as described above.
MOSFETs 11 and 12 separated by the OCOS 10
13 and 14 are produced. These MOSFETs are source / drain 11a, 12a, 13a, 14 respectively.
a, gate electrodes 11b, 12b, 13b, 14b, and gate insulating films 11c, 12c, 13c, 14c.

[0011]

As shown in FIG. 1, a plurality of well layers 2a, 2b, 3a, 3b, 4a, 4 are formed on the main surface side of the semiconductor substrate 1.
b, and the well layers 2a, 3a on the front surface side of the semiconductor substrate are formed.
Diffusion of minority carriers diffused from the substrate side into the well layer by forming high concentration well layers 2b, 3b, 4b having a carrier concentration distribution having maximum concentrations 5, 6, 7 in a portion deeper than 4a. Can be prevented. This can reduce the leak current of the source / drain junction due to the diffusion of minority carriers.

Further, the well layers 2b, 3b, 4b of high concentration
As is well known, parasitic bipolar operation and soft error can be suppressed by forming the. Further, by forming the crystal defects 8 in the well layer, it is possible to collect damages and contamination in the semiconductor device manufacturing process, which are introduced on the MOSFET side, in the crystal defects 8. By forming the crystal defect 8 in the well layer where the carrier concentration is relatively high, contamination and damage can be effectively collected. As a result, it is possible to prevent generation of leakage current at the source / drain junction and deterioration of the characteristics of the gate insulating film due to damage or contamination.

Further, the well layer has a layer having crystal defects 8 and the depth of the crystal defects 8 is the maximum carrier concentration of the well layers 5, 6, 7 when the surface of each well layer is used as a reference.
By making the depth deeper than the depth of, the minority carriers generated under the influence of the crystal defects 8 can be prevented from moving to the MOSFET side. As a result, it is possible to prevent the generation of leak current at the source / drain junction due to the minority carriers.

Further, by making the depth of the crystal defect layer 8 of each well layer different, the effect of collecting damages and defects in each well layer can be controlled. Then, from the depth of the crystal defect 8, the maximum carrier concentration of the well layer is 5, 6, 7
By changing the distance to the depth of the first well layer 2b and the other well layers 3b and 4b other than the first well layer, it is possible to control the effect of collecting the contamination and damage in the crystal defects 8. become.

Here, it is necessary to change the position of the crystal defect 8 depending on the characteristics of the element formed in the well layer and the characteristics between the well layers. For example, the distance from the depth of the layer having crystal defects 8 in the well layers 2a, 2b in the information storage portion to the depth of the maximum carrier concentration 5 in the well layer 2b is defined as the well layer 3a in the information processing portion. The distance from the depth of the layer having the crystal defect 8 in 3b, 4a, 4b to the depth of the maximum carrier concentration 6, 7 of the well layers 3a, 4a is made shorter. That is, in the portion for storing information, the leakage current of the source / drain junction or the characteristic variation of the gate insulating film deteriorates the memory characteristic, and therefore it is necessary to reduce the contamination and damage most. Therefore, the crystal defects 8 need to be as close to the surface of the well layer as possible to effectively collect contamination and damage. On the other hand, in the portion for processing information, the most problem is malfunction due to the parasitic bipolar operation, the junction breakdown voltage between wells and the junction leakage current due to the leakage current of the source / drain junction and the characteristic variation of the gate insulating film. Therefore,
In order to prevent the deterioration of the junction characteristics between the wells, it is necessary to avoid the presence of the crystal defect 8 at the portion where the high concentration portion of the well layer contacts. For this reason, it is more convenient for the information processing section to have the crystal defects 8 capable of collecting contamination and damage in a relatively low concentration area. In particular, by preventing the crystal defects 8 from existing in the portions where the well layers having different conductivity types are in contact with each other, the inter-well junction characteristics of the crystal defects are not deteriorated at all.

Although the above-mentioned shield layer is not shown in FIG. 1, if a layer of the opposite conductivity type is formed under the well layer 2b, it does not affect the above operation. A well-known effect peculiar to the shield layer formation can be obtained. In this case, by making the crystal defect 8 relatively close to the high-concentration portion 5, the depletion layer of the pn junction formed by the well layer 2b and the shield layer thereunder can be prevented from spreading to the crystal defect 8. As a result, it is possible to prevent the occurrence of a leak current at this pn junction. Such a structure is effective when it corresponds to the well layer of the portion for storing the above information.

Further, as shown in FIG. 2, even when the surface positions of the well layers are different, the same operation as described above is performed. In this case, the crystal defects 8 can be formed on the same plane as the other well layers, so that the semiconductor device manufacturing process is slightly facilitated.

The present invention suppresses parasitic bipolar operation that causes malfunction of a semiconductor device, suppresses junction leakage current that increases power consumption of the semiconductor device, and suppresses reliability deterioration of an insulating film that deteriorates the life of the semiconductor device. And a semiconductor device of high quality and high reliability can be achieved.

[0019]

Embodiments of the present invention will be described below with reference to FIGS.

A structure in which the present invention is applied to a flash device which is a non-volatile memory is shown in FIG. The well layers 15a and 15b in the portion for storing information are formed by a known technique as shown in FIG.
The carrier concentration distribution and the defect density distribution as shown in FIG. In addition, the well layer in the portion that processes information is
n-type well layers 16a, 16b and p-type well layers 17a,
17b, each having a carrier concentration distribution and a defect density distribution as shown in FIG.

With such a structure, the gate insulating film 19 of the memory MOSFET 18 in the portion for storing information is formed.
It is possible to reduce the influence of contamination and damage on the gate insulating film, and it is possible to reduce the number of MOSFETs in which the information retention characteristic is deteriorated by the leak current of the gate insulating film by one digit or more as compared with the case where no defect is formed. Furthermore, the reliability of the gate insulating film 19 can be improved and the operating life can be improved. Also, a pn formed by the n-type well layer 16b and the p-type well layer 17b in the portion for processing information
Without adversely affecting the junction and the leakage current of the pn junction formed by the well layer 15b and the n-type shield layer 20 for storing information, the adverse effects such as contamination and damage on the operation of the MOSFET 21 for processing information are prevented. Since it can be eliminated, the information processing does not malfunction. The crystal defects 8 formed in the high-concentration portion of each well
By eliminating the existence of the depletion layer in the depletion layer formed between the well layers, the leak current of the pn junction can be completely ignored.

As described above, when the present invention is applied to the flash element, it is possible to improve the information retention characteristic and prevent the increase in power consumption due to the leak current due to the element operation. The concentration of crystal defects existing in the well layer is shown in FIG.
The concentration may be higher or lower than that shown in FIG. In other words, the higher the concentration, the higher the ability to collect contamination and damage, and the lower the ability to collect, the lower the concentration, but the concentration may be matched to the degree of contamination and damage in the process of manufacturing a semiconductor device.

Next, FIG. 6 shows a structure in which the present invention is applied to a dynamic random access memory device. The feature in this case is that the surfaces of the well layers have different heights. As a result, the crystal defects 8 existing in the well layer can be placed on substantially the same plane, and the defect introduction process before the semiconductor device manufacturing process can be simplified. That is, in the previous example, it was necessary to form a layer having crystal defects 8 having different depths, and the defect introduction process was complicated.

The p-type well layer 21 for storing information
a and 21b, crystal defects 8 having the distribution shown in FIG.
By coexisting with the high-concentration portion 21b, contamination and damage during the process could be efficiently collected. As a result, MOS
Since the leak current of the junction of the FET 24 in contact with the capacitor 25 can be reduced, the information retention time can be lengthened. Further, due to the crystal defects 8 in the well layers 23a, 23b, 24a, 24b having the carrier distribution and the crystal defect distribution as shown in FIG.
It was possible to obtain the same effect as that of the above-mentioned embodiment.

As can be judged from the above two embodiments, according to the present invention, it is possible to suppress not only the parasitic bipolar operation which causes a malfunction of the semiconductor device but also the junction leak current which increases the power consumption of the semiconductor device, and Since it has been possible to suppress the reliability deterioration of the insulating film which deteriorates the life of the semiconductor device, it is possible to provide a high quality and highly reliable semiconductor device.

[0026]

According to the present invention, the parasitic bipolar operation that causes the malfunction of the semiconductor device is suppressed, the junction leakage current that increases the power consumption of the semiconductor device is suppressed, and the reliability of the insulating film that deteriorates the life of the semiconductor device is suppressed. Since it is possible to suppress deterioration of the characteristics, a semiconductor device of high quality and high reliability can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view of a well structure of the present invention.

FIG. 2 is a sectional view of a well structure of the present invention.

FIG. 3 is a cross-sectional view of a flash device embodying the present invention.

FIG. 4 is a carrier distribution and crystal defect concentration distribution chart of the well layer of the present invention.

FIG. 5 is a carrier distribution and crystal defect concentration distribution chart of the well layer of the present invention.

FIG. 6 is a structural cross-sectional view of a dynamic random access memory device of an example.

FIG. 7 is a carrier distribution and crystal defect concentration distribution chart of the well layer of the example.

FIG. 8 is a carrier distribution and crystal defect concentration distribution chart of the well layer of the example.

[Explanation of symbols]

1 ... Semiconductor substrate, 2a, 3a, 4a ... Low concentration part of well layer, 2b, 3b, 4b ... High concentration part of well layer, 5, 6,
7 ... Maximum carrier concentration part, 8 ... Crystal defect, 10 ... Element isolation oxide film, 11, 12, 13, 14 ... MOSFET.

Claims (6)

[Claims] 1. A semiconductor device having a plurality of well layers, which is a well layer having a carrier concentration distribution having a maximum concentration in a semiconductor substrate and having a crystal defect layer in at least one type of well layer. apparatus. 2. In a semiconductor device having a plurality of well layers, a well layer having a carrier concentration distribution having a maximum concentration in a semiconductor substrate, at least one type of well layer having a crystal defect layer, and individual well layers. A semiconductor device characterized in that the depth of the crystal defect layer is deeper than the maximum carrier concentration depth of the well layer when the surface is taken as a reference. 3. In a semiconductor device having a plurality of well layers, a well layer having a carrier concentration distribution having a maximum concentration in a semiconductor substrate, at least one type of well layer having a crystal defect layer, and individual well layers. A semiconductor device in which the depths of crystal defect layers of individual well layers are different when the surface is used as a reference. 4. In a semiconductor device having a plurality of well layers, a well layer having a carrier concentration distribution having a maximum concentration in a semiconductor substrate, having crystal defect layers in a plurality of kinds of well layers, and having a depth of the crystal defect layer. 4. The semiconductor device according to claim 1, wherein the distance from the first well layer to the depth of the maximum carrier concentration of the well layer is different from that of the other well layers other than the first well layer. 5. A semiconductor device having a plurality of well layers, which is a well layer having a carrier concentration distribution having a maximum concentration in a semiconductor substrate, having crystal defect layers in a plurality of types of well layers, and storing information. The distance from the depth of the crystal defect layer in the well layer to the depth of the maximum carrier concentration in the well layer depends on the distance from the depth of the crystal defect layer in the portion of the information processing part to the maximum carrier concentration in the well layer. The semiconductor device according to claim 1, 2, 3, or 4, which is shorter than the distance up to that point. 6. A semiconductor device having a plurality of well layers, which is a well layer having a carrier concentration distribution having a maximum concentration in a semiconductor substrate, having a crystal defect layer in at least one kind of well layers, and having different conductivity types. The semiconductor device according to claim 1, 2, 3, 4, or 5, wherein no crystal defect exists in a portion where the well layer contacts.