JPH0964352A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the on-resistance, reduce chip area, and form a one-chip IC along with another semiconductor element. SOLUTION: A semiconductor device has a MOSFET in single drain structure with an n<+> type first buried layer 2 with a high-concentration impurity provided in a semiconductor substrate (a sub substrate 1 and a semiconductor layer 4) and at least two n<+> type impurity regions (a drain region 6 and a source region 7) formed at a p<-> type semiconductor region 5 on the first buried layer, the drain region is connected to the first buried layer by an n<+> type high- concentration-impurity region 6a, and a drain electrode D is provided on the surface of an n<+> type drain electrode formation region 8 which is connected at another part of the first buried layer and is exposed on the surface of the semiconductor substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a power MOSFET capable of obtaining a large current. More specifically, the present invention relates to a semiconductor device in which a large current can be obtained, a drain electrode is taken out from the surface side of a semiconductor substrate, and a power MOSFET can be integrated into one chip as an IC together with other elements.

[0002]

2. Description of the Related Art A conventional MOSFET having a structure as shown in FIG. 8 is known. The structure shown in FIG. 8A is a lateral MOSFET for a logic small signal transistor which has been most widely used in the past, and an n ⁺ type source region 52 and a drain region 53 are formed on a p ⁻ type semiconductor substrate 51. The insulating film 5 is formed on the inter-channel region 51a.
The gate electrode G is formed via the gate electrode 4. Note that S,
D is a source electrode and a drain electrode, respectively.

The structures shown in FIGS. 8 (b) to 8 (c) are for use in power requiring a large current, and therefore, in order to prevent an increase in on-resistance which is a problem when increasing the channel width, the structure in the vertical direction is used. Vertical MOS with a wide current path on the bottom side of the semiconductor substrate
This is the structure of the FET. In FIGS. 8B to 8C, n
An n ⁻ type semiconductor layer 62 to be a drain region is epitaxially grown on the ⁺ type sub substrate 61 to form a channel region 63a.
Forming ap ⁻ type semiconductor region 63 and an n ⁺ type source region 64. These structures are called double dephased drain structures (DMOS) because the source region 64, the channel region 63a, and the drain region 62 are separated by two diffusions.

In the structure shown in FIG. 8B, V-shaped etching is performed through the p ⁻ type semiconductor region 63 and the n ⁺ type source region 64, and the gate electrode G is formed through the insulating film 65.
Is provided, the source region 64, the channel region 63a, and the drain region 62 are formed in the vertical direction of the semiconductor substrate (the sub-substrate 61 and the semiconductor layer 62).
Is provided on the back surface of the semiconductor substrate, and a current flows in the vertical direction.

In the structure shown in FIG. 8C, the gate electrode G is a semiconductor substrate (sub-substrate 61 and semiconductor layer 62).
In order to increase the channel width, the p ⁻ type regions 63 that form the source region 64 and the channel region 63a are provided on both sides of the drain region 62 so that the current flows to the lower surface side of the semiconductor substrate. The electrode D is provided on the back surface of the semiconductor substrate.

In the structure shown in FIG. 8 (d), ap ^-- type region 56 forming a channel region 56a is formed in an n ^-- type semiconductor substrate 55 to be a drain region, and an n ⁺ -type region 56 is formed in the p ^-- type region 56. Type source region 57 is provided, and an n ⁺ type drain electrode forming region 58 is formed on the surface of the n ⁻ type semiconductor substrate 55 at a position separated from the channel region 56a by a distance h required to have a withstand voltage between the source and the drain. Is provided. This structure is a horizontal DMOS with a wide channel.
It has a structure and can be used in combination with a logic small signal transistor.

[0007]

In the structure of the logic small signal transistor shown in FIG. 8A, since the current path is the surface layer of the semiconductor substrate, the channel width is widened in order to obtain a large current. To lower the on-resistance. Therefore, in order to make a MOSFET of large current with this structure, a large area is required, and there is a problem that the chip size becomes large.

In the vertical MOSFET shown in FIGS. 8B to 8C, the current path is vertical to the semiconductor substrate, and the entire bottom surface of the semiconductor substrate can be used as the current path.
Since the drain electrode is provided on the back surface of the semiconductor substrate, there is a problem that it cannot be used as one chip together with other semiconductor elements. Further, the DMOS structure has a problem that it is difficult to control the concentration of the surface channel portion and the controllability of the threshold voltage is not good.

Further, the horizontal DMO shown in FIG.
In the SFET, as in the structure of FIG. 8A, the current path is the surface layer of the semiconductor substrate, and basically, like the logic small-signal transistor, it has a large area for a large current. There is a problem that the ON resistance is higher than that of the DMOS.

The present invention solves the drawback of the high on-resistance of such a lateral MOSFET, and also improves the vertical MOSF.
An object of the present invention is to provide a semiconductor device having a power MOSFET that improves the drawbacks of the back electrode of the ET, has a small on-resistance, a small chip area, and can be integrated into one chip IC together with other semiconductor elements, and a method for manufacturing the same. And

[0011]

According to the present invention, there is provided a semiconductor device comprising:
A high-concentration impurity first-conductivity first buried layer provided in a semiconductor substrate, and at least two first-conductivity type formed in a second-conductive-type semiconductor region on the first buried layer. A MOSFET having a single drain structure having an impurity region, wherein at least one of the first conductivity type impurity regions is connected to the first buried layer by a first conductivity type high-concentration impurity region. A drain electrode is provided on the surface of the high-concentration impurity region of the first conductivity type which is connected to the other part of the buried layer and exposed on the surface of the semiconductor substrate.

Here, the first conductivity type and the second conductivity type are
When one of the n-type and p-type of a semiconductor is the first conductivity type, it means that the other p-type or n-type is the second conductivity type.

In the semiconductor device, specifically, the MOSFET having the single drain structure is such that the source region and the drain region made of the first conductivity type impurity region are alternately formed on the surface of the second conductivity type semiconductor region. A gate electrode is provided on the gap between the source region and the drain region via an insulating film, and the drain region is connected to the first buried layer by the high-concentration impurity region of the first conductivity type. Is formed by

The gate electrodes on both sides of the drain region are
It is preferable to continuously form a thick insulating film on the drain region because a small gate electrode can be efficiently and reliably formed.

The fact that the second buried layer of the second conductivity type high-concentration impurity is provided between the source region and the first buried layer lowers the current amplification factor of the parasitic bipolar transistor. It is preferable because it can be caused.

The method of manufacturing a semiconductor device of the present invention is the method of manufacturing a semiconductor device according to claim 4, wherein (a) the first buried layer of the first conductivity type is formed on the sub-substrate of the second conductivity type. A first conductivity type impurity region for forming the second buried layer, and (b) introducing a second conductivity type impurity for forming the second buried layer,
(C) epitaxially growing a semiconductor layer of the first conductivity type,
(D) A second conductivity type semiconductor region is formed on the first buried layer at the formation location of the MOSFET having the single drain structure, and (e) at each of the formation locations of the drain region and the drain electrode formation region. A high concentration impurity region of the first conductivity type is formed by introducing a first conductivity impurity into the central portion so as to connect to the first buried layer, and (f) a second impurity region of the second conductivity type is formed in the second conductivity type semiconductor region. The source region, the drain region, and the drain electrode formation region are formed by introducing an impurity of one conductivity type.

In the above manufacturing method, growing the first conductivity type epitaxial layer between the step (a) and the step (b) is performed between the first buried layer and the second buried layer. It is preferable in that the withstand voltage can be improved.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a semiconductor device of the present invention and a method for manufacturing the same will be described.

FIG. 1 is a sectional explanatory view of an embodiment of a semiconductor device of the present invention, FIG. 2 is an explanatory view showing another embodiment, and FIGS.
4 is a diagram showing the manufacturing process of FIG. 1, and FIG. 5 is a power MOSFE.
FIG. 6 is a diagram showing a state in which a CMOSFET for logic is further provided in T, FIG. 6 is a cross-sectional explanatory diagram of still another embodiment,
FIG. 7 is a diagram showing the manufacturing process of FIG.

In FIG. 1, reference numeral 1 denotes a second conductivity type, for example, p ⁻ type sub-substrate, 2 denotes a first conductivity type, for example, n ⁺ type first buried layer, and 3 denotes a second conductivity type. Second buried layer of p ⁺ type, for example, is a first buried layer of n ⁻ type
The conductive type semiconductor layer 5 is a second conductive type semiconductor region formed of, for example, a p-well, which is formed by introducing the second conductive type impurity into the first conductive type semiconductor layer 4, and 6 is of an n ⁺ type, for example. A drain region of the first conductivity type, 7 is a source region of the same conductivity type as the drain region 6, and 8 is, for example, n.
First conductivity type drain electrode formation region of ⁺ type, 9 is n ⁺
In order to reduce the current amplification factor of the lateral parasitic bipolar transistor formed between the n-type source region 7 and the n ⁺ -type drain electrode forming region 8 and the source region 7 and the second conductivity type semiconductor region 5. This is ap ⁺ type region which is a high concentration impurity region for forming a contact extending over the same. Reference numerals 6a and 8a denote the drain region 6 and the gate electrode forming region 8 in order to electrically connect the drain region 6 and the gate electrode forming region 8 to the first buried layer 2, respectively.
Is a high-concentration impurity region of the first conductivity type formed by diffusing impurities of the same conductivity type as the respective regions. In addition, 10
Is an insulating film made of silicon oxide or silicon nitride. D
Is a drain electrode, S is a source electrode, and G is a gate electrode. Further, here, the sub-substrate 1 and the semiconductor layer 4 are collectively referred to as a semiconductor substrate.

With this structure, the source region 7 and the drain region 6
A MOSFET of which the surface layer of the second conductivity type semiconductor region (p well) 5 sandwiched between and becomes the channel region 5a, and whose on / off is controlled by the gate electrode G provided on the surface of the channel region 5a via the thin insulating film 10a. Is formed.
As a result, the carrier flow of the on-current flows from the source region 7 to the drain region 6 via the channel region 5a and from the drain region 6 to the first buried layer 2 via the high-concentration impurity region 6a. It flows into the drain electrode D through the buried layer 2, the high-concentration impurity region 8a, and the drain electrode formation region 8. In this example, the gate electrodes G on both sides of the drain region 6 are provided so as to be connected on the thick insulating film 10 on the drain region 6. With such a structure, the region occupied by the gate electrode G can be made small, and the size of the drain region immediately below can be reduced even when the width of the gate electrode portion is widened as necessary to reduce the input resistance of the gate. There is an advantage that they can be expanded together and there is no need to increase the element size.

As shown in FIG. 2 of the MOSFET having this structure (illustrated in a simplified manner in FIG. 2B),
Since a large number of source regions 7 and drain regions 6 are alternately and repeatedly provided on the first buried layer 2, a wide channel width can be formed and a large current can be obtained. Even with such a structure, each drain region 6
Since it is not necessary to form an electrode on each of the first buried layer 2 and the drain electrode D may be formed on one or two places at the end of the first buried layer 2, the source region 7 and the drain region 6 can be continuously formed in a narrow region.
Can be formed in large numbers, and a large current can be easily obtained. Moreover, the drain current is the first buried layer 2 which is the high concentration impurity region.
Since the current flows through the capacitor, the on-resistance can be sufficiently reduced. As a result, a large current can be obtained at a low voltage, and an IC with low power consumption can be realized.

Further, in the present invention, since the MOS structure has a single drain structure in which the surface impurity concentration is uniform in the channel region, the concentration control of the surface channel portion is facilitated and the controllability of the threshold voltage is improved.

In the structure shown in FIG. 1, the p ⁺ -type second buried layer 3 is composed of the n ⁺ -type semiconductor region (p well) 5 of the source region 7, the first buried layer 2 and the second conductivity type semiconductor region (p well) 5. This is to lower the current amplification factor of the parasitic bipolar transistor in the vertical direction formed between the n ⁺ type and the n ⁺ type so that the parasitic transistor does not function, and performs the same function as the p ⁺ type region 9.

As described above, in the MOSFET having the structure of the present invention, a current path is formed from the surface of the semiconductor substrate (the sub-substrate 1 and the semiconductor layer 4) toward the first buried layer 2 in the semiconductor substrate. An electric current flows in the vertical direction of the substrate. Therefore, a large current with a small on-resistance can be obtained with a small chip area. Moreover, the drain electrode D is not on the back surface side of the semiconductor substrate, but from the front surface side of the semiconductor substrate via the first buried layer 2 of high concentration impurity, the high concentration impurity region 8a, and the drain electrode formation region 8 of high concentration impurity. Taken out. Since this current path is formed in the high-concentration impurity region, the on-resistance is very small. Further, since the drain electrode D is taken out from the surface of the semiconductor substrate, it is easy to form one chip together with other logic CMOS and the like.
It is possible to obtain a semiconductor device in which a power MOSFET capable of obtaining a large current and another semiconductor element for signal processing are integrated into one chip. Further, the degree of freedom of the place where the drain electrode is formed is increased, which facilitates the layout design.

Next, the power MOSFE shown in FIG.
The manufacturing method of T will be described with reference to FIGS.

[0027] First, as shown in FIG. 3 (a), p ^-
Mask 1 made of SiO ₂ or the like on the surface of the mold sub-substrate 1
1 is formed, an opening 11a is provided at the place where the first buried layer is formed, and an n-type impurity such as phosphorus or arsenic for forming the first buried layer is introduced by diffusion or ion implantation. , N ⁺ -type regions 21 are formed.

Next, as shown in FIG. 3B, S is again formed on the surface of the sub-substrate 1 to form a second buried layer.
A mask 12 made of iO ₂ or the like is formed, and p-type impurity ions such as boron B ⁺ are implanted.

After that, as shown in FIG. 3C, n ⁻
Type semiconductor layer (n ^- Epi) 4 is epitaxially grown. At this time, the n ⁺ type region 21 and the p type impurity ions introduced in the previous step are also diffused to the semiconductor layer 4 side, and the n ⁺ type first buried layer 2 and the p ⁺ type second buried layer 2 are formed. 3 is formed.

Next, as shown in FIG. 3D, n
^- Power on the first buried layer 2 of type semiconductor layer 4 MOSF
An impurity of the second conductivity type is introduced into the formation location of ET to form, for example, the second conductivity type semiconductor region 5 of the p well (p / W).

Next, as shown in FIG. 4E, an impurity of the same conductivity type as those of the drain region and the drain electrode forming region is introduced into the central region of the drain region and the drain electrode forming region by diffusion or the like, so that the n ⁺ -type impurity is increased. Concentrated impurity regions 6a and 8a are formed. After that, the mask 15 made of silicon oxide, silicon nitride or the like is further patterned to form the p ⁺ type region 9 so as to reach the second buried layer 3. The n ⁺ -type high-concentration impurity regions 6a and 8a and the p ⁺ -type region 9 may be formed in the reverse order.

Then, as shown in FIG. 4F, the mask 16 is further patterned to form a drain region 6, a source region 7 and a drain electrode formation region 8 each of n ⁺ type by diffusion of n type impurities. To do. As a result, drain region 6 and drain electrode formation region 8 are electrically connected to first buried layer 2 via n ⁺ type high-concentration impurity regions 6a and 8a.

After that, the electrodes D, S and G are formed as shown in FIG. 1 to form the power MOS of the present invention.
The FET section is formed. The insulating film 10 made of silicon oxide, silicon nitride, or the like is removed by etching only the channel region 5a to form a thin insulating film 10a as a gate insulating film.

FIG. 5 shows a CM together with the power MOSFET section.
It is a figure which shows the CMOSFET part at the time of forming an OSFET part. The leftmost drain electrode D shown in FIG. 5 is the rightmost drain electrode D of the power MOSFET section shown in FIG. 1, and a CMOSFET section is further formed on the right side thereof.

In FIG. 5, reference numeral 31 lowers the current amplification factor of the parasitic bipolar transistor in the CMOSFET section,
In order to prevent the parasitic transistor from functioning, for example, an n ⁺ type third buried layer, 32 and 34 are CMOS
The p ⁺ region and p well (p / W) of the isolation region for separating the FET part from other regions are shown,
33 is a p-well (p / W) for forming an NMOS,
Reference numerals 36 and 37 denote PMOS source and drain regions, and 38 and 39 denote NMOS source and drain regions. The n ⁺ region and the p ⁺ region are formed at the same time when the respective regions of the power MOSFET are formed, and are formed only by masking without requiring a special process. By forming the isolation region as in this example, the power MOSFET
And the CMOS logic part can be separated into different potentials. Bi-
The same applies to CMOS.

FIG. 6 is a sectional view showing the structure of still another embodiment of the present invention. In this embodiment, after the impurities for the first buried layer 2 are introduced and before the impurities for the second buried layer are introduced, the epitaxial layer 4 of the n ⁻ type semiconductor layer 4 is introduced.
a is formed, and then n ⁺ -type impurities for the lower and lower parts 6b and 8b of the high-concentration impurity regions for connecting the drain region 6 and the drain electrode forming region 8 to the first buried layer 2 are introduced. In addition, after the p ⁺ -type impurity for the second buried layer 3 is introduced, the n ⁻ -type semiconductor layer 4b is epitaxially grown again. After that, the same structure as in FIGS. 1 and 5 is used. A power NMOS is formed by forming the p well 5, the p ⁺ type region 9, the drain region 6, the source region 7 and the drain electrode forming region 8 in the n ⁺ type. In this example, the semiconductor substrate has a laminated structure of the sub-substrate 1, the epitaxial layer 4a and the semiconductor layer 4b.

In the example shown in FIG. 6, the power NMOS FE is used.
This is an example in which T and a CMOSFET having the same structure as shown in FIG. 5 are formed. The CMOS portion is given the same reference numeral as that in FIG. 5 and its description is omitted.

Next, a method of manufacturing the semiconductor device having the structure shown in FIG. 6 will be described with reference to FIG.

[0039] First, as shown in FIG. 7 (a), p ^-
A mask 11 made of SiO ₂ or the like is formed on the surface of the mold type sub-substrate (p ⁻ −Sub) 1, and the first buried layer and the CMO are formed.
The openings 11a and 1 are formed at the place where the third buried layer for S is formed.
1b is provided and n-type impurities such as phosphorus and arsenic for forming the first buried layer and the third buried layer are introduced by diffusion or ion implantation to form the n ⁺ -type regions 21 and 22, respectively. Form.

Next, as shown in FIG. 7B, n
^{A −} type epitaxial layer (n ⁻ Epi) 4a is grown. At this time, the impurities of the n ⁺ type regions 21 and 22 also diffuse into the epitaxial layer 4a during the growth of the epitaxial layer 4a, so that the first buried layer 2 and the third buried layer 31 are formed. To be done. Subsequently, a mask 13 made of SiO ₂ or the like is formed on the surface of the epitaxial layer 4a, and an opening 13 is formed at the formation location of the drain region and the drain electrode formation region.
a and 13b are formed, n-type impurities such as phosphorus and arsenic are introduced by diffusion or ion implantation, and the bottom of the high-concentration impurity region for connection with the first buried layer in the drain region and the drain electrode formation region is formed. The n ⁺ type regions 23 and 24 for use are formed respectively.

Then, as shown in FIG. 7C, a mask 12 made of SiO ₂ or the like is formed again on the surface of the epitaxial layer 4a in order to form a second buried layer.
A p-type impurity ion such as boron B ^{+ is} implanted through the opening.

Next, as shown in FIG. 7D, the n ^-- type semiconductor layer (n ^-- Epi) 4b is epitaxially grown again. At this time, the n ⁺ -type regions 23 and 24 for the lower bottom portion are diffused and spread below the newly grown semiconductor layer 4b and the epitaxial layer 4a, and are connected to the first buried layer 2 as well as the semiconductor. Lower parts 6b and 8b of the high-concentration impurity regions for connecting to the first buried layer 2 in the drain region and the drain electrode forming region are formed so as to extend into the layer 4b. Further, the ion-implanted B ⁺ is also diffused to form the second buried layer 3. At this time, the lower bottom portion 32b of the isolation is also formed at the same time.

After that, by repeating the same procedure as shown in FIGS. 3D to 4F, a semiconductor device having the power NMOS and CMOS having the structure shown in FIG. 6 is obtained.

By growing the epitaxial layer 4a between the introduction of impurities for the first buried layer 2 and the introduction of impurities for the second buried layer 3 as in this example, the first buried layer 4a is grown. The n-type impurity for the buried layer 2 and the p-type impurity for the second buried layer 3 are not introduced into the same place and are not offset, and there is an advantage that both functions can be achieved reliably. The lower bottom portions 6b and 8b of the high-concentration impurity region are formed by the two layers of the epitaxial layer 4a and the semiconductor layer 4b, and the n ⁻ -type semiconductor layer is formed thicker. This is to solve the problem that it is difficult to reach the first buried layer 2 only by diffusion, and if the first buried layer can be reached by introducing impurities from the surface, the formation of the lower bottom portions 6b and 8b is not always necessary. Not necessary.

[0045]

According to the present invention, the power MOSFET through which a large current flows has a vertical structure in which the current flows into the first buried layer formed in the semiconductor substrate, and the drain electrode is formed from the surface of the semiconductor substrate. The structure is such that it is taken out from the surface of the semiconductor substrate via the high-concentration impurity region introduced until it reaches the first buried layer. Therefore, a power MOSFET having a small on-resistance can be obtained with a small chip size, and the gate electrode is taken out from the surface of the semiconductor substrate.
A single chip such as an ET can be easily formed, and a highly integrated semiconductor device having a high-performance power MOSFET can be obtained at low cost.

[Brief description of drawings]

FIG. 1 is a cross-sectional explanatory diagram of an embodiment of a semiconductor device of the present invention.

FIG. 2 is an explanatory diagram of another embodiment of the semiconductor device of the present invention.

FIG. 3 is a diagram showing a manufacturing process of the semiconductor device in FIG. 1;

FIG. 4 is a view showing a manufacturing process of the semiconductor device of FIG. 1;

FIG. 5 is an explanatory cross-sectional view of a CMOS portion formed together with a power MOS.

FIG. 6 is a cross-sectional explanatory view of still another embodiment of the semiconductor device of the present invention.

FIG. 7 is a diagram showing a manufacturing process of the semiconductor device in FIG. 6;

FIG. 8 is an explanatory diagram of a structure of a conventional MOSFET.

[Explanation of symbols]

 1 Sub-Substrate 2 First Buried Layer 3 Second Buried Layer 4 First Conduction Type Semiconductor Layer 5 Second Conduction Type Semiconductor Region 6 Drain Region 6a High Concentration Impurity Region 7 Source Region 8 Drain Electrode Forming Region 8a High Concentration impurity region S Source electrode D Drain electrode G Gate electrode

Claims (6)

[Claims] 1. A first-conductivity-type first buried layer of a high-concentration impurity provided in a semiconductor substrate, and at least two formed in a second-conductivity-type semiconductor region on the first buried layer. First of two
MO of single drain structure having conductivity type impurity region
SFET, at least one of the first conductivity type impurity regions is connected to the first buried layer by a first conductivity type high concentration impurity region, and another portion of the first buried layer is provided. And a drain electrode is provided on the surface of a high-concentration impurity region of the first conductivity type which is connected to the semiconductor substrate and exposed on the surface of the semiconductor substrate. 2. The single drain structure MOSFE
A source region and a drain region made of the first conductivity type impurity region are alternately formed on the surface of the second conductivity type semiconductor region, and T is provided on the gap between the source region and the drain region via an insulating film. 2. A structure in which a gate electrode is provided, wherein the drain region is connected to the first buried layer by the first-conductivity-type high-concentration impurity region.
13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein the gate electrodes on both sides of the drain region are continuously formed on a thick insulating film on the drain region. 4. The semiconductor device according to claim 2, wherein a second buried layer of a second conductivity type high-concentration impurity is provided between the source region and the first buried layer. 5. The method of manufacturing a semiconductor device according to claim 4, wherein (a) the first conductivity type for forming the first buried layer of the first conductivity type on the sub-substrate of the second conductivity type. Forming an impurity region, (b) introducing a second conductivity type impurity for forming the second buried layer, (c) epitaxially growing a first conductivity type semiconductor layer, and (d) the first At a place where the single drain structure MOSFET is formed on the buried layer of
By forming a conductive type semiconductor region, and (e) introducing a first conductive impurity into the central portion of each of the formation locations of the drain region and the drain electrode formation region so as to connect to the first buried layer. Forming a high-concentration impurity region of a first conductivity type, and (f) forming a source region, a drain region, and a drain electrode formation region by introducing a first conductivity type impurity into the second conductivity type semiconductor region. And a method for manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the first conductivity type epitaxial layer is grown between the step (a) and the step (b).