JPH0955652A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit suitable for a higher speed operation by reducing a standby current without losing a circuit operation margin even when a low power supply voltage is employed. SOLUTION: This integrated circuit has a circuit array consisting of three stages of inverter circuits I (I1, I2, I3) each comprising a series connection of a P-channel MOS transistor(TR) Mp (Mp1, Mp2, Mp3) and an N-channel MOS TR Mn (Mn1, Mn2, Mn3). Each MOS TR is formed on an SOI substrate and an input terminal of the 1st stage inverter circuit I1 is connected to a base area of the MOS TRs Mp3, Mn3 being components of the 3rd stage inverter circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of logic gates including MOS transistors.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuits has been remarkably improved, and in a G (giga) bit class semiconductor memory, hundreds of millions of semiconductor elements are integrated on one chip. Higher integration is achieved by device miniaturization,
In G-bit DRAM, the gate length is 0.15 μm
If a fine MOS transistor of a certain degree is used and the degree of integration is further increased, a MOS transistor having a gate length of 0.1 μm or less will be used.

In such a fine MOS transistor, deterioration of transistor characteristics due to generation of hot carriers and TDDB (Time Dependent Dielectric Breakdow).
n) Breakdown of the insulating film occurs. Further, in order to suppress a decrease in threshold voltage due to a shortened channel length, if the impurity concentration in the bulk (substrate region) or the channel portion is increased, the junction breakdown voltage between the source and the drain is reduced.

In order to maintain the reliability of these fine elements, it is effective to lower the power supply voltage. That is, by weakening the horizontal electric field between the source and drain, generation of hot carriers is prevented, and by weakening the vertical electric field between the gate and bulk, TDDB is prevented. Further, by lowering the power supply voltage, the reverse bias applied to the junction between the source and the bulk and between the drain and the bulk is reduced, and the withstand voltage is reduced.

FIG. 31 shows a conventional buffer circuit including three stages of inverter circuits which operate under such a low voltage. Each of the inverter circuits I1, I2, I3 is constructed by inserting a pMOS transistor and an nMOS transistor in series between the power supply terminal (Vcc) and the ground terminal (Vss). Vcc is connected to the bulk of each pMOS transistor Mp1, p2, p3, and each nMOS transistor Mn
Vss or a negative voltage is applied to the bulk of 1, n2, n3.

In order to minimize the delay time of such a buffer circuit, it is desirable that the ratio of the output capacity to the input capacity (fanout f) of each inverter circuit is 3.
The input capacitance of the inverter circuit I1 is the sum of the gate capacitances of Mp1 and Mn1, and the output capacitance is the sum of the gate capacitances of Mp2 and Mn2. The gate capacitance of a MOS transistor is proportional to the gate width when the gate length and the oxide film thickness are constant. Therefore,
If the gate widths of Mp1 and Mn1 are Wp1 and Wn1, respectively,
The gate widths of Mp2 and Mn2 are 3 × Wp1 and 3 × Wn1, respectively. Similarly, the gate widths of Mp3 and Mn3 are each 9 × W.
p1,9 × Wn1.

Next, the operation of the buffer circuit of FIG. 31 will be described with reference to FIG.
This will be described using the operation waveform of No. 2. Where Iss1 and Iss
2 and Iss3 represent currents flowing from the respective sources of Mn1, Mn2 and Mn3 to Vss. Also, Iss is Iss1
Represents the sum of Iss3. From time t0 to t1, the input voltage Vin is at the "H" level and the potential Vn of the node N1.
1, the output potential Vout becomes "L" level, and the potential Vn2 of the node N2 becomes "H" level. At this time, Mn1, Mp2, M
n3 becomes conductive and Mp1, Mn2, Mp3 become non-conductive. Mp1, M
If the absolute values of the threshold voltages of n2 and Mp3 are sufficiently high, the subthreshold current is sufficiently small, and Vn1 and Vout are Vss,
Vn2 becomes Vcc.

However, when Vcc becomes smaller due to miniaturization, it is necessary to make the absolute value of the threshold voltage smaller than that in the case where the power supply voltage is not lowered in order to obtain the operation margin of the circuit. For example, when Vcc is 0.5V, it is necessary to reduce the absolute value of the threshold voltage to about 0.1 to 0.2V. At such a low threshold voltage, the subthreshold current is as large as several tens nA to several hundreds nA. Therefore, Iss1, Iss2, and Iss3 cannot be ignored, and Vn1 and Vou
t becomes higher than Vss, and Vn2 becomes lower than Vcc.

When Vin transitions from Vcc to Vss from time t1 to t2, Mp1 becomes conductive when Vin becomes Vcc-Vtp1 (Vtp1: absolute value of threshold voltage of Mp1) or less, and Vn1
Rises. When Vn1 becomes Vtn2 (Vtn2: threshold voltage of Mn2) or more, Mn2 becomes conductive and Vn2 decreases. When Vn2 becomes lower than Vcc-Vtp3 (Vtp3: absolute value of threshold voltage of Mp3), Mp3 becomes conductive and Vout rises. At this time, Mn1, Mp2, and Mn3 transit to the non-conducting state.

From time t2 to t3, Vin is "L"
Since Vn1 and Vout are at "H" level, Vn2
Becomes "L" level. Therefore, Mn1, Mp2 and Mn3 are non-conductive. In this case, if the absolute values of the threshold voltages of Mn1, Mp2 and Mn3 are sufficiently high, the subthreshold current is sufficiently small and the output potential Vout is charged to Vcc. However, since the absolute value of the threshold voltage needs to be lowered under a low voltage as described above, Vn1 and Vout are V
The potential becomes lower than cc, Vn2 becomes higher than Vss, and the standby current also increases.

FIG. 33 shows a MOS corresponding to a lower power supply voltage.
A conventional example of a complementary logic gate using a transistor is shown. M3 and M4 are complementary signals IN,
This is an nMOS transistor to which / IN is input, the sources are commonly connected to Vss, and the complementary signals OUT and / OUT are output from the drains, respectively. Then, Vss or a negative voltage is applied to the p-type region which is a bulk.
M1 and M2 are pMOS transistors whose gates are cross-connected to OUT and / OUT, the sources are commonly connected to Vcc, and the drains are OUT and / OU, respectively.
Connected to T. The bulk n-type region is connected to Vcc.

The operation of this logic gate is shown in FIG.
This will be described with reference to the timing chart of (b). Input signal I
N and / IN are complementary signals having an amplitude between the power supply voltage Vcc and the ground voltage Vss. IN is now from Vcc to Vss,
Consider a case where / IN transits from Vss to Vcc (time t1 to t2). At this time, since M3 is off and M4 is on, OUT falls from Vcc to Vss. Then, since M1 turns on, / OUT rises from Vss to Vcc, and M2 turns off. Therefore, the output OUT, / OUT
Are complementarily inverted. The same operation is performed when IN changes from Vss to Vcc and / IN changes from Vcc to Vss at times t3 to t4.

Here, in order for the logic gate to operate at a low voltage, it is necessary to lower the threshold voltage of the MOS transistor. When the threshold voltage is high, the drive current of the MOS transistor becomes small, which causes a decrease in switching speed, and when the power supply voltage becomes lower than the threshold voltage, the MOS transistor becomes
This is because the transistor does not work.

However, if the threshold voltage is lowered,
When the gate-source voltage is set to 0V, the cutoff characteristic becomes poor. That is, the subthreshold current of the MOS transistor increases and the standby current increases.
FIG. 34C shows the current Icc flowing through the power supply voltage when the complementary gate is operating. When the threshold voltage of the MOS transistor is low and the sub-threshold current is high, the current Isb remains at the standby time (time t0 to t1, t2 to t3) when the potential is fixed without transition of the input signal and the output signal. It will flow.

FIG. 35 shows a conventional example of an inverter circuit which is the simplest logic gate composed of nMOS transistors. The gate of the nMOS transistor M11 is connected to the power source terminal (Vcc), the bulk is connected to the power source E, and 0V or a negative voltage is applied to the ground terminal (Vss). M11 is a depletion type nMOS transistor, and the threshold voltage Vt when the voltage E is applied between the bulk and source is 0V, and Vt when the output OUT is Vo is VtL. nMOS transistor M
The input signal IN is applied to the gate of 12 and the bulk is connected to the power supply E.

The operation of this inverter will be described with reference to the timing chart of FIG. IN is Vc from time t0 to t1
When c, M12 is on. At this time, M11 is also in the ON state, but when the current driving capability of M12 is much larger than that of M11, the output OUT becomes approximately Vss and the standby current Isb 'flows. I from time t1 to t2
When N transitions from Vcc to Vss, M12 transitions to the off state and the output OUT is charged to a high level. At this time, M
If the gate width of 11 is too small, the load capacitance connected to OUT cannot be charged at high speed, so it is necessary to increase the gate width according to the load capacitance.

In the standby state from time t2 to t3, IN is Vss and M12 is off. M12
If the threshold voltage Vt of is sufficiently high, the leak current in the off state (subthreshold current) is sufficiently small, and OUT
Is charged to Vcc. However, when the power supply voltage Vcc becomes smaller due to the miniaturization, it is necessary to make Vt smaller than Vcc in order to obtain an operation margin of the circuit. For example, V
When cc is 0.5V, it is necessary to reduce VtH to about 0.1 to 0.2V. With such a low threshold voltage, the subthreshold current becomes as large as several tens nA to several hundreds nA, and the leak current in the off state cannot be ignored. as a result,
OUT is charged only up to Vo and does not reach Vcc. Further, the standby current Isb will flow. From time t3 to t4, IN changes from Vss to Vcc, and OUT becomes almost Vss.

In general, the power consumption P of a logic gate is P
= CVcc ² f. Here, C is the sum of the parasitic capacitance and the intrinsic capacitance of the MOS transistor forming the logic gate,
Vcc is a power supply voltage, and f is an operating frequency. Now, assuming that the operating frequency is constant, in order to suppress power consumption, the capacitance C
Or the power supply voltage Vcc may be reduced. In order to reduce C, it is effective to reduce the number of MOS transistors constituting the logic circuit or the gate width of the transistors. Further, since P is proportional to the square of Vcc, lowering Vcc is effective for lowering power consumption.

Recently, complicated logic has been applied to a relatively small number of elements,
Pass transistor logic has attracted attention as a logic gate realized with a simple configuration. FIG. 37 shows a 2-input logical product (AND) and negative logical product (NAND) gate configured by pass transistor logic. In this logic gate, two nMOS transistors M1 and M2 form an AND logic, and two nMOS transistors M3 and M4 form a NAND.
Constitutes the logic. Also, its output nodes N1 and N2
The signals Y and / Y appearing on the pMOS transistors M5 and M
7. A buffer circuit composed of nMOS transistors M6 and M8 amplifies. In addition, two pMOS transistors M for holding the high level of the output nodes N1 and N2
A high-level holding circuit composed of M9 and M10 is provided.

That is, the source of the nMOS transistor M1 is connected to the node N1, the signal XA is input to the drain, the signal XB is input to the gate, the source of the nMOS transistor M2 is connected to the node N2, and the drain is connected to the drain. The signal XB is input, and the gate is a complementary signal / X of the signal XB.
B is typing. Now, when the input / output signal is the ground potential Vss, it is defined as logic 0, and when it is the power supply voltage Vcc, it is defined as logic 1. When the input signal XB is logic 1, the nMOS transistor M1
Is on and the nMOS transistor M2 is off. As a result, the output node N1 has the same logic as the signal XA,
It becomes a logic 0 when XA is a logic 0, and becomes a logic 1 when XA is a logic 1. On the other hand, when the input signal XB is logic 0, nMO
S transistor M1 is non-conductive, nMOS transistor M
2 is conductive. As a result, the output node N1 receives the signal XB.
It becomes the same logic 0 as.

The source of the nMOS transistor M3 is connected to the node 2, the signal / XB is input to the drain, the signal / XB is input to the gate, and the source of the nMOS transistor M4 is connected to the node N2 and the drain thereof. Is inputted with the complementary signal / XA of the signal XA, and the gate is inputted with the signal XB. When the input signal XB is logic 1, n
MOS transistor M3 is non-conductive, and nMOS transistor M4 is conductive. As a result, output node N2 has a logic opposite to that of signal XA, and a logic 1 when XA is logic 0.
In addition, when XA is logic 1, it becomes logic 0. On the other hand, when the input signal XB is logic 0, the nMOS transistor M3 is conductive and the nMOS transistor M4 is non-conductive. As a result, the output node N1 becomes a logic 1 opposite to the signal XB.

By the way, the input signals of the signals Y and / Y are nM.
Since it passes through the OS transistors M1 to M4,
The driving capability is reduced due to the resistance of the transistor. Assuming that the threshold voltages of the nMOS transistors M1 to M4 are Vt, the logic 1 output from these transistors is lower than the power supply voltage by Vt. Therefore, when the pass transistor logic circuit of the next stage is driven by the signals Y and / Y, the driving capability of the output signal becomes further smaller, resulting in lower speed and malfunction. Therefore, the signal Y is the C composed of the pMOS transistor M5 and the nMOS transistor M6.
It is inverted and amplified by a MOS inverter, and the signal / Y is inverted and amplified by a CMOS inverter composed of a pMOS transistor M7 and an nMOS transistor M8. As a result, the AND output having the driving capability is output to the output OUT
, A NAND output having driving capability can be obtained.

However, the logic 1 of the nodes N1 and N2
Since the output is lower than the power supply voltage by Vt, the driving capability of the nMOS transistor M6 or M7 whose output is input to the gate is reduced, or the output of the NMOS transistor M6 or M7 is input to the gate.
The cut-off characteristics of the MOS transistor M5 or M7 deteriorate. As a result, the driving capability cannot be obtained as expected, or power consumption increases due to through current. Therefore,
The source is connected to the power supply voltage Vcc, and the gate is the node N2
Connected to the node and its drain connected to the node N1
A high level holding circuit composed of an S-transistor M9 and a pMOS transistor M10 having a source connected to Vcc, a gate connected to a node N1 and a drain connected to a node N2 is connected to the logic 1 side of the nodes N1 and N2. The potential is held at Vcc.

As described above, in the conventional gate circuit composed of pass transistor logic, in order to form a 2-input AND / NAND gate having driving capability, four n transistors are formed.
It was composed of a MOS transistor, a buffer circuit composed of two CMOS inverters, and a high level holding circuit composed of two pMOS transistors.

Here, the threshold voltage of the MOS transistor must be lowered in order for the logic gate to operate even when the power supply voltage Vcc is lowered to secure the reliability of the element and reduce the power consumption. This is because if the threshold voltage is high, the driving capability of the MOS transistor is reduced and the operation speed is reduced, and if the power supply voltage is lower than the threshold voltage, the MOS transistor does not operate. However, when the threshold voltage is lowered, the cutoff characteristics of the non-conductive transistor deteriorate. That is, the transistor having the logic 0 input to the gate does not become non-conductive, and the circuit may malfunction.

If the wiring capacitance is ignored, the node N1
Load capacitance of the nMOS transistor M6, the gate capacitance of the pMOS transistor M5, the pMOS
The sum of the drain junction capacitance of the transistor M9 and the gate capacitance of the pMOS transistor M10 results in the load capacitance of the node N2 being the gate capacitance of the nMOS transistor M8, p
The sum of the gate capacitance of the MOS transistor M7, the drain junction capacitance of the pMOS transistor M10, and the gate capacitance of the pMOS transistor M9 results in the nodes N1 and N2 having to drive a large capacitance. As a result, the nMOS transistors M1 to M that form the pass transistor logic.
4, and it is necessary to increase the gate width of the pMOS transistors M9 and M10 that form the high level holding circuit.

[0027]

As described above, in the conventional semiconductor integrated circuit using the fine MOS transistor, the threshold voltage is lowered in order to maintain the reliability of the element and to reduce the voltage, and to obtain the circuit operation margin. If the value is lowered, there is a problem that the current during standby increases and it becomes difficult to reduce power consumption, and there is a problem that the cutoff characteristic of the MOS transistor deteriorates and the circuit malfunctions.

Further, in the conventional pass transistor logic circuit, since the CMOS inverter is used as the buffer circuit, the output load of the pass transistor logic circuit becomes large, and the transistors constituting the pass transistor logic circuit and the high level holding circuit are constructed. It was necessary to increase the gate width of the transistor to be used. As a result, there has been a problem that the chip cost rises as the element area increases, and the power consumption increases as the capacity increases.

The present invention has been made in consideration of the above circumstances, and an object thereof is to reduce the standby current without impairing the circuit operation margin even when the power supply voltage is lowered. , To provide a semiconductor integrated circuit suitable for higher speed operation.

Another object of the present invention is to reduce the voltage with a sufficient operating margin without lowering the threshold voltage, and to reduce the output load of the pass transistor logic circuit without lowering the driving ability. An object of the present invention is to provide a semiconductor integrated circuit that can be manufactured.

[0031]

[Means for Solving the Problems]

(Outline) The essence of the present invention is to use a MOS transistor as an SOI.
(Silicon On Insulator) Each MO is formed on the substrate etc.
The purpose is to change the bulk potential of the S transistor according to the operating state. Further, according to the present invention, the substrate region of the MOS transistor forming the pass transistor logic circuit is controlled by the input signal given to the gate, and the output of the pass transistor logic circuit is received only by the nMOS transistor.
This is to amplify with a 2-line input buffer circuit that is latched by an OS transistor.

That is, according to the present invention (claim 1), the gates are commonly connected, and the pMOS transistor and the n-type transistor are connected between the power supply and the ground.
In a semiconductor integrated circuit having a circuit row in which n-stage (n ≧ 3) inverter circuits in which MOS transistors are connected in series are connected, each of the k-th stage (k ≧ 3) inverter circuits of the circuit row is formed. In the substrate region of the MOS transistor, k-2m (m = 1, 2, ...
It is characterized in that the input terminal of the (m ≦ k−1) th stage inverter circuit is connected.

According to a fifth aspect of the present invention, in a semiconductor integrated circuit including a MOS transistor, a source is connected to a power supply terminal, a gate is connected to a first output node, and a drain is connected to a second output node. A first pMOS transistor which is connected to the substrate region and receives a first signal; a source connected to the power supply terminal; a gate connected to a second output node; and a drain connected to the first output node A second pMOS transistor to which a second signal, which is a complementary signal of the first signal, is input to the substrate region, the source is connected to the ground terminal, the drain is connected to the second output node, and the gate and A first nMOS transistor to which a first signal is input to the substrate region, a source connected to the ground terminal, and a drain connected to a first output node,
The second n inputting the second signal to the gate and the substrate region
And a MOS transistor.

According to the present invention (claim 6), in a semiconductor integrated circuit comprising a MOS transistor, the source is connected to the power supply terminal, the gate and the substrate region are connected to the first output node, and the drain is the second. A first pMOS transistor connected to the output node, a second source connected to the power supply terminal, a gate and a substrate region connected to the second output node, and a drain connected to the first output node. a pMOS transistor, a first input circuit connected between the first output node and the ground terminal for receiving a plurality of signals, and a second input node connected between the ground terminal and the second output node; A second input circuit to which a complementary signal of the input signal of the first input circuit is input.

According to the present invention (claim 11), in a semiconductor integrated circuit comprising a MOS transistor, a drain and a gate are connected to a power supply terminal, and a source and a substrate region are first.
A first nMOS transistor connected to the node of
A drain and a gate are connected to the power supply terminal, a source is connected to the second node, and a substrate region is connected to the first node, and a second nMOS transistor is connected between the first node and the ground terminal. First connected and receiving multiple signals
An input circuit, and a second input circuit connected between the second node and the ground terminal, to which the plurality of signals are input,
It is characterized by comprising.

According to the present invention (claim 12), in a semiconductor integrated circuit comprising a MOS transistor, a drain and a gate are connected to a power supply terminal, a source is connected to a first node, and a substrate region is a second node. A first nMOS transistor connected to the node, a second nMOS transistor having a drain and a gate connected to the power supply terminal, a source connected to a second node, and a substrate region connected to the first node, A first input circuit connected between a first node and a ground terminal for receiving a plurality of signals, and a second input circuit connected between a second node and the ground terminal for receiving the plurality of signals. And a second input circuit according to the present invention.

According to a thirteenth aspect of the present invention, in a semiconductor integrated circuit including a MOS transistor, a resistance element connected between a power supply terminal and a first node, and a drain and a gate are connected to the power supply terminal. , The source is connected to the second node and the substrate region is connected to the first node nM
An OS transistor, a first input circuit connected between the first node and a ground terminal for receiving a plurality of signals, and a second node connected between the second node and the ground terminal. And a second input circuit to which a signal is input.

Further, according to the present invention, in a semiconductor integrated circuit forming a pass transistor logic circuit, at least one MOS transistor having a gate and a substrate region to which a first signal is inputted and a drain to which a second signal is inputted is provided. A logic circuit that outputs a third signal and a fourth signal that is a complementary signal to the third signal, a source connected to the power supply terminal, a gate connected to the first output node, and a drain connected to the second output node. The first p that is connected and receives the third signal in the substrate region
A second pMOS having a MOS transistor, a source connected to the power supply terminal, a gate connected to a second output node, a drain connected to a first output node, and a fourth signal input to the substrate region. A transistor and a source are connected to the ground terminal, a drain is connected to the second output node, and a third signal is input to the gate and the substrate region.
NMOS transistor, a source is connected to the ground terminal, a drain is connected to the first output node, and a fourth signal is input to the gate and the substrate region.
And a transistor. (Operation) According to the present invention, the MOS transistor is formed into the SOI.
By forming it on a substrate or the like, the bulk of the transistor (substrate region) is separated for each transistor. Also,
The threshold voltage of the transistor is controlled by applying a potential according to the operating state to each bulk.

According to the present invention (claims 1 to 4), when the MOS transistor in the k-th inverter circuit becomes conductive, the threshold voltage is lowered in advance to set the current driving capability to a high state. Therefore, the circuit operates at high speed. Further, since the threshold voltage can be raised at the time of cutoff, the standby current becomes small, and full amplitude operation becomes possible even when the power supply voltage is lowered. This makes it possible to realize a high-speed, low-current-consumption circuit without impairing the reliability of an ultrafine device having a gate length of 0.1 μm or less.

According to the present invention (claims 5 to 10), since the threshold voltage is lowered when the MOS transistor in the complementary logic gate is turned on, there is an effect that the current driving capability is increased. Further, since the threshold voltage rises when cut off, there is an effect that the standby current becomes small.
Therefore, it is possible to make the threshold voltage equal to or less than the absolute value when the power supply voltage is cut off, and the gate length is 0.1
Without damaging the reliability of ultra-fine devices of μm or less,
It is possible to realize a circuit with high speed and low current consumption.

According to the present invention (claims 11 to 20), when the output load capacitance is charged, the threshold voltage of the charging MOS transistor can be lowered, and high-speed operation becomes possible. At this time, since the threshold voltage of the discharge MOS transistor can be increased, the standby current can be reduced. Also, when discharging the output load capacitance, the discharge MOS
The threshold voltage of the transistor can be reduced and high speed operation can be achieved. At this time, since the threshold voltage of the charging MOS transistor can be increased, the standby current can be reduced.

According to the present invention (claims 21 and 22), the threshold voltage of the conduction transistor is lowered by controlling the substrate region of the MOS transistor forming the pass transistor logic circuit by the input signal applied to the gate. ,
The threshold of the non-conducting transistor increases. Further, the output capacitance of the pass-transistor logic circuit is reduced by receiving the output of the pass-transistor logic circuit only by the nMOS transistor and amplifying it by the 2-wire input buffer circuit latched by the pMOS transistor.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a diagram showing a buffer circuit according to a first embodiment of the present invention.

The pMOS transistor Mp1 and the nMOS transistor Mn1 form a first-stage inverter circuit I1. Similarly, Mp2 and Mn2 form a second-stage inverter circuit I2, and Mp3 and Mn3 form a third-stage inverter circuit.

The sources of Mp1 to Mp3 are connected to the power source terminal (Vcc), and the sources of Mn1 to Mn3 are connected to the ground terminal (Vss). The gates of Mp1 and Mn1 are commonly connected to the input terminal, and the drains are commonly connected to the node N1.
The gates of Mp2 and Mn2 are commonly connected to the node N1, and the drains are commonly connected to the node N2. The gates of Mp3 and Mn3 are commonly connected to the node N2, and the drains are commonly connected to the output terminal. In the figure, CL indicates the load capacity.

Although the basic structure up to this point is the same as that of the conventional example shown in FIG. 31, the inverter I is used in this embodiment.
The potential applied to the bulk of each MOS transistor 3 is changed. That is, each MOS transistor forming the buffer circuit is formed on the SOI substrate by using the known SOI technique, so that the bulk regions of each transistor are all separated. The input terminal of the inverter circuit I1 is connected to the n-type region which is the bulk of Mp3 and the p-type region which is the bulk of Mn3.

The power supply voltage Vcc is applied to the n-type region, which is the bulk of Mp1 and Mp2, as in the conventional case, and Mn1 and Mn2 are supplied.
In the p-type region, which is the bulk of the
Alternatively, a negative voltage is applied.

Next, the operation of this circuit will be described with reference to the operation waveforms of FIG. Mn1, Mn2, Mp1, Mp2, Vn1, Vn2
Since it is basically the same as the case of FIG. 32, detailed description thereof will be omitted.

Now, assume that the power supply voltage Vcc is 0.5V and the ground voltage Vss is 0V. Input voltage V from time t0 to t1
Since in is 0.5 V, Vout becomes "L" level. At this time, since a forward bias is applied between the bulk source of Mn3, the threshold voltage of Mn3 is lowered. The threshold voltage VtnL at this time is, for example, 0.1V. Also,
The bulk-source voltage of Mp3 is 0V, and the absolute value VtpH of the threshold voltage of Mp3 at this time is 0.5V, for example. In this case, Mn3 is conducting and Mp3 is completely cut off. Therefore, Iss3 hardly flows, and the output voltage Vout
Becomes 0V.

At this time, if the leak current (subthreshold current) flowing through the inverter I1 is Isb1, Iss
Since 1 = Isb1 and the subthreshold current is proportional to the gate width, Iss2 = 3.times.Isb1. In the past, the leakage current flowing through the inverter I3 was as large as Iss3 = 9 × Isb1, and thus it was not possible to cope with low power consumption.
When this embodiment is used, Mp3 is completely cut off, so that Iss3 becomes almost 0, and the standby current Isb flowing at this time can be reduced to 4/13 of the conventional case.

When Vin starts to decrease from time t1 to t2, a forward bias is applied between the bulk source of Mp3 and the absolute value of the threshold voltage becomes small. The absolute value VtpL of the threshold voltage at this time is, for example, 0.1V.
Further, since the bulk-source voltage of Mn3 approaches 0V, the threshold voltage increases. The threshold voltage VtnH at this time is set to 0.5 V, for example. In this case, Mn3 transits to the non-conducting state, and when Vn2 becomes 0.4 V or less, Mp3
Conducts. Therefore, Vout transits to "H" level.

From time t2 to t3, Vin is in a standby state and is constant at 0V. Vn2 becomes "L" level, and at this time, the absolute value of the threshold voltage of Mp3 is 0.1.
The absolute values of the threshold voltages of V and Mn3 are 0.5V. In this case, Mp3 is conducting and Mn3 is completely cut off.
Therefore, the standby current Isb flowing at this time is also Iss.
Only the sum of 1 and Iss2 can be reduced to 4/13 of the conventional one.

Vin is 0V to 0.5 at the time t3 to t4.
When it transits to V, the bulk-source voltage of Mp3 is 0V.
And the absolute value of the threshold voltage is 0.1V to 0.5V
Rise to Also, since a forward bias is applied between the bulk sources of Mn3, the threshold voltage is 0.5V to 0.1V.
Fall to. Therefore, when Vn2 transitions from 0V to 0.5V, Mp3 becomes non-conductive, and when Vn2 becomes 0.1V or more, Mn3 becomes conductive, so Vout becomes 0V.

As described above, in the present embodiment, by controlling the bulk voltage of Mn3 and Mp3 forming the third stage inverter, the threshold voltage is lowered in advance when Mn3 and Mp3 are turned on, and current driving is performed. Since the capacity can be set high, the third-stage inverter can be operated at high speed. Further, since the threshold voltage can be raised at the time of cutoff, the subthreshold currents of Mn3 and Mp3 become almost 0, and the standby current can be reduced to 4/13 of the conventional one. (Embodiment 2) FIG. 3 is a diagram showing a buffer circuit according to a second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The difference between this embodiment and the first embodiment described above is that the bulks of the MOS transistors of the inverters I1 and I2 are connected to their respective inputs. That is, the bulk of the MOS transistors Mp1 and Mn1 of I1 are connected to the input terminal, and the MOS transistors Mp2 and Mp of I2 are connected.
The bulk of n2 is connected to node N1.

With such a configuration, the threshold voltages of Mn1, Mn2, Mp1 and Mp2 also change according to the input voltage as shown in the operation timing chart of FIG. At this time, since Vn1 and Vn2 also operate at full amplitude, Mn
2, Mn3, Mp2, the gate-source voltage of the Mp3 is increased, the sum t _p of the delay times of the inverters I2, I3 is smaller than the conventional. Also, during standby, Iss1, I
Since ss2 hardly flows, the standby current becomes smaller. (Embodiment 3) FIG. 5 is a diagram showing a buffer circuit according to a third embodiment of the present invention. This buffer circuit
In this example, the inverter circuit has three or more stages.

When the buffer circuit is an inverter circuit array having three or more stages in this way, as shown in FIG.
The bulk of the MOS transistor forming the (≧ 3) th stage inverter I _k is converted into an inverter I _k-2m (m = 1, 2, ...,
However, it may be connected to the input terminal of 2m ≦ k−1). Also in this case, inverters other than the _k-th inverter I _k , for example, bulks of MOS transistors forming I _k-1 and I _k-2 may be connected to each input. (Embodiment 4) FIGS. 6A and 6B are circuit configuration diagrams showing a buffer circuit according to a fourth embodiment of the present invention.

The circuit of FIG. 6A is an example in which the NAND circuit 10 is connected to the input side of an inverter circuit array of three or more stages. Instead of the NAND circuit 10, another logic circuit such as a NOR circuit may be used. In addition, the circuit of FIG. 6B has a NAND on the output side of the inverter circuit array of three or more stages.
This is an example in which the circuit 20 is connected. Also in this case, as in the case of (a), another logic circuit such as a NOR circuit may be used instead of the NAND circuit 20.

Further, logic circuits may be connected to both the input side and the output side. Further, various circuits can be realized by combining these. (Fifth Embodiment) FIG. 7 is a circuit configuration diagram showing a complementary logic gate according to a fifth embodiment of the present invention.

M3 and M4 are nMOS transistors whose gates receive complementary signals IN and / IN, respectively, whose sources are commonly connected to the ground terminal (Vss) and whose drains are complementary signals OUT and /, respectively. OUT is output. M1 and M2 have their respective gates OUT and / OU
This is a pMOS transistor cross-connected to T, the sources are commonly connected to the power supply terminal (Vcc), and the drains are respectively connected to OUT and / OUT.

The basic structure up to this point is the same as that of the conventional example shown in FIG. 33, but in this embodiment, the potential applied to the bulk of each transistor is changed. That is, the MOS transistors M1 to M4 are S
It is formed on the OI substrate, and the bulk regions are all separated. The bulks of M1 and M3 are connected to the input end to which the signal IN is input, and M2 and M4 are connected to the input end to which the signal / IN is input.

The operation of the complementary logic gate of this embodiment will be described with reference to FIG. The input signals IN and / IN are complementary signals having an amplitude between the power supply voltage Vcc and the ground voltage Vss. The power supply voltage Vcc is 0.5V and the ground voltage Vss is 0V.

From time t0 to t1, IN is 0.5V,
Since / IN is 0V, it is nM due to the substrate bias effect.
The threshold voltage VtnL of the OS transistor M3 is nMOS.
It becomes lower than the absolute value VtnH of the threshold voltage of the transistor M4. Now, assuming that VtnL = 0.1V and VtnH = 0.5V, M3 is on and M4 is off, and the subthreshold current of M4 hardly flows.

On the other hand, the absolute value VtpH of the threshold voltage of the pMOS transistor M1 is larger than the absolute value VtpL of the threshold voltage of the pMOS transistor M2. Therefore, the subthreshold current of M1 hardly flows. As a result, almost no through current flows and Isb becomes small.

From time t1 to t2, IN and / IN transition, so that all the MOS transistors are turned on and Icc flows. From time t2 to t3, IN is 0V and / IN is 0.5V, so the absolute value of the threshold voltage of M1 is Vtp.
In H, the absolute value of the threshold voltage of M2 is VtpL, the threshold voltage of M3 is VtnL, and the threshold voltage of M4 is VtnH. Therefore, M1 is on, M2 is off, M3 is off, M
4 turns on, and the subthreshold currents of M2 and M3 decrease.

From time t3 to t4, IN and / IN transition, so that all the MOS transistors are turned on and Icc flows. As described above, according to the present embodiment, the MOSs that are turned on by connecting the bulks of M1 and M3 to the input terminal of IN and connecting the bulks of M2 and M4 to the input terminal of / IN.
The threshold voltage of the transistor can be lowered and the threshold voltage of the MOS transistor to be turned off can be raised. Then, the current driving capability can be enhanced by lowering the threshold voltage of the MOS transistor to be turned on, and the standby current can be reduced by raising the threshold voltage of the MOS transistor to be turned off. As a result, it becomes possible to realize a high-speed, low-current-consumption circuit. (Sixth Embodiment) FIG. 9 is a circuit configuration diagram showing an n-input complementary gate according to a sixth embodiment of the present invention.

The source of the first pMOS transistor M1 is connected to the power supply terminal (Vcc), the gate and bulk (substrate region) are connected to the first output node (OUT), and the source is the second output node (/ OUT). The source of the second pMOS transistor M2 is connected to Vcc, its gate and bulk are connected to the second output node, and its source is connected to the first output node. Then, between the first output node and Vss, a plurality of signals IN (1,2,
, N) is input, and the second input circuit 40, to which the complementary signal / IN of the input signal IN is input, is inserted between the second output node and Vss. Has been done.

In this way, the pMOS transistors M1,
The bulk potential of M2 is connected to each gate. When M1 is cut off, OUT is Vcc =
0.5V, / OUT is Vss = 0V. At this time, M
Since the bulk-source voltage Vbs of 1 is 0 V, the threshold voltage becomes -VtpH and the subthreshold current is small. On the other hand, the bulk-source voltage Vbs of M2 is −
Since it is 0.5V, the threshold voltage becomes -VtpL,
M2 turns on.

An example of the input circuits 30 and 40 is shown in FIG.
FIG. 10A shows a one-input circuit composed of one nMOS transistor M5. The bulk of M5 is connected to the input gate, and the threshold voltage at cutoff is V
The threshold voltage during ON is controlled to tnH and VtnL.

FIG. 10C shows an example in which two nMOS transistors M8 and M9 are connected in parallel to form a two-input OR circuit configuration. In this case as well, the bulk of M8 and M9 are connected to their respective gates, and the threshold voltage at cutoff is V
The threshold voltage during ON is controlled to tnH and VtnL.

The case of 1 input and 2 inputs is shown above, but 3
The threshold voltage can be controlled by connecting the bulks to the respective gates similarly in a multi-input OR circuit configuration of more than inputs or a circuit configuration in which these are combined. (Seventh Embodiment) FIG. 11 is a circuit configuration diagram showing a logic gate circuit according to a seventh embodiment of the present invention. The MOS transistor is formed on the SOI substrate by using a known SOI technique. Therefore, the bulk regions of each transistor are all separated.

The gate of the depletion type nMOS transistor M3 is connected to the power source terminal (Vcc), and the bulk is connected to the node A which is the source. Also, nM
The gate of the OS transistor M4 is connected to Vcc, and the bulk is connected to the node A. A plurality of signals IN are provided between the source (node A) of M3 and the ground terminal (Vss).
The first input circuit 50 to which (1,2, ..., n) is input is inserted, and similarly, the second input circuit 60 to which the signal IN is input is inserted between the source of M4 and Vss. ing.

The input circuits 50 and 60 are constructed as shown in FIG. FIG. 10A shows the case where n = 1, and the bulk of the MOS transistor M5 is connected to the gate. FIG. 10B shows two MOS transistors M
This is a case where 6 and M7 are connected in series to form a 2-input AND circuit configuration. The bulk of M6 is connected to the gate of M6, and the bulk of M7 is connected to the gate of M7. FIG.
0 (c) is a case where two MOS transistors M8 and M9 are connected in parallel to form a two-input OR circuit configuration.
The bulk of 8 is connected to the gate of M8, and the bulk of M9 is connected to the gate of M9. The input circuits of 50 and 60 have exactly the same configuration, but the gate widths of the transistors may be different.

When the input IN1 in FIG. 10 (a) is at high level, when both IN1 and IN2 in FIG. 10 (b) are at high level, and at least one of IN1 and IN2 in FIG. 10 (c) is At the high level, the logic gate of FIG. 11 operates exactly the same. In addition, the input IN of FIG.
When 1 is low level, and IN1 and IN in FIG. 10 (b)
When at least one of 2 is low level, and FIG.
When both IN1 and IN2 are low level, the logic gate of FIG. 11 operates exactly the same.

Next, referring to the timing chart of FIG.
The operation of the logic gate when the circuit 1 is used will be described.
The power supply voltage Vcc is 0.5V and the ground voltage Vss is 0V.
The input circuits 50 and 60 have the configuration shown in FIG.

Since IN is 0.5 V from time t0 to t1, a forward bias of 0.5 V is applied between the bulk and source of the MOS transistor M5 of the input circuit 50,
The threshold voltage becomes lower than when the bulk-source voltage is 0V. The threshold voltage at this time is 0V. The voltage between the bulk and source of the depletion type transistor M3 is always 0V, and the threshold voltage at this time is 0V.
V. If M5 is in the ON state and M3 is in the ON state at this time, but if the current driving capability of M5 is much larger than that of M3, the node A becomes approximately Vss.

Since the MOS transistor M5 of the input circuit 60 is also in the ON state, the output OUT becomes Vss. At this time, the bulk-source voltage of M4 is 0V as in M3.
And the threshold voltage at this time is Vcc. By doing so, M4 is completely cut off, and the subthreshold current hardly flows.

When IN changes from Vcc to Vss from time t1 to t2, the bulk-source voltage of M5 becomes 0V, and the threshold voltage rises to 0.5V. Therefore, M5 is completely cut off. At this time, node A
Is charged by M3 and the potential rises. Then,
The bulk-source voltage of M4 is forward biased, the threshold voltage of M4 is lowered, and M4 is turned on. Then, the output OUT is charged to almost Vcc.

In the standby state from time t2 to t3, M5 is completely cut off, so that no standby current flows. From time t3 to t4, IN changes from Vss to Vcc and M5 is turned on, so that a current flows and the node A and the output OUT become Vss.

In the logic gate of this embodiment, the depletion type transistor M3 is always turned on, and the gate width of M3 is made much smaller than M4 and M5, whereby the standby current can be reduced. It is not necessary to increase the gate width of M3 even if the load capacity increases.

10 (b) and 10 (c) show the case of two inputs, the present invention is also effective in a multi-input AND / OR circuit configuration of three or more inputs, or a circuit configuration combining these. Is. (Embodiments 8 and 9) FIG. 13 is a circuit configuration diagram showing an eighth embodiment of the present invention, and FIG. 14 is a circuit configuration diagram showing a ninth embodiment of the present invention.

The embodiment of FIG. 13 differs from the embodiment of FIG. 11 in that the bulk of the depletion type nMOS transistor M3 is connected to the output OUT. Even in this logic gate, the standby current can be reduced without lowering the operation margin.

The embodiment of FIG. 14 differs from the embodiment of FIG. 11 in that the depletion type nMOS transistor M3 is replaced with a resistor R1. Even in this logic gate, the standby current can be reduced without lowering the operation margin.

The present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention. For example, as a modification of the fifth embodiment, as shown in FIG.
A delay circuit 70 may be inserted between N, / IN and the substrate to shift the operation timings of the gate and the substrate potential. In this case, the inputs IN and / IN are delayed by the delay circuit 70 by the delay time τ and the MOS transistors M3 and M4 are delayed.
Respectively. As a result, the substrate potentials of the MOS transistors M1, M2, M3, M4 are controlled before the MOS transistor M3 or M4 operates.

As a modified example of the input circuit in the sixth to ninth embodiments shown in FIGS. 10A to 10C, as shown in FIGS. 16A to 16C, the input circuit is 1,
The delay circuit 70 may be inserted between the input of the nMOS transistor forming the circuit 2 and the substrate.

In FIG. 16A, the input IN1 is input to the MOS transistor M5 after a delay time τ by the delay circuit 70. This controls the substrate potential before M5 operates. In FIG. 16B, the inputs IN1 and IN2 are input to the MOS transistors M6 and M7 after being delayed by the delay circuit 70 by the delay time τ. As a result, the substrate potentials of M6 and M7 are controlled before M6 and M7 operate. In FIG. 16 (c), the inputs IN1 and IN2 are M by the delay circuit 70.
It is input to the OS transistors M8 and M9, respectively. As a result, the substrate potentials of M6 and M7 are controlled before M6 and M7 operate. (Embodiment 10) FIG. 17 is a circuit configuration diagram showing a pass transistor logic circuit and a buffer circuit according to a tenth embodiment of the present invention.

1 is 2n complementary signals IN1, / IN1,
, INn, / INn are input, two complementary signals Y,
It is a pass transistor logic circuit that outputs / Y. M
In 11, the source is connected to the power supply voltage Vcc, the gate is connected to the output terminal OUT, and the drain is the output terminal / OUT.
Is a pMOS transistor whose substrate region is connected to the output Y of the pass transistor logic circuit 1. M1
2 is pMO in which the source is connected to Vcc, the gate is connected to / OUT, the drain is connected to OUT, and the substrate region is connected to the output / Y of the pass transistor logic circuit 1.
It is an S transistor. The source of M13 is ground potential V
connected to ss, the gate and substrate area are connected to output Y,
An nMOS transistor whose drain is connected to / OUT. M14 is an nMOS transistor whose source is connected to Vss, whose gate and substrate region are connected to the output / Y, and whose drain is connected to OUT. Here, each of the transistors M11 to M14 is formed on the SOI substrate.

The circuit composed of the MOS transistors M11 to M14 is a two-line input buffer circuit which inputs the complementary output signals Y and / Y of the pass transistor logic circuit 1 and outputs the complementary signals OUT and / OUT.

The input capacitance of this 2-wire input buffer circuit is n.
The gate capacitance and the substrate capacitance of the MOS transistor M13 or M14 and the substrate capacitance of the pMOS transistor M11 or M12. However, since the MOS transistor formed on the SOI substrate has almost no source-drain junction capacitance, the substrate capacitance is almost zero. Therefore, the input capacitance of this 2-wire input buffer circuit is only the gate capacitance of the nMOS transistor M13 or M14. As described above, the output load capacitance of the pass transistor logic circuit 1 becomes smaller than that of the buffer circuit configured by the conventional CMOS inverter. Therefore, the pass transistor logic circuit 1
It is not necessary to increase the gate width of the transistor included in the device, and it is possible to contribute to the reduction of the element area and the power consumption.

18 to 29 are circuit configuration diagrams showing examples of the pass transistor logic circuit 1. FIG.
(A) is a 2-input logical product (AND). That is, nM
The signal XA is input to the drain of the OS transistor M15, the signal XB is input to the gate and substrate regions, the source is connected to the output Y, and the nMOS transistor M16.
The signal XB is input to the drain of the, the complementary signal / XB of the signal XB is input to the gate and the substrate region, and the source is connected to the output Y.

When the input signal XB is logic 1, the nMOS transistor M15 is conductive and the nMOS transistor M16.
Is non-conducting. As a result, the output Y has the same logic as the signal XA. When XA is logic 0, it is logic 0, and XA is logic 1.
When, it becomes logical 1. At this time, the MOS transistor M
Since the signal XB of logic 1 is input to the substrate region of 15, the threshold voltage of the MOS transistor M15 decreases. If the threshold voltage at this time is 0 V, logic 1
There is no threshold drop during output.

On the other hand, when the input signal XB is logic 0, nM
The OS transistor M15 is non-conductive, and the nMOS transistor M16 is conductive. As a result, the output node N1 becomes the same logic 0 as the signal XB. That is, in this AND circuit, when the input signals XA and XB are both logic 1, the output Y
Outputs a logic 1 without threshold drop, and outputs a logic 0 in other combinations.

FIG. 18B shows a 2-input NAND (NA).
ND). That is, the signal / XA is input to the drain of the nMOS transistor M17, the signal XB is input to the gate and substrate regions, the source is connected to the output / Y, and the signal / XA is input to the drain of the nMOS transistor M18.
XB is input, the signal / XB is input to the gate and the substrate region, and the source is connected to the output / Y. In this case as well, if the input signals XA and XB are both logical 1
At this time, the output Y is the logic 0, and the other combinations are the logic 1 without the threshold drop.

FIG. 19A shows a 2-input logical sum (OR). That is, the signal XA is input to the drain of the nMOS transistor M19, and the signal / A is input to the gate and the substrate region.
XB is input, source is connected to output Y, nMOS
The signal XB is input to the drain of the transistor M20, the signal XB is input to the gate and the substrate region, and the source is connected to the output Y. In this case as well, when the input signals XA and XB are both logic 0, a logic 0 is output as the output Y, and a logic 1 having no threshold drop is output in other combinations.

FIG. 19B shows a 2-input NOR operation (NO).
R). That is, the signal / XA is input to the drain of the nMOS transistor M21, the signal / XB is input to the gate and substrate regions, the source is connected to the output / Y, and the signal / XA is input to the drain of the nMOS transistor M22.
XB is input, the signal XB is input to the gate and substrate regions, and the source is connected to the output / Y. In this case as well, when the input signals XA and XB are both logic 0, the output Y outputs a logic 1 without threshold drop, and in other combinations, a logic 0 is output.

FIG. 20A shows a 2-input exclusive OR (E
XOR). That is, the signal XA is input to the drain of the nMOS transistor M23, the signal / XB is input to the gate and substrate regions, the source is connected to the output Y, and the signal / A is input to the drain of the nMOS transistor M24.
XA is input, the signal XB is input to the gate and substrate regions, and the source is connected to the output Y. In this case as well, when the input signals XA and XB are both logic 0 or logic 1, a logic 0 is output as the output Y, and a logic 1 without threshold drop is output in other combinations.

FIG. 20B shows a 2-input exclusive NOR (EXNOR). That is, the nMOS transistor M
The signal / XA is input to the drain of 25, the signal / XB is input to the gate and the substrate region, and the output is / Y to the source.
, The signal XA is input to the drain of the nMOS transistor M26, and the signal XA is input to the gate and the substrate region.
B is input and the source is connected to output / Y. In this case as well, when the input signals XA and XB are both logic 0 or logic 1, the output Y is logic 1 without threshold drop.
Is output, and logic 0 is output in other combinations.

FIG. 21A shows a 3-input AND. That is, the signal X is applied to the drain of the nMOS transistor M27.
C is input, the signal XA is input to the gate and substrate regions, the source is connected to the node N1, the drain of the nMOS transistor M28 is connected to the node N1, and the signal XB is input to the gate and substrate regions. Is connected to the output Y. In addition, the nMOS transistor M
The signal XA is input to the drain of 29, the signal / XA is input to the gate and the substrate region, the source is connected to the output Y, the signal XB is input to the drain of the nMOS transistor M30, and the signal is input to the gate and the substrate region. Is signal / XB
Is input, and the source is connected to the output Y.

In this case as well, the input signal X
When A, XB, and XC are all logic 1, the output Y outputs a logic 1 without threshold drop, and in other combinations, a logic 0 is output.

FIG. 21B shows a 3-input NAND.
That is, the signal / XC is input to the drain of the nMOS transistor M31, the signal XA is input to the gate and the substrate region, the source is connected to the node N2, and the drain of the nMOS transistor M32 is connected to the node N2. The signal XB is input to the substrate area and the source is connected to the output / Y. Further, the signal / XA is input to the drain of the nMOS transistor M33,
The signal / XA is input to the gate and substrate regions, the source is connected to the output / Y, the signal / XB is input to the drain of the nMOS transistor M34, and the signal / XB is input to the gate and substrate regions. Is connected to the output / Y.

In this case as well, the input signal X
When all of A, XB, and XC are logic 1, logic 0 is output as the output Y, and in other combinations, logic 1 without threshold drop is output.

FIG. 22A shows a 3-input OR. That is,
The signal XC is input to the drain of the nMOS transistor M35, the signal / XA is input to the gate and the substrate region, the source is connected to the node N3, the drain of the nMOS transistor M36 is connected to the node N3, and the gate and the substrate region. The signal / XB is input to and the source is connected to the output Y. In addition, the nMOS transistor M
The signal XA is input to the drain of 37, the signal XA is input to the gate and substrate regions, the source is connected to the output Y, the signal XB is input to the drain of the nMOS transistor M38, and the gate and substrate regions are input. The signal XB is input, and the source is connected to the output Y.

In this case as well, the input signal X
When all of A, XB, and XC are logic 0, a logic 0 is output as the output Y, and in other combinations, a logic 1 without threshold drop is output.

FIG. 22B shows a 3-input NOR. That is, a signal / is applied to the drain of the nMOS transistor M39.
XC is input, a signal / XA is input to the gate and the substrate region, the source is connected to the node N4, the drain of the nMOS transistor M40 is connected to the node N4,
The signal / XB is input to the gate and substrate regions, and the source is connected to the output / Y. Further, the signal / XA is input to the drain of the nMOS transistor M41, the signal XA is input to the gate and the substrate region, the source is connected to the output / Y, and the signal / XB is input to the drain of the nMOS transistor M42. , The signal XB is input to the gate and substrate regions, and the source is connected to the output / Y.

In this case as well, the input signal X
When A, XB, and XC are all logic 0, the output Y outputs a logic 1 without threshold drop, and in other combinations, a logic 0 is output.

FIG. 23 shows a 3-input EXOR / EXNOR. That is, the signal XB is input to the drain of the nMOS transistor M43, and the signal XB is input to the gate and the substrate region.
A is input, the source is connected to the node N5, and nMO
The signal / XB is input to the drain of the S transistor M44, and the signal / XA is input to the gate and the substrate region.
The source is connected to the node N5. Furthermore, nMO
The signal XB is input to the drain of the S-transistor M45, the signal / XA is input to the gate and the substrate region, the source is connected to the node N6, and the nMOS transistor M45 is connected.
The signal / XB is input to the drain of 46, the signal XA is input to the gate and the substrate region, and the source is the node N6.
It is connected to the.

Further, the drain of the nMOS transistor M47 is connected to the node N5, the signal / XC is input to the gate and the substrate region, the source is connected to the output Y, and n
The drain of the MOS transistor M48 is connected to the node N5, and the signal XC is input to its gate and substrate region.
The source is connected to the output Y. Further, the drain of the nMOS transistor M49 is connected to the node N6,
The signal XC is input to the gate and substrate regions, the source is connected to the output / Y, the drain of the nMOS transistor M50 is connected to the node N6, the signal / XC is input to the gate and substrate regions, and the source is output / Y. Connected to Y.

In this case as well, the input signal X
When all of A, XB, and XC are logic 0 or logic 1, the output Y is a logic 1 without a threshold drop, the output / Y is a logic 0, and in other combinations, the output Y is a logic 0. Is output, and the output / Y is a logic 1 without a threshold drop. This output is also the sum signal SU of the full adder.
It is also M and / SUM.

FIG. 24A shows a carry signal C0 generating circuit of the full adder. That is, the nMOS transistor M5
The signal / XA is input to the drain of 1, the signal XB is input to the gate and the substrate region, the source is connected to the node N7, and the signal / XC is input to the drain of the nMOS transistor M52. Signal to
XB is input, the source is connected to the node N7, and nM
The signal / XA is input to the drain of the OS transistor M53, the signal / XB is input to the gate and the substrate region, the source is connected to the node N8, and the signal / XC is input to the drain of the nMOS transistor M54. The signal XB is input to the substrate area and the source is connected to the node N8.

Further, the drain of the nMOS transistor M55 is connected to the node N7, the signal XA is input to the gate and the substrate region, and the source is connected to the output C0.
The drain of the nMOS transistor M56 is connected to the node N8, the signal / XA is input to the gate and the substrate region, and the source is connected to the output C0.

In this case as well, the input signal X
When at least two of A, XB, and XC are both logic 1, the output C0 is logic 1 without threshold drop,
Logic 0 is output in other combinations.

FIG. 24B shows a complementary signal / of the carry signal.
This is a C0 generating circuit. That is, the nMOS transistor M5
The signal XA is input to the drain of 7, the signal XB is input to the gate and the substrate region, the source is connected to the node N9, the signal XC is input to the drain of the nMOS transistor M58, and the gate and the substrate region are input. Signal / XB
Is input, the source is connected to the node N9, and the nMOS
The signal XA is input to the drain of the transistor M59, the signal / XB is input to the gate and the substrate region, the source is connected to the node N10, and the signal XC is input to the drain of the nMOS transistor M60. The signal XB is input to the source of the node N1
Connected to 0.

Further, the drain of the nMOS transistor M61 is connected to the node N9, the signal XA is input to the gate and the substrate region, the source is connected to the output / C0, and the drain of the nMOS transistor M62 is connected to the node N9.
10, the signal / XA is input to the gate and substrate regions, and the source is connected to the output / C0.

In this case as well, the input signal X
When at least two of A, XB, and XC are both logic 1, a logic 0 is output as the output / C0, and other combinations output a logic 1 without threshold drop.

FIG. 25A shows another example of the 2-input AND. That is, the signal XA is input to the source of the pMOS transistor M63, and the signal / X is input to the gate and the substrate region.
B is input, drain is connected to output Y, and nMOS
The drain of the transistor M64 is connected to the output Y, the signal / XB is input to the gate and the substrate region, and the source is connected to the ground potential Vss. Further, the signal XB is input to the source of the pMOS transistor M65, the signal / XA is input to the gate and the substrate region, the drain is connected to the output Y, the drain of the nMOS transistor M66 is connected to the output Y, and the gate and The signal / XA is input to the substrate region, and the source is connected to the ground potential Vss.

When the input signals XA and XB are both logic 0,
pMOS transistors M63 and M65 are both non-conductive, and n
Both MOS transistors M64 and M66 are conductive.
As a result, the output Y is a logic 0. Input signal XA
Is a logic 1 and XB is a logic 0, the nMOS transistor M64 and the pMOS transistor M65 are conductive and the pMOS transistor M65 is conductive.
The transistor M63 and the nMOS transistor M66 are non-conductive. As a result, the output Y is a logic 0.

When the input signal XA is logic 0 and XB is logic 1, the nMOS transistor M64 and pMOS transistor M65 are non-conductive, and the pMOS transistors M63 and nM.
The OS transistor M66 is conductive. As a result, the output Y is a logic 0. When the input signals XA and XB are both logic 1, the pMOS transistors M63 and M65 are both conductive, and the nMOS transistors M64 and M66 are both non-conductive. As a result, a logical 1 is output as the output Y.
That is, in this AND circuit, the input signals XA and XB are
Are both logic 1, a logic 1 is output as the output Y, and a logic 0 is output in other combinations.

FIG. 25B shows another example of a 2-input NAND. That is, the source of the pMOS transistor M67 is connected to the power supply voltage Vcc, the signal XB is input to the gate and the substrate region, the drain is connected to the output / Y, and nM
The drain of the OS transistor M68 is connected to the output / Y, the signal XB is input to the gate and the substrate region, and the signal / XA is input to the source. And pMOS
The source of the transistor M69 is connected to Vcc, the signal XA is input to the gate and the substrate region, the drain is connected to the output / Y, the drain of the nMOS transistor M70 is connected to the output / Y, and the gate and the substrate region are connected. The signal XA is input and the signal / XB is input to the source.

In this case as well, the input signal X
When both A and XB are logic 1, logic 0 is output as the output Y, and logic 1 is output in other combinations. FIG. 26A shows another example of the 2-input OR. That is, pM
The source of the OS transistor M71 is connected to the power supply voltage Vcc, the signal / XB is input to the gate and the substrate region,
The drain is connected to the output Y, and the nMOS transistor M
The drain of 72 is connected to the output Y, the signal / XB is input to the gate and the substrate region, and the signal XA is input to the source. The source of the pMOS transistor M73 is connected to Vcc, the signal / XA is input to the gate and substrate regions, the drain is connected to the output Y, and nM
The drain of the OS transistor M74 is connected to the output Y, the signal / XA is input to the gate and the substrate region, and the signal XB is input to the source.

In this case as well, the input signal X
When both A and XB are logic 0, a logic 0 is output as the output Y, and in other combinations, a logic 1 is output. FIG. 26B is another example of the 2-input NOR. That is, p
The signal / XA is input to the source of the MOS transistor M75, and the signal XB is input to the gate and the substrate region.
The drain is connected to the output / Y, the drain of the nMOS transistor M76 is connected to the output / Y, the signal XB is input to the gate and the substrate region, and the source is the ground potential Vss.
It is connected to the. In addition, pMOS transistor M7
The signal / XB is input to the source of 7, the signal XA is input to the gate and the substrate region, the drain is connected to the output / Y, the drain of the nMOS transistor M78 is connected to the output / Y, and the gate and the substrate region. A signal XA is input to the input terminal of the source and the source is connected to the ground potential Vss.

In this case as well, the input signal X
When both A and XB are logic 0, a logic 1 is output as the output Y, and logic 0 is output in other combinations. FIG. 27A shows another example of the 2-input EXOR. That is,
The signal XA is input to the source of the pMOS transistor M79, the signal XB is input to the gate and substrate regions,
The drain is connected to the output Y, and the nMOS transistor M
The signal / XB is input to the drain of 80, the signal XA is input to the gate and substrate regions, and the source is connected to the output Y. Then, the signal / XA is input to the source of the pMOS transistor M81, the signal / XB is input to the gate and the substrate region, the drain is connected to the output Y, and the signal X is input to the drain of the nMOS transistor M82.
B is input, the signal / XA is input to the gate and the substrate region, and the source is connected to the output Y.

In this case as well, the input signal X
When both A and XB are logic 0 or logic 1, output Y is logic 0
Is output, and logic 1 is output in other combinations. FIG. 27B is another example of the 2-input EXNOR. That is, the signal / XB is input to the source of the pMOS transistor M83, and the signal XA is input to the gate and the substrate region.
Is input, the drain is connected to the output / Y, and nMOS
The signal XA is input to the drain of the transistor M84, the signal XB is input to the gate and the substrate region, and the source is connected to the output / Y. Further, the signal XB is input to the source of the pMOS transistor M85, the signal / XA is input to the gate and substrate regions, the drain is connected to the output / Y, and the signal / XA is input to the drain of the nMOS transistor M86. , The signal / XB is input to the gate and substrate regions, and the source is connected to the output Y.

In this case as well, the input signal X
When both A and XB are logic 0 or logic 1, output Y is logic 1
Is output, and logic 0 is output in other combinations. FIG. 28 shows another example of the 3-input EXOR / EXNOR. Reference numeral 2 denotes the 2-input EXOR shown in FIG. 27A, which receives the signals XA and XB and whose output appears at the node N11. Reference numeral 3 denotes the 2-input EXNOR shown in FIG. 27B, which receives the signals XA and XB and whose output appears at the node N12.

The drain of the nMOS transistor M87 is connected to the node N11, the signal / XC is input to the gate and substrate regions, the source is connected to the output Y, and the pMO
The source of the S transistor M88 is connected to the node N11, the signal XC is input to the gate and the substrate region, and the drain is connected to the output Y. Further, the drain of the nMOS transistor M89 is connected to the node N11,
The signal XC is input to the gate and substrate regions, the source is connected to the output / Y, the source of the pMOS transistor M90 is connected to the node N11, the signal / XC is input to the gate and substrate regions, and the drain is the output / Y. Connected to Y.

The drain of the nMOS transistor M91 is connected to the node N12, the signal XC is input to the gate and the substrate region, the source is connected to the output Y, and p
The source of the MOS transistor M92 is connected to the node N12, the signal / XC is input to the gate and the substrate region, and the drain is connected to the output Y. Furthermore, nM
The drain of the OS transistor M93 is connected to the node N12, the signal / XC is input to the gate and the substrate region, the source is connected to the output / Y, the source of the pMOS transistor M94 is connected to the node N12, and the gate and the substrate region. The signal XC is input to the
Connected to Y.

In this case as well, the input signal X
When all of A, XB, and XC are logic 0 or logic 1, the output Y outputs the logic 1, the output / Y outputs the logic 0, and in other combinations, the output Y outputs the logic 0 and the output / A logical 1 is output for Y. This output is also the sum signal SUM, / SUM of the full adder.

FIG. 29 shows a carry signal C0 and its complementary signal / C0 generating circuit. Reference numeral 4 denotes the two-input AND shown in FIG. 25A, which receives the signals XA and XB and whose output appears at the node N13. 5 is the 2-input N shown in FIG.
It is AND, inputs signals XA and XB, and outputs appear at node N14. 6 is the 2-input OR shown in FIG.
And the signals XA and XB are input, and the output is the node N15.
Appears in Reference numeral 7 denotes the 2-input NOR shown in FIG. 26B, which receives the signals XA and XB and whose output appears at the node N16.

The drain of the nMOS transistor M95 is connected to the node N13, the signal / XC is input to the gate and the substrate region, the source is connected to the output C0, and the pM
The source of the OS transistor M96 is connected to the node N13, the signal XC is input to the gate and the substrate region, and the drain is connected to the output C0. The drain of the nMOS transistor M97 is connected to the node N14, the signal XC is input to the gate and substrate regions, the source is connected to the output / C0, the source of the pMOS transistor M98 is connected to the node N14, and the gate and substrate regions are connected. Signal / XC is input, and the drain is connected to the output / C0.

The drain of the nMOS transistor M99 is connected to the node N15, the signal XC is input to the gate and the substrate region, the source is connected to the output C0, and the pMO
The source of the S transistor M100 is connected to the node N15, and the signal / XC is input to the gate and the substrate region,
The drain is connected to the output C0. The drain of the nMOS transistor M101 is connected to the node N16,
The signal / XC is input to the gate and substrate regions, the source is connected to the output / C0, and the pMOS transistor M10
The source of 2 is connected to the node N16, the signal XC is input to the gate and the substrate region, and the drain is connected to the output / C0.

In this case as well, the input signal X
When at least two of A, XB, and XC are both logic 1, the output C0 is the logic 1 and the output / C0 is the logic 0.
Is output, and in other combinations, a logical 0 is output as the output C0 and a logical 1 is output as the output / C0.

As described above, in this embodiment, by controlling the substrate region of the MOS transistor forming the pass transistor logic circuit 1 by the input signal applied to the gate, the threshold voltage of the conductive transistor is lowered and the non-conductive transistor is reduced. Threshold rises. Further, the output of the pass transistor logic circuit 1 is connected to the nMOS transistor M1.
3, M14 only, and pMOS transistor M11,
The output capacitance of the pass-transistor logic circuit 1 is reduced by the amplification by the 2-wire input buffer circuit 2 latched by M12.

Therefore, it is possible to realize the pass transistor logic circuit 1 capable of lowering the voltage with a sufficient operation margin without lowering the threshold voltage of the MOS transistor. Moreover, since the output load of the pass transistor logic circuit 1 can be reduced, a sufficient driving capability can be provided, and as a result, it is possible to contribute to the reduction of the element area and the power consumption.

In the above description, the 2-transistor 3-input gate is shown as the pass transistor logic circuit 1, but it is easy to extend this to n inputs (n is a natural number of 5 or more). Further, various pass transistor logic circuits can be made by combining these. (Embodiment 11) FIG. 30 is a circuit diagram showing a pass transistor logic circuit and a buffer circuit according to an eleventh embodiment of the present invention. The difference from the tenth embodiment described above is that pMOS transistors M103 and M104 that form a high level holding circuit are added.

In this case, even if the threshold voltage of the MOS transistor forming the pass transistor logic circuit 1 becomes high and the output of the logic 1 drops by the threshold value, the high level can be sufficiently maintained, and the deterioration of the driving capability can be prevented. be able to.

[0135]

As described in detail above, according to the present invention, M
An OS transistor is formed on, for example, an SOI substrate,
By changing the bulk potential of each MOS transistor according to the operating state, the standby current can be reduced without impairing the circuit operation margin even when the power supply voltage is lowered, and a semiconductor suitable for higher speed operation It becomes possible to realize an integrated circuit.

Further, according to the present invention, it is possible to provide a pass transistor logic circuit having a sufficient operation margin without lowering the threshold voltage even if the voltage is lowered. Further, since the input capacitance of the buffer circuit can be reduced, the load capacitance of the pass transistor logic circuit is reduced. As a result, the gate width of the transistors forming the pass transistor logic circuit can be reduced and the element area can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a buffer circuit according to a first embodiment.

FIG. 2 is an operation waveform diagram for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit configuration diagram showing a buffer circuit according to a second embodiment.

FIG. 4 is an operation waveform diagram for explaining the operation of the circuit of FIG.

FIG. 5 is a circuit configuration diagram showing a buffer circuit according to a third embodiment.

FIG. 6 is a circuit configuration diagram showing a buffer circuit according to a fourth embodiment.

FIG. 7 is a circuit configuration diagram showing a complementary logic gate according to a fifth embodiment.

8 is an operation waveform diagram for explaining the operation of the circuit of FIG.

FIG. 9 is a circuit configuration diagram showing an n-input complementary gate according to a sixth embodiment.

FIG. 10 is a circuit configuration diagram showing an example of an input circuit.

FIG. 11 is a circuit configuration diagram showing a logic gate circuit according to a seventh embodiment.

12 is an operation waveform chart for explaining the operation of the circuit of FIG.

FIG. 13 is a circuit configuration diagram showing an eighth embodiment.

FIG. 14 is a circuit configuration diagram showing a ninth embodiment.

FIG. 15 is a circuit configuration diagram showing a modified example of the fifth embodiment.

FIG. 16 is a circuit configuration diagram showing a modification of the sixth to ninth embodiments.

FIG. 17 is a circuit configuration diagram showing a pass transistor logic circuit and a buffer circuit according to the tenth embodiment.

FIG. 18: 2-input AND / by pass transistor logic
FIG. 3 is a circuit configuration diagram showing an example of NAND.

FIG. 19 is a 2-input OR / N based on pass transistor logic.
The circuit block diagram which shows the example of OR.

FIG. 20: 2-input EXOR by pass transistor logic
FIG. 6 is a circuit configuration diagram showing an example of / EXNOR.

FIG. 21: 3-input AND / by pass transistor logic
FIG. 3 is a circuit configuration diagram showing an example of NAND.

FIG. 22: 3-input OR / NO by pass transistor logic
The circuit block diagram which shows the example of R.

FIG. 23: 3-input EXOR by pass transistor logic
FIG. 6 is a circuit configuration diagram showing an example of / EXNOR.

FIG. 24 is a circuit configuration diagram showing a carry signal generation circuit of a full adder configured by pass transistor logic.

FIG. 25 is a circuit configuration diagram showing another example of a 2-input AND / NAND.

FIG. 26 is a circuit configuration diagram showing another example of 2-input OR / NOR.

FIG. 27 is a circuit configuration diagram showing another example of the 2-input EXOR / EXNOR.

FIG. 28 is a circuit configuration diagram showing another example of the 3-input EXOR / EXNOR.

FIG. 29 is a circuit configuration diagram showing another example of the carry signal generation circuit of the full adder.

FIG. 30 is a circuit configuration diagram showing a pass transistor logic circuit and a buffer circuit according to the eleventh embodiment.

FIG. 31 is a diagram showing a conventional example of a buffer circuit including three stages of inverter circuits.

32 is an operation waveform chart for explaining the operation of the buffer circuit in FIG. 31.

FIG. 33 is a diagram showing a conventional example of a complementary logic gate using a MOS transistor.

FIG. 34 is an operation waveform chart for explaining the operation of the circuit of FIG. 33.

FIG. 35 is a diagram showing a conventional example of an inverter circuit composed of nMOS transistors.

36 is an operation waveform chart for explaining the operation of the circuit of FIG. 35.

FIG. 37 is a 2-input A based on the conventional pass transistor logic.
FIG. 6 is a circuit configuration diagram showing an ND / NAND gate.

[Explanation of symbols]

 Mp1, Mp2, Mp3, M1, M2 ... pMOS transistors Mn1, Mn2, Mn3, M3, M4 ... nMOS transistors I1, I2, I3 ... Inverter circuits N1, N2, A ... Nodes 30, 50 ... First input circuit 40, 60 ... Second input circuit 70 ... Delay circuit 1 ... Pass transistor logic circuit 2 ... 2-input EXOR gate 3 ... 2-input EXNOR gate 4 ... 2-input AND gate 5 ... 2-input NAND gate 6 ... 2-input OR gate 7 ... 2 Input NOR gates N1 to N16 ... Nodes M1 to M104 ... MOS transistors

Claims (22)

[Claims] 1. A gate is commonly connected, and p is provided between a power supply and ground.
In a semiconductor integrated circuit having a circuit row in which an MOS transistor and an nMOS transistor are connected in series and connected in n stages (n ≧ 3), a k-th inverter circuit (k ≧ 3) in the circuit row is provided. An input terminal of a k−2m (m = 1, 2, ..., 2m ≦ k−1) stage inverter circuit of the circuit array is connected to the substrate region of each MOS transistor to be formed. Integrated semiconductor circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the plurality of nMOS transistors and pMOS transistors of the circuit array are formed on a silicon substrate on an insulating film. 3. The semiconductor integrated circuit according to claim 1, wherein each of the substrate regions of the plurality of nMOS transistors and pMOS transistors in the circuit array is electrically isolated. 4. Each inverter circuit other than the k-th inverter circuit in the circuit array is characterized in that an input terminal of the inverter circuit composed of the MOS transistor is connected to a substrate region of each MOS transistor. The semiconductor integrated circuit according to claim 1. 5. The source is connected to the power supply terminal, and the gate is first.
A first pMOS transistor having a drain connected to a second output node, a first signal input to a substrate region, a source connected to the power supply terminal, and a gate connected to a second gate. A second pMOS transistor connected to the output node, a drain connected to the first output node, and a second signal which is a complementary signal of the first signal input to the substrate region, and a source connected to the ground terminal A first nMOS transistor having a drain connected to the second output node, a first signal input to the gate and the substrate region, a source connected to the ground terminal, and a drain connected to the first output node. And a second nMOS transistor connected to the gate and the substrate region to which the second signal is input, and the semiconductor integrated circuit. 6. The source is connected to the power supply terminal, and the gate is the first
A first pMOS transistor having a drain connected to a second output node, a first signal input to a substrate region, a source connected to the power supply terminal, and a gate connected to a second gate. A second pMOS transistor connected to the output node, a drain connected to the first output node, and a second signal, which is a complementary signal of the first signal, input to the substrate region, and the first signal input A first delay circuit that outputs a third signal, a second delay circuit that receives the second signal and outputs a fourth signal, a source connected to the ground terminal, and a drain connected to the second A first nMOS transistor connected to the output node of the second gate, a third signal input to the gate, and a first signal input to the substrate region, and a source connected to the ground terminal and a second output connected to the drain. Connected to the node, Fourth signal is input to the bets, the semiconductor integrated circuit characterized by being provided with a second nMOS transistor having a second signal is inputted to the substrate region. 7. The source is connected to the power supply terminal, the gate and the substrate region are connected to the first output node, and the drain is the second.
A first pMOS transistor connected to the output node, a source connected to the power supply terminal, a gate and a substrate region connected to the second output node, and a drain connected to the first output node. Of the pMOS transistor, a first input circuit connected between the first output node and the ground terminal and receiving one or more signals, and a second output node between the ground terminal and Connected, first
A second input circuit to which a complementary signal of the input signal of the input circuit is input, and a semiconductor integrated circuit. 8. The semiconductor integrated circuit according to claim 5, wherein each of the MOS transistors is formed on a silicon substrate on an insulating film. 9. The substrate regions of the respective MOS transistors are all electrically isolated.
7. The semiconductor integrated circuit according to any one of 7. 10. The first and second input circuits are configured by one nMOS transistor whose substrate region is connected to a gate or a plurality of nMOS transistors connected in parallel. Semiconductor integrated circuit. 11. The first and second input circuits are each composed of one nMOS transistor in which a delay circuit is connected between a gate and a substrate region or a plurality of nMOS transistors connected in parallel. The semiconductor integrated circuit according to claim 7. 12. The semiconductor integrated circuit according to claim 10, wherein the substrate regions of the MOS transistors of the first and second input circuits are all electrically isolated. 13. A drain and a gate are connected to a power source end,
The first n with the source and substrate region connected to the first node
A MOS transistor, a second nMOS transistor having a drain and a gate connected to the power supply terminal, a source connected to a second node, and a substrate region connected to the first node; a first node and a ground terminal; And a first input circuit connected between the second node and the ground terminal, the first input circuit being connected between the first input circuit and the second input terminal, and receiving the one or more signals. And a second input circuit. 14. A drain and a gate are connected to a power supply end,
A first nMOS transistor having a source connected to the first node and a substrate region connected to the second node; a drain and a gate connected to the power supply terminal; a source connected to the second node; A second nMOS transistor whose region is connected to the first node; a first input circuit which is connected between the first node and the ground terminal and receives one or more signals; A second input circuit that is connected between the node and the ground terminal and receives the one or more signals. 15. A resistance element connected between a power supply terminal and a first node, a drain and a gate are connected to the power supply terminal, a source is connected to a second node, and a substrate region is a first node. An nMOS transistor connected to the first node, a first input circuit connected between the first node and the ground terminal and receiving one or more signals, and a second node between the ground node and the ground terminal. And a second input circuit connected to the input terminal to which the one or more signals are input, and a semiconductor integrated circuit. 16. The first and second input circuits are constituted by one nMOS transistor whose substrate region is connected to a gate or a plurality of nMOS transistors connected in series. 16. The semiconductor integrated circuit according to any one of 15. 17. The first and second input circuits are each composed of one nMOS transistor having a delay circuit connected between the gate and the substrate region or a plurality of nMOS transistors connected in series. Claims 13 to 15
The semiconductor integrated circuit according to any one of 1. 18. The first and second input circuits are constituted by one nMOS transistor whose substrate region is connected to a gate or a plurality of nMOS transistors connected in parallel. 16. The semiconductor integrated circuit according to any one of 15. 19. The first and second input circuits are each composed of one nMOS transistor in which a delay circuit is connected between a gate and a substrate region or a plurality of nMOS transistors connected in parallel. Claims 13 to 15
The semiconductor integrated circuit according to any one of 1. 20. The semiconductor integrated circuit according to claim 13, wherein each of the MOS transistors is formed on a silicon substrate on an insulating film. 21. A fourth signal which is at least one MOS transistor having a gate and a substrate region to which a first signal is input and a drain to which a second signal is input, and which is a third signal and its complementary signal. A logic circuit that outputs a, a source connected to a power supply terminal, a gate connected to a first output node, and a drain connected to a second output node,
A first pMOS transistor to which a third signal is input to the substrate region, a source connected to the power supply terminal, a gate connected to the second output node, and a drain connected to the first output node, Second pMOS in which the fourth signal is input to the region
A transistor, a source connected to the ground terminal, a drain connected to the second output node, a gate and a first nMOS transistor to which a third signal is input to the substrate region, and a source connected to the ground terminal. A second nMOS transistor having a drain connected to the first output node and having a gate and a substrate region to which a fourth signal is input, the semiconductor integrated circuit. 22. A third pMOS transistor having a source connected to the power supply terminal, a gate and a substrate region connected to a second output node, and a drain supplied with a third signal, and a source connected to the power supply terminal. 22. A fourth pMOS transistor having a gate and a substrate region connected to the first output node and having a drain to which a fourth signal is input. Semiconductor integrated circuit.