JPH09311743A - Bus driver circuit and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the output delay time and to reduce the output signal distortion in a high speed bus driver. SOLUTION: A current boost circuit is controlled by a voltage control system using the value of signal voltage Va inputted to the gate of the transistor Q1 of an open drain-type output circuit, and the current boost performance of the current boost circuit is variably set in accordance with the value of Va. Since the current boost performance of the current boost circuit can gradually be deteriorated by adjusting it to the drop of Va, the fall inclination of Va can be made sharp by large current boost performance immediately after the fall of Va, and the inclination of fall can be made smooth as the value of Va becomes low. Thus, output delay time can be shortened and output signal distortion can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus driver circuit and a control method thereof, and more particularly to a bus driver circuit and a control method thereof for driving a bus in which a plurality of devices are connected to the same transmission path at high speed.

[0002]

2. Description of the Related Art In recent years, advances in semiconductor technology and system architecture have been made in the field of computers, and accordingly, high-speed bus transfer is required. Due to this, recently, the clock frequency of the bus is also increased, and for example, the clock frequency of the bus connecting the microprocessor and the memory, or a plurality of microprocessors is about 66 to 100 MHz.

Conventionally, a TTL-structured bus interface has been adopted for each device connected to the bus. However, it becomes difficult for such a TTL-structured bus interface to sufficiently support a high-speed bus. There is. Therefore, recently, a new high-speed bus interface has been actively developed in order to cope with an increase in bus speed.

GT is one of the high-speed bus interfaces.
L (Gunning Transceiver Logi)
c) is known. The GTL is a small-amplitude interface composed of an open drain type buffer circuit using CMOS devices used in a large-scale ASIC.

The open drain type buffer circuit is a circuit that has been widely used as a hot-pluggable bus interface, but the GTL is a circuit for further increasing the operating speed of the open drain type buffer circuit. Is added. FIG. 5 shows the configuration of the open drain type buffer circuit, and FIG. 7 shows the configuration of the GTL circuit.

As shown in FIG. 5, in the open drain type buffer circuit, the drain of an N channel MOS transistor Q1 is connected to a bus transmission line, and the transistor Q1 is connected to a P channel MOS transistor Q11 and an N channel MOS transistor. The configuration is such that the operation is controlled by the CMOS inverter composed of Q12.
Output signal Vou of this open drain type buffer circuit
The high-side voltage of t is held by the external termination resistor Rt.

Note that Vtt is a power supply voltage supplied to the terminating resistor Rt, and is usually a value lower than the internal power supply voltage Vcc (5 V or 3.3 V), for example, 1.2 V.
The voltage value of this Vtt becomes the voltage value on the high side of the output signal Vout.

The output characteristics of the open drain type buffer circuit are shown in FIG. This output characteristic is that the output signal Vout changes from Low to high due to the turn-off of the transistor Q1.
It is when you stand up to h. In the figure, Vref is the circuit threshold voltage of the output circuit composed of the N-channel MOS transistor Q1, and the output signal Vout is Low.
The boundary of / High is shown. Vref is usually
It is 0.8V.

As can be seen from FIG. 6, the input signal IN is 0
The output signal Vout becomes V from the time when it changes from V to Vcc.
A relatively large delay time T is required before reaching tt. The cause of such a delay is a delay in the falling speed of the output signal voltage Va of the CMOS inverter. That is, in the small-amplitude interface, the value of Vref is as low as 0.8V, so the voltage Va supplied to the gate of the transistor Q1 changes from VCC (5V) to the transistor Q.
It takes a lot of time for the 1 to turn off to a voltage of about Vref (0.8V) at which the output signal Vout rises with a delay.

On the other hand, in the GTL, as shown in FIG. 7, in addition to the open drain type output circuit of FIG. 5, a current boost circuit composed of two transistors Q2 and Q3 and two inverters are composed. And a delay circuit are added. The current boost circuit is CM
This is to accelerate the voltage drop of the output signal voltage Va of the OS inverter, and its effective operation period is determined by the delay time by the delay circuit. The current boost circuit also functions as a feedback circuit for reducing waveform distortion of the output signal Vout such as overshoot and undersheet.

The output characteristic of this GTL is shown in FIG. This output characteristic is when the transistor Q1 is turned off, that is, when the output signal Vout rises from Low to high.

As can be seen from FIG. 8, the input signal IN is 0
For a while after the change from V to Vcc, the voltage Vb supplied to the gate of the transistor Q3 of the current boost circuit is held at Vcc for a time defined by the delay time of the delay circuit. Therefore, both the transistors Q2 and Q3 are in the ON state during the period from when the input signal IN changes to Vcc until the delay time of the delay circuit elapses. As a result, these transistors Q
2, output signal voltage V of the CMOS inverter via Q3
The potential of a is pulled to the output terminal side, and the voltage drop of the output signal voltage Va of the CMOS inverter is accelerated.

The steeper the slope of the fall of Va, the faster the rise of the output signal Vout. Further, the falling slope of Va near Vref is reflected as it is on the waveform of Vout as the steepness of the rising of the output signal Vout.
To prevent noise caused by a sudden change in out,
It is preferable that the falling slope of Va be as smooth as possible near Vref.

However, since the delay circuit composed of two inverters defines the effective operation period of the current boost circuit, if the delay time deviates from the design value due to the process variation of the inverter,
Variation occurs during the effective operation period of the current boost circuit. Therefore, it is practically difficult to accurately control the falling slope of Va immediately after the rising of the input signal IN and to smooth the falling slope after Va becomes close to Vref. is there.

If the delay time of the delay circuit is large and the effective operation period of the current boost circuit is too long, the voltage value of Va becomes the output signal V.
The transistors Q2 and Q3 are maintained in the ON state even after the voltage becomes higher than out, and as a result, as shown in the figure, the current reversion phenomenon in which the voltage value of Va once increases during the process of voltage decrease of Va. Occurs. Such fluctuation of Va becomes a factor that causes noise in the output signal Vout.

[0016]

As described above, the GTL of the conventional time control system in which the effective operation period of the current boost circuit is defined by utilizing the delay time of the delay circuit.
In the circuit, since the delay time of the delay circuit fluctuates due to process variations and the like, immediately after the rising edge of the input signal IN, the slope of the falling edge of Va is made steep and Va
It was practically difficult to perform control such that the slope of the falling edge is smoothed after V becomes near Vref. Therefore, there is a drawback that it is not possible to achieve both the reduction of the output delay time for the high-speed bus drive and the reduction of the output signal distortion.

The present invention has been made in view of the above point. The slope of the fall of Va is made steep immediately after the rise of the input signal IN, and the slope of the fall is made after Va becomes close to Vref. To provide a bus drive circuit and a control method thereof that can easily realize control such as smoothing, and can achieve both reduction of output delay time for high-speed bus drive and reduction of output signal distortion. With the goal.

[0018]

According to the present invention, in a bus drive circuit for driving a bus to which a plurality of devices are commonly connected, an open drain type output circuit and a current for controlling a slew rate of the output circuit are provided. A boost circuit, comprising: a current boost circuit in which a current boost capability is variably set according to a boost control voltage supplied to a control input terminal, the input terminal of the output circuit and the control input terminal of the current boost circuit. By connecting and
The current boosting capability of the current boosting circuit is variably set according to the value of the input signal voltage input to the input end of the output circuit.

In this bus drive circuit, instead of the conventional time control method of defining the effective operation period of the current boost circuit by utilizing the delay time of the delay circuit,
A voltage control method using the value itself of the input signal voltage input to the input terminal of the open drain type output circuit is adopted. That is, the input terminal of the open drain type output circuit and the control input terminal of the current boost circuit are connected to each other, and the current boost circuit of the current boost circuit is connected according to the value of the input signal voltage input to the input terminal of the output circuit. The current boost capability is variably set. Therefore, the current boost capability of the current boost circuit can be gradually reduced as the input signal voltage drops, and the falling slope of the input signal can be made steep by the large current boost capability immediately after the input signal falls. As the value of the input signal voltage decreases, the falling slope can be smoothed. Further, since the open drain type output circuit and the current boost circuit are controlled by the same signal voltage, the operations of the output circuit and the current boost circuit can be balanced. Therefore, it is possible to solve the problem that the current boost circuit continues to operate even after the transistor of the open drain type output circuit is turned off, and it is also possible to prevent the output signal waveform from being disturbed due to the current backtracking phenomenon.

Also, according to the present invention, in a bus drive circuit for driving a bus to which a plurality of devices are commonly connected, an open drain type output circuit and a slew rate of the output circuit which are connected in parallel with each other are controlled. A plurality of current boost circuits, each of which has a current boost capability variably set according to a value of an input signal voltage input to an input terminal of the output circuit, and the plurality of current boost circuits. Is selectively operated.

In this bus drive circuit, a plurality of current boost circuits whose current boosting capability is variably set according to the value of the input signal voltage input to the input terminal of the output circuit are connected in parallel. The plurality of current boost circuits are selectively operated. Therefore, the current boost capability can be changed by selecting a current boost circuit to be operated among a plurality of current boost circuits having different characteristics, or by controlling the number of current boost circuits operating in parallel. Therefore, for example, variations in boost current due to variations in semiconductor manufacturing process
The current boost circuit to be selected and the parallelism can be adjusted depending on the increase / decrease of the parallelism, and the optimum output signal characteristic can be realized. Further, the degree of delay of the output signal and the degree of smoothness of the output waveform can be optimally set according to the bus configuration (stub length, line length, package) to be driven.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a computer system using a bus drive circuit according to the first embodiment of the present invention. In this computer system, a plurality of system devices 11, 12, 13, ... Such as processors and various controllers are connected to the same bus 10, and the system devices 11, 12, 13 ,.
Input / output buffer groups used as high-speed bus interfaces are provided inside the LSIs for realizing 12, 13, ... Each input / output buffer is composed of a GTL-configured bus driver and a receiver.

Each GTL bus driver is for driving one transmission line on the bus 10, and comprises an open drain type buffer circuit and a current boost circuit for controlling the output slew rate of this buffer circuit. It is configured.

As shown, the open drain type buffer circuit includes an open drain type output circuit composed of an N-channel MOS transistor Q1 whose drain is connected to the bus transmission line.
Is a CMOS composed of a P-channel MOS transistor Q11 and an N-channel MOS transistor Q12.
The operation is controlled by the output signal Va of the inverter.

The high side voltage of the output signal Vout of the open drain type buffer circuit is held by the external terminating resistor Rt. Note that Vtt is a power supply voltage supplied to the terminating resistor Rt, and is usually the internal power supply voltage Vcc.
Value lower than (5V or 3.3V), eg 1.2V
It is. The voltage value of this Vtt is h of the output signal Vout.
It becomes the voltage value on the high side.

The current boost circuit accelerates the decrease of the output signal Va of the CMOS inverter and optimizes the slew rate at the time of rising of the output signal of the open drain type output circuit to prevent the occurrence of overshoot or undershoot. used.

That is, when the transmission line of the bus 10 is driven, overshoot and undershoot as shown by the dotted line in FIG. 2 may occur due to the distortion of the signal waveform due to the characteristic impedance of the transmission line. is there. This is a major factor causing malfunction of other devices connected to the bus 10.
Therefore, in the high-speed bus interface, it is necessary not only to increase the response speed of the open drain type output circuit but also to make the rising edge of the output signal sufficiently smooth as shown by the solid line in FIG. In order to achieve this, the current boost circuit is configured as follows.

That is, the current boost circuit includes a transistor Q which serves as a signal input terminal of the open drain type output circuit.
1 and the drain of the transistor Q1 which is the signal output terminal of the open drain type output circuit, and is composed of two N-channel MOS transistors Q2 and Q3 which are connected in series. Controlled by the voltage supplied to the gate of the. In this embodiment, in order to realize a configuration in which the operation of the current boost circuit is controlled by the voltage control method using the value itself of the signal voltage Va input to the signal input terminal of the open drain type output circuit, the gate of the transistor Q3 is realized. Is a CMO composed of a P-channel MOS transistor Q11 and an N-channel MOS transistor Q12.
It is directly connected to the output of the S inverter.

N-channel MOS transistors Q2 and Q3
Is set to be larger than the transistor of the conventional boost circuit shown in FIG. This is to accelerate the fall of Va sufficiently to shorten the propagation delay between Va and Vout.

That is, in this embodiment, as shown in FIG.
Instead of the configuration in which the gate of the transistor Q3 is held at the high level for a certain period by the delay circuit as in the conventional circuit shown in FIG.
Since it is directly connected to the output of the OS inverter, the current boost capability of the current boost circuit decreases as Va decreases. Therefore, it is important to increase the size of the transistors Q2 and Q3 to enhance the current boosting capability immediately after the fall of Va.

The size of the transistors Q2 and Q3 is sufficiently smaller than that of the transistor Q1.
Increasing 2 and Q3 does not affect the overall size of the GTL bus driver. Also, the transistors Q2, Q
The value to be set for the size of 3 may be determined according to the characteristics of the bus transmission line (stub length, line length, etc.). The change characteristic of the current boosting capability of the current boosting circuit can also be controlled by adjusting the relationship between the threshold voltage value of the transistor Q3 and the threshold voltage value of the transistor Q1. In this case, the threshold voltage of the transistor Q3 is
If it is set higher than the threshold voltage value of 1, the current boost operation of the current boost circuit can be terminated before the transistor Q1 is turned off.

The output characteristics of this GTL bus driver are shown in FIG.
Shown in This output characteristic is when the transistor Q1 is turned off, that is, when the output signal Vout rises from Low to high.

When the input signal IN rises from Low to High, Va starts to drop. Immediately after this decrease in Va, the current boosting capability of the current boost circuit is large, so that the potential of the output signal voltage Va of the CMOS inverter is extracted to the output terminal side via the transistors Q2 and Q3, and the output signal voltage Va of the CMOS inverter The voltage drop is accelerated. When the voltage of Va enters the voltage region (a) where the transistor Q1 starts to turn off, the conduction resistance of the transistor Q3 increases, and the current boosting capability of the current boosting circuit starts to decrease. Therefore, after that, V
The lower the value of a, the smoother the slope of the fall.

The falling slope of Va in the voltage region (a) is directly reflected on the waveform of Vout as the steepness of rising of the output signal Vout. Therefore, it is possible to realize control such that the falling slope of Va is made steep immediately after the rising of the input signal IN, and the slope of the falling is made smooth after Va becomes the voltage region (a). Thereby, the propagation delay of Vout can be shortened and the rising waveform thereof can be made sufficiently smooth.

As described above, in the GTL bus driver of this embodiment, the value itself of the signal voltage Va input to the input terminal of the open drain type output buffer is used instead of the time control method using the delay time of the delay circuit. Is used, and the current boost capability of the current boost circuit is variably set according to the value of Va. Therefore, the current boosting capability of the current boosting circuit can be gradually lowered in accordance with the decrease in Va, so that the falling slope of Va can be made steep by the large current boosting capability immediately after the fall of Va.
The lower the value of, the smoother the falling slope can be. Moreover, since the open drain type output buffer and the current boost circuit are controlled by the same signal voltage Va, the operations of the output buffer and the current boost circuit can be balanced. Therefore, it is possible to solve the problem that the current boost circuit continues to operate even after the transistor Q1 is turned off, and it is possible to prevent the output signal waveform from being disturbed due to the current backtracking phenomenon.

FIG. 4 shows a second embodiment of the GTL bus driver. In this GTL bus driver, two first and second current boost circuits (boost circuit 1 and boost circuit 2) whose current boost capability is variably set according to the value of the voltage Va are connected in parallel,
The number of current boost circuits operating in the current boost circuits is controlled by the external control signal CONT.

That is, the first current boost circuit is connected in series between the gate of the transistor Q1 which is the signal input terminal of the open drain type output circuit and the drain of the transistor Q1 which is the signal output terminal of the open drain type output circuit. Two N-channel MOS transistors Q2,
It is composed of Q3, and Va is supplied to the gate of the transistor Q3. The second current boost circuit is connected in series between the gate of the transistor Q1 which is the signal input terminal of the open drain type output circuit and the drain of the transistor Q1 which is the signal output terminal of the open drain type output circuit. It is composed of two N-channel MOS transistors Q4 and Q5, and Va is supplied to the gate of the transistor Q5 through an AND gate G1.

The AND gate G1 is for controlling the degree of parallelism of the current boost circuit, and the external control signal CO
When NT is at the Low level, the supply of Va to the second current boost circuit is prohibited and only the operation of the first current boost circuit is enabled. On the other hand, the external control signal CONT is H
When it is at the high level, the AND gate G1 supplies Va to the second current boost circuit as it is, thereby operating the first and second current boost circuits simultaneously.

Thus, the current boost capability can be changed by variably setting the parallel degree of the current boost circuit. Therefore, for example, variations in boost current due to variations in semiconductor manufacturing process can be adjusted by increasing or decreasing the degree of parallelism, and optimal output signal characteristics can be realized. Also, the degree of delay of the output signal and the degree of smoothness of the output waveform can be optimally set according to the bus configuration (stub length, line length, package) to be driven.

The voltage of the external pin of the LSI package can be used as the control signal CONT. This makes it possible to easily adjust the parallelism of the current boost circuit depending on the mounting form such as grounding the external pin or connecting it to the power supply terminal. The voltage value of the control signal CONT may be determined by the wiring process inside the LSI chip.

In the second embodiment, two current boost circuits are connected in parallel to switch the current boosting capability in two steps. However, more current boost circuits are connected in parallel and the external control signal is supplied. The current boost capability may be switched in multiple stages by.
This is, for example, A for each of the second and subsequent current boost circuits.
An ND gate is provided, Va is supplied to the first input of each AND gate, and different external control signals are supplied to the second input, so that the supply of Va is permitted for each current boost circuit from the second stage onward. It can be realized by prohibiting. Can be realized.

Further, a plurality of current boost circuits having different characteristics are connected in parallel, the current boost circuits are selectively selected by an external control signal, and Va is supplied only to the selected current boost circuit to operate. You may comprise so that it may be made. This is, for example, A for each current boost circuit.
This is realized by providing an ND gate, supplying Va to the first input of each AND gate, and supplying different external control signals to the second input, thereby permitting or prohibiting the supply of Va for each current boost circuit. can do.

[0043]

As described above, according to the present invention, the slope of the fall of Va is made steep immediately after the rise of the input signal IN, and Va is in the voltage region where the transistor of the open drain type output circuit starts turning off. After entering the control, it becomes possible to realize control such as smoothing the falling slope, and it is possible to achieve both reduction of output delay time for high-speed bus drive and reduction of output signal distortion. Further, by connecting a plurality of current boost circuits in parallel and selectively operating the current boost circuits in accordance with an external control signal, it becomes possible to adjust the output waveform according to the characteristics of the bus to be used. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a computer system using a bus driver circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a signal waveform of a bus transmission line required in the system of the first embodiment.

FIG. 3 is a diagram for explaining operating characteristics of a bus driver circuit used in the system of the first embodiment.

FIG. 4 is a circuit diagram showing a configuration of a bus driver circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a normal open drain type output buffer circuit.

FIG. 6 is a diagram for explaining operating characteristics of the open drain type output buffer circuit of FIG.

FIG. 7 is a circuit diagram showing a configuration of a conventional GTL circuit.

FIG. 8 is a diagram for explaining operating characteristics of the GTL circuit of FIG.

[Explanation of symbols]

10 ... Bus, 11-13 ... System device, Q1 ... Output transistor of open drain type output circuit, Q
2, Q3 ... Transistors for current boost circuit, Q4, Q
5 ... Transistor for current boost circuit, G1 ... Gate circuit.

Claims (7)

[Claims] 1. A bus drive circuit for driving a bus to which a plurality of devices are commonly connected, comprising: an open drain type output circuit; and a current boost circuit for controlling a slew rate of the output circuit, wherein a control input A current boost circuit in which a current boost capability is variably set according to a boost control voltage supplied to the terminal, and by connecting an input terminal of the output circuit and a control input terminal of the current boost circuit, A bus drive circuit characterized in that the current boosting capability of the current boosting circuit is variably set according to the value of the input signal voltage input to the input terminal of the output circuit. 2. A bus drive circuit for driving a bus to which a plurality of devices are commonly connected, wherein an open-drain type output circuit and a first and second series-connected output gates of transistors of the output circuit are connected in series. A current boost circuit configured to variably set a current boost capability according to a boost control voltage supplied to the gate of the first transistor, and a gate of the transistor of the output circuit. By connecting the gate of the first transistor of the current boost circuit, the current boost capability of the current boost circuit is variably set according to the value of the input signal voltage input to the gate of the transistor of the output circuit. A bus drive circuit characterized by being configured as follows. 3. A bus drive circuit for driving a bus to which a plurality of devices are commonly connected, wherein an open drain type output circuit and a plurality of currents connected in parallel to each other and controlling the slew rates of the output circuits respectively. A plurality of current boost circuits, each of which has a current boost capability variably set according to a value of an input signal voltage input to an input terminal of the output circuit, and the plurality of current boost circuits are selectively selected. A bus drive circuit comprising: means for operating the bus drive circuit. 4. The means for selectively operating the current boost circuit includes a plurality of current boost circuits in response to an external control signal supplied to an external pin of an LSI package containing a bus drive circuit. 4. The bus drive circuit according to claim 3, wherein the current boost circuits to be operated or the number thereof are determined and the input signal voltage is supplied to the current boost circuits. 5. A bus drive circuit for driving a bus to which a plurality of devices are commonly connected, wherein an open drain type output circuit and a first and a second series connection between a gate and a drain of a transistor of the output circuit are provided. An input signal voltage input to the gate of the transistor of the output circuit is supplied to the gate of the first transistor, and the current boost capability is variably set according to the input signal voltage. A first current boost circuit, and third and fourth transistors connected in series between the gate and drain of the transistor of the output circuit, the gate of the third transistor being connected to the output circuit. The input signal voltage that is input to the gate of the transistor of the A second current boost circuit whose variability is set, and means for permitting or prohibiting the supply of the input signal voltage to the second current boost circuit according to an external control signal. Characteristic bus drive circuit. 6. A bus including an open drain type output circuit, and a current boost circuit which has a current boost capability variably set according to a boost control voltage supplied to a control input terminal and which controls a slew rate of the output circuit. A control method for controlling a drive circuit, wherein an input signal voltage input to an input terminal of the output circuit is directly supplied to a control input terminal of the current boost circuit, and the input signal voltage is changed according to a voltage transition of the input signal voltage. The control method is characterized in that the slew rate at the time of rising of the output signal of the bus drive circuit is controlled by dynamically changing the current boost capability of the current boost circuit. 7. An open drain type output circuit, and a plurality of current boosting capacities that are variably set according to a value of an input signal voltage input to an input terminal of the output circuit, and control a slew rate of the output circuit. A method for controlling a bus drive circuit including a current boost circuit according to claim 1, wherein the current boost circuits to be operated in the plurality of current boost circuits or the number thereof are determined in accordance with an external control signal. A control method, wherein the slew rate at the time of rising of the output signal of the bus drive circuit is controlled by variably setting the current boost circuits permitted to operate, or the number thereof.