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JPH09213881A - Hybrid integrated circuit device and manufacture thereof - Google Patents

Hybrid integrated circuit device and manufacture thereof

Info

Publication number
JPH09213881A
JPH09213881A JP2143296A JP2143296A JPH09213881A JP H09213881 A JPH09213881 A JP H09213881A JP 2143296 A JP2143296 A JP 2143296A JP 2143296 A JP2143296 A JP 2143296A JP H09213881 A JPH09213881 A JP H09213881A
Authority
JP
Japan
Prior art keywords
conductor
opening
conductors
integrated circuit
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2143296A
Other languages
Japanese (ja)
Other versions
JP3656307B2 (en
Inventor
Takahisa Koyasu
貴久 子安
Koji Numazaki
浩二 沼崎
Mitsuhiro Saito
斎藤  光弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP02143296A priority Critical patent/JP3656307B2/en
Publication of JPH09213881A publication Critical patent/JPH09213881A/en
Application granted granted Critical
Publication of JP3656307B2 publication Critical patent/JP3656307B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To properly mount a semiconductor chip on a board by a method wherein a conductor land is kept constant in area even if a mask alignment slippage occurs between a conductor and a protective glass. SOLUTION: An integrated circuit device is formed through such a manner that conductors 2 are printed on a thick film board 1 through a screen printing method, and a protective glass 3 is screen-printed on the conductor 2 so as to make a part of the conductor 2 exposed to serve as a conductor land 2a, and the electrode 5 of a semiconductor chip 4 is soldered onto the conductor land 2a, wherein the opening of the protective glass 3 for the conductor land 2a is so formed as to be located on a part of each of the conductors 2 which the side of a frame-like opening 7 intersects. Therefore, even if the opening 7 deviates laterally and vertically from from the conductor 2, a distance between the edges of the opening 7 is kept constant, so that the conductor land 2a can be kept constant in area, and the semiconductor chip 4 can be properly mounted on the board 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、厚膜基板上に露出
して形成された導体と半導体素子の電極とがはんだ付け
されてなる混成集積回路装置およびその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device in which a conductor exposed on a thick film substrate and an electrode of a semiconductor element are soldered, and a manufacturing method thereof.

【0002】[0002]

【従来の技術】図7に従来の混成集積回路装置の構成を
示す。(a)は断面構成図、(b)は半導体素子として
の半導体チップを厚膜基板にはんだ付けする前の状態を
示す平面図である。混成集積回路装置は、厚膜基板1上
に複数の導体2をスクリーン印刷し、導体2の一部が露
出するように厚膜基板1の上に絶縁膜としての保護ガラ
ス3をスクリーン印刷し、露出した導体2上に四角形状
の半導体チップ4の電極5(表面がはんだで覆われたも
の)をはんだ付けして構成される。
2. Description of the Related Art FIG. 7 shows the structure of a conventional hybrid integrated circuit device. (A) is a cross-sectional configuration diagram, and (b) is a plan view showing a state before a semiconductor chip as a semiconductor element is soldered to a thick film substrate. The hybrid integrated circuit device screen-prints a plurality of conductors 2 on the thick-film substrate 1, and screen-prints a protective glass 3 as an insulating film on the thick-film substrate 1 so that a part of the conductors 2 is exposed. An electrode 5 (having a surface covered with solder) of a rectangular semiconductor chip 4 is soldered on the exposed conductor 2.

【0003】保護ガラス3は、図7(b)に示すよう
に、導体2の一部の領域(以下、導体ランドという)2
aが露出するように開口部6を有して形成されており、
その導体ランド2aに半導体チップ4の電極5がはんだ
付けされる。なお、図7(b)において、保護ガラス3
の形成領域をハッチングで示している。
As shown in FIG. 7B, the protective glass 3 has a partial region 2 of the conductor 2 (hereinafter referred to as a conductor land).
a is formed so as to expose a,
The electrode 5 of the semiconductor chip 4 is soldered to the conductor land 2a. In FIG. 7B, the protective glass 3
The formation region of is indicated by hatching.

【0004】[0004]

【発明が解決しようとする課題】上記した従来のもので
は、導体2の長手方向の1箇所を保護ガラス3で区切る
ことにより導体ランド2aを形成している。この場合、
導体2と保護ガラス3のマスク合わせズレが生じなけれ
ば、全ての導体ランド2aの面積を均一にして、半導体
チップ4の電極5を良好にはんだ付けすることができ
る。
In the conventional device described above, the conductor land 2a is formed by partitioning the conductor 2 at one position in the longitudinal direction with the protective glass 3. in this case,
If there is no mask misalignment between the conductor 2 and the protective glass 3, the areas of all the conductor lands 2a can be made uniform and the electrodes 5 of the semiconductor chip 4 can be soldered well.

【0005】しかしながら、導体2と保護ガラス3のマ
スク合わせズレが生じると、導体ランド2aの面積が一
定にならない。例えば、図8(b)に示すように保護ガ
ラス3が図の右側へズレて形成された場合には、露出距
離a、bが異なり、左右の導体ランド2aの面積が不均
一になる。このため、導体ランド2a上に供給されるは
んだ高さが不均一になり、図8(a)に示すように半導
体チップ4を適正に組み付けることができない。また、
場合によっては電極5のオープン、はんだつぶれによる
導体ランド2a間のショートなどの問題も生じうる。
However, if mask misalignment between the conductor 2 and the protective glass 3 occurs, the area of the conductor land 2a is not constant. For example, as shown in FIG. 8B, when the protective glass 3 is formed so as to be displaced to the right side of the drawing, the exposure distances a and b are different, and the areas of the left and right conductor lands 2a are not uniform. For this reason, the height of the solder supplied onto the conductor lands 2a becomes non-uniform, and the semiconductor chip 4 cannot be properly assembled as shown in FIG. Also,
In some cases, problems such as opening of the electrode 5 and short-circuiting between the conductive lands 2a due to crushed solder may occur.

【0006】特に、近年、ICの高集積化および1チッ
プ化により、半導体チップ4の電極数が多くなってきて
おり、半導体チップ4の電極サイズおよび導体ランド2
aを微細化する場合には、上記した問題が顕著になる。
本発明は上記問題に鑑みたもので、導体と絶縁膜との間
に位置ズレが生じても導体ランドの面積を一定にするこ
とを目的とする。
In particular, in recent years, the number of electrodes of the semiconductor chip 4 has been increasing due to the high integration of the IC and the integration into one chip.
When a is miniaturized, the above-mentioned problem becomes remarkable.
The present invention has been made in view of the above problems, and an object of the present invention is to make the area of a conductor land constant even if a positional deviation occurs between the conductor and the insulating film.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するた
め、請求項1乃至14に記載の発明においては、導体ラ
ンド(2a)を形成するための開口部(7、7a〜7
d、7e〜7r)が、導体(2)の長手方向において導
体上に両端が位置するように形成されていることを特徴
としている。
In order to achieve the above object, in the invention described in claims 1 to 14, openings (7, 7a to 7a) for forming conductor lands (2a) are formed.
d, 7e to 7r) are formed so that both ends are located on the conductor in the longitudinal direction of the conductor (2).

【0008】従って、導体の長手方向に絶縁膜との間で
位置ズレが生じても、開口部の両端間の距離が一定であ
るため、導体ランドの面積を一定にすることができる。
このことにより、半導体素子を適正に実装することがで
きる。また、請求項11に記載のように、導体群(A〜
D)毎に4つの開口部(7a〜7d)を分離して形成
し、それぞれのコーナー部において導体を形成するよう
にすれば、コーナー部に電極を有する半導体素子におい
ても、適正に導体ランドを形成することができる。
Therefore, even if the conductor is misaligned with the insulating film in the longitudinal direction, the area of the conductor land can be made constant because the distance between both ends of the opening is constant.
As a result, the semiconductor element can be mounted properly. Moreover, as described in claim 11, the conductor group (A to
If the four openings (7a to 7d) are formed separately for each D) and the conductors are formed at the respective corners, conductor lands can be properly formed even in a semiconductor element having electrodes at the corners. Can be formed.

【0009】また、請求項14に記載の発明のように、
半導体素子が位置する領域において厚膜導体が露出する
ように絶縁膜を形成すれば、半導体素子と厚膜導体との
間に空間を確保して、モールドする場合のモールド材の
侵入を容易にすることができる。
According to the invention described in claim 14,
If the insulating film is formed so that the thick film conductor is exposed in the region where the semiconductor element is located, a space is secured between the semiconductor element and the thick film conductor to facilitate the intrusion of the molding material when molding. be able to.

【0010】[0010]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

(第1実施形態)図1(a)に第1実施形態に係る混成
集積回路装置の断面構成を示し、同図(b)に半導体チ
ップを厚膜基板にはんだ付けする前の平面構成を示す。
厚膜基板1上には、並列配置された複数の帯状の導体2
が形成されており、それらは四角形の4辺の位置関係を
なす第1乃至第4の導体群A〜Dを構成している。ここ
で、導体ランド2aを形成するための保護ガラス3の開
口部は、図7で示した従来の開口部6と異なり、図1
(b)に示すように、第1乃至第4の導体群A〜Dのそ
れぞれを横切るようにして形成された1つの枠状の開口
部7となっている。
(First Embodiment) FIG. 1A shows a sectional structure of a hybrid integrated circuit device according to the first embodiment, and FIG. 1B shows a plane structure before soldering a semiconductor chip to a thick film substrate. .
A plurality of strip-shaped conductors 2 arranged in parallel on the thick film substrate 1.
Are formed, and they form first to fourth conductor groups A to D having a positional relationship of four sides of a quadrangle. Here, the opening of the protective glass 3 for forming the conductor land 2a is different from that of the conventional opening 6 shown in FIG.
As shown in (b), one frame-shaped opening 7 is formed so as to cross each of the first to fourth conductor groups A to D.

【0011】この開口部7は、それぞれの導体2の長手
方向において導体2上に両端が位置しているため、開口
部7が導体2に対し上下左右方向にズレても、開口部7
の両端が導体2上に位置している限り、導体ランド2a
の面積は一定となる。なお、導体2および保護ガラス3
には印刷ズレがあり、また導体2と保護ガラス3との間
にはマスク合わせズレがあるが、前者をαμm、後者を
±βμmとした時、導体2の端部と開口部7の端部との
距離(図(b)に示すd)が、α+βμm以上になるよ
うに設定しておけば、図2に示すように最大限のズレが
生じても、導体1上に開口部7の両端を位置させること
ができるため、導体ランド2aの面積を一定にすること
ができる。
Since both ends of the opening 7 are located on the conductor 2 in the longitudinal direction of each conductor 2, even if the opening 7 is displaced in the vertical and horizontal directions with respect to the conductor 2, the opening 7 is formed.
As long as both ends of the conductor are located on the conductor 2, the conductor land 2a
Area is constant. The conductor 2 and the protective glass 3
Has a print misalignment and a mask misalignment between the conductor 2 and the protective glass 3, but when the former is αμm and the latter is ± βμm, the end of the conductor 2 and the end of the opening 7 are If the distance (d in FIG. 2 (b)) is set to be α + β μm or more, even if the maximum deviation occurs as shown in FIG. Can be positioned, so that the area of the conductor land 2a can be made constant.

【0012】従って、導体ランド2a上に供給されるは
んだ高さを均一にして、半導体チップ4を適正に組み付
けることができる。次に、本実施形態に係る混成集積回
路装置の製造方法について図3を基に説明する。 〔図3(a)の導体印刷工程〕厚膜導体1上に印刷マス
ク10を設置し、導体ペースト11をスキージ12を用
いてスクリーン印刷し、厚さ約10μmの導体2を形成
する。 〔図3(b)の焼成・乾燥工程〕導体2が印刷された厚
膜導体1を、焼成し、乾燥させる。 〔図3(c)の抵抗印刷・焼成・乾燥工程〕所望の導体
2間に、混成集積回路の一部をなす抵抗体13を印刷形
成し、その後、焼成、乾燥を行う。 〔図3(d)の保護ガラス印刷工程〕印刷マスク14を
設置し、ガラスペースト15をスキージ16を用いてス
クリーン印刷し、厚さ約15μmの保護ガラス3を形成
する。この場合、印刷マスク14として、保護ガラス3
の形成パターンが図1(b)のようになるものを用い
る。 〔図3(e)の焼成・乾燥工程〕保護ガラス3が形成さ
れた厚膜導体1を、焼成し、乾燥させる。 〔図3(f)のはんだ印刷工程〕印刷マスク17を設置
し、はんだペースト18をスキージ19を用いてスクリ
ーン印刷し、導体ランド2a上にはんだ20を形成す
る。 〔図3(g)の素子組付工程〕半導体チップ4の電極5
を導体ランド2a上のはんだ20に位置合わせしてはん
だ付けする。 (第2実施形態)半導体チップ4のサイズが小さくコー
ナー部にも電極5が存在する場合には、図4に示すよう
に、コーナー部に導体2が存在するように導体2の形成
パターンを設定し、保護ガラス3の開口部を、第1乃至
第4の導体群A〜Dのそれぞれに対応して分割した開口
部7a〜7dとする。
Therefore, the height of the solder supplied onto the conductor land 2a can be made uniform, and the semiconductor chip 4 can be properly assembled. Next, a method of manufacturing the hybrid integrated circuit device according to this embodiment will be described with reference to FIG. [Conductor Printing Step of FIG. 3A] A printing mask 10 is placed on the thick film conductor 1, and a conductor paste 11 is screen-printed using a squeegee 12 to form a conductor 2 having a thickness of about 10 μm. [Firing / Drying Step of FIG. 3B] The thick film conductor 1 on which the conductor 2 is printed is fired and dried. [Resistance Printing / Firing / Drying Step of FIG. 3C] A resistor 13 forming a part of the hybrid integrated circuit is formed by printing between desired conductors 2, and then firing and drying are performed. [Protective Glass Printing Step of FIG. 3D] The print mask 14 is installed, and the glass paste 15 is screen-printed using the squeegee 16 to form the protective glass 3 having a thickness of about 15 μm. In this case, the protective mask 3 is used as the print mask 14.
1 is used as the formation pattern of FIG. [Firing / Drying Step of FIG. 3 (e)] The thick film conductor 1 on which the protective glass 3 is formed is baked and dried. [Solder Printing Step of FIG. 3 (f)] The printing mask 17 is set, the solder paste 18 is screen-printed using the squeegee 19, and the solder 20 is formed on the conductor land 2a. [Device Assembly Step of FIG. 3G] Electrode 5 of Semiconductor Chip 4
Is aligned with the solder 20 on the conductor land 2a and soldered. (Second Embodiment) When the size of the semiconductor chip 4 is small and the electrodes 5 also exist at the corners, the formation pattern of the conductors 2 is set so that the conductors 2 exist at the corners, as shown in FIG. Then, the openings of the protective glass 3 are divided into openings 7a to 7d corresponding to the first to fourth conductor groups A to D, respectively.

【0013】この場合、4つの開口部7a〜7dは四角
形状の4辺の位置関係にあり、それぞれのコーナー部に
おいて、導体2が存在することになる。従って、この実
施形態においても、それぞれの開口部により導体ランド
2aの面積を一定にすることができる。 (第3実施形態)上記した第1実施形態では、半導体チ
ップ4と厚膜基板1との間に保護ガラス3が存在して形
成されるが、このようにすると、半導体チップ4を実装
後、樹脂モールドする際に、モールド材が半導体チップ
4と厚膜基板1との間に入りにくくなる可能性がある。
In this case, the four openings 7a to 7d are in the positional relationship of the four sides of the quadrangular shape, and the conductor 2 is present at each corner. Therefore, also in this embodiment, the area of the conductor land 2a can be made constant by each opening. (Third Embodiment) In the above-described first embodiment, the protective glass 3 is formed between the semiconductor chip 4 and the thick film substrate 1, but in this case, after mounting the semiconductor chip 4, When resin-molding, the molding material may be difficult to enter between the semiconductor chip 4 and the thick film substrate 1.

【0014】そこで、この実施形態においては、図5に
示すように、上部に半導体チップ4が位置する領域8に
おいて保護ガラス3を形成せずに厚膜導体1を露出させ
るようにしている。従って、半導体チップ4と厚膜基板
1との間に空間が確保されるため、モールド材を半導体
チップ4と厚膜基板1との間に入れやすくすることがで
きる。 (第4実施形態)上記した種々の実施形態では、導体群
に対して開口部を形成するものを示したが、図6に示す
ように、個々の導体2に対して開口部7e〜7rを形成
するようにしてもよい。この場合、上下左右方向に導体
2と保護ガラス3間においてマスク合わせズレが生じて
も、導体2の長手方向、幅方向に開口部3aのそれぞれ
の両端が位置するため、導体ランド2aの面積を一定に
することができる。
Therefore, in this embodiment, as shown in FIG. 5, the thick film conductor 1 is exposed without forming the protective glass 3 in the region 8 where the semiconductor chip 4 is located. Therefore, since a space is secured between the semiconductor chip 4 and the thick film substrate 1, the molding material can be easily inserted between the semiconductor chip 4 and the thick film substrate 1. (Fourth Embodiment) In the various embodiments described above, the openings are formed in the conductor group. However, as shown in FIG. 6, the openings 7e to 7r are formed in the individual conductors 2. It may be formed. In this case, even if mask misalignment occurs between the conductor 2 and the protective glass 3 in the vertical and horizontal directions, since both ends of the opening 3a are positioned in the longitudinal direction and the width direction of the conductor 2, the area of the conductor land 2a is reduced. Can be constant.

【0015】この実施形態における開口部としては、図
に示すような正方形に限らず、それ以外の多角形でもよ
く、また円形でもよい。また、この実施形態に対し、上
記第3実施形態のように、上部に半導体チップ4が位置
する領域8において保護ガラス3を形成しないようにし
てもよい。なお、上述した種々の実施形態において、厚
膜基板1としては、単層の基板に限らず、絶縁膜を介し
て下部と上部導体が形成される厚膜2層基板や、導体が
内部に何層も形成されている多層基板であってもよい。
The opening in this embodiment is not limited to a square as shown in the figure, but may be a polygon other than the square or a circle. Further, in contrast to this embodiment, the protective glass 3 may not be formed in the region 8 where the semiconductor chip 4 is located, as in the third embodiment. In the various embodiments described above, the thick-film substrate 1 is not limited to a single-layer substrate, but a thick-film two-layer substrate in which a lower conductor and an upper conductor are formed via an insulating film or a conductor inside the thick-film substrate. It may be a multilayer substrate in which layers are also formed.

【0016】また、導体上に形成する絶縁膜としては、
保護ガラス以外に、絶縁ガラスを用いることもできる。
As the insulating film formed on the conductor,
Insulating glass may be used instead of the protective glass.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施形態に係る混成集積回路装置
の構成を示す図である。
FIG. 1 is a diagram showing a configuration of a hybrid integrated circuit device according to a first embodiment of the present invention.

【図2】図1に示すものにおいて、導体2と保護ガラス
3との間に位置ズレが生じた場合の状態を示す図であ
る。
FIG. 2 is a diagram showing a state in the case where a positional deviation occurs between a conductor 2 and a protective glass 3 in the thing shown in FIG.

【図3】図1に示す混成集積回路装置の製造工程を示す
工程図である。
FIG. 3 is a process drawing showing a manufacturing process of the hybrid integrated circuit device shown in FIG.

【図4】本発明の第2実施形態を示す図である。FIG. 4 is a diagram showing a second embodiment of the present invention.

【図5】本発明の第3実施形態を示す図である。FIG. 5 is a diagram showing a third embodiment of the present invention.

【図6】本発明の第4実施形態を示す図である。FIG. 6 is a diagram showing a fourth embodiment of the present invention.

【図7】従来の混成集積回路装置の構成を示す図であ
る。
FIG. 7 is a diagram showing a configuration of a conventional hybrid integrated circuit device.

【図8】図7に示すものにおいて、導体2と保護ガラス
3との間に位置ズレが生じた場合の問題点を説明するた
めの図である。
FIG. 8 is a diagram for explaining a problem in the case where a positional deviation occurs between the conductor 2 and the protective glass 3 in the thing shown in FIG. 7.

【符号の説明】[Explanation of symbols]

1…厚膜基板、2…導体、3…保護ガラス、4…半導体
チップ、5…電極、7、7a〜7d、7e〜7r…開口
部。
DESCRIPTION OF SYMBOLS 1 ... Thick film substrate, 2 ... Conductor, 3 ... Protective glass, 4 ... Semiconductor chip, 5 ... Electrode, 7, 7a-7d, 7e-7r ... Opening.

Claims (15)

【特許請求の範囲】[Claims] 【請求項1】 厚膜基板(1)と、この厚膜基板上に形
成された帯状の導体(2)と、この導体の一部が露出す
るように前記厚膜基板上に形成された絶縁膜(3)と、
前記露出した導体上に電極(5)がはんだ付けされた半
導体素子(4)とを有する混成集積回路装置において、 前記絶縁膜は、前記導体の一部を露出させるための開口
部(7、7a〜7d、7e〜7r)を有し、かつ前記帯
状の導体の長手方向において前記導体上に前記開口部の
両端が位置するように形成されていることを特徴とする
混成集積回路装置。
1. A thick film substrate (1), a strip-shaped conductor (2) formed on the thick film substrate, and an insulation formed on the thick film substrate so that a part of the conductor is exposed. A membrane (3),
In a hybrid integrated circuit device having a semiconductor element (4) having an electrode (5) soldered on the exposed conductor, the insulating film has an opening (7, 7a) for exposing a part of the conductor. .About.7d, 7e to 7r) and is formed so that both ends of the opening are located on the conductor in the longitudinal direction of the strip-shaped conductor.
【請求項2】 前記厚膜基板上に、前記帯状の導体が複
数並列配置されており、それらの帯状の導体を横切るよ
うに前記絶縁膜の開口部(7、7a〜7d)が形成され
ていることを特徴とする請求項1に記載の混成集積回路
装置。
2. A plurality of the strip conductors are arranged in parallel on the thick film substrate, and openings (7, 7a to 7d) of the insulating film are formed so as to cross the strip conductors. The hybrid integrated circuit device according to claim 1, wherein:
【請求項3】 前記厚膜基板上に、前記帯状の導体が前
記長手方向に対向して離間配置されており、それらの対
向配置した帯状の導体のそれぞれに前記開口部(7、7
a〜7d、7e〜7r)が形成されていることを特徴と
する請求項1又は2に記載の混成集積回路装置。
3. The strip conductors are arranged on the thick film substrate so as to be opposed to each other in the longitudinal direction, and the openings (7, 7) are provided in the strip conductors arranged to face each other.
a-7d, 7e-7r) are formed, The hybrid integrated circuit device of Claim 1 or 2 characterized by the above-mentioned.
【請求項4】 前記開口部(7e〜7r)は前記導体の
幅方向にも両端を有しており、この幅方向の両端が前記
導体上に位置するように前記絶縁膜が形成されているこ
とを特徴とする請求項1乃至3のいずれか1つに記載の
混成集積回路装置。
4. The opening (7e to 7r) has both ends in the width direction of the conductor, and the insulating film is formed so that both ends in the width direction are located on the conductor. The hybrid integrated circuit device according to any one of claims 1 to 3, wherein
【請求項5】 厚膜基板(1)と、 この厚膜基板上に並列配置された複数の帯状の導体
(2)からなる第1の導体群(A(又はB))と、 前記厚膜基板上に前記第1の導体群と離間して並列配置
された複数の帯状の導体からなる第2の導体群(C(又
はD))と、 前記それぞれの導体の一部が露出するように前記厚膜基
板上に形成された絶縁膜(3)と、 前記露出した導体上に電極(5)がはんだ付けされた半
導体素子(4)とを備え、 前記絶縁膜は、前記それぞれの導体の一部を露出させる
ための開口部(7、7a〜7d、7e〜7r)を有し、
かつ前記開口部は、前記それぞれの導体上で導体の長手
方向において両端が位置するように形成されていること
を特徴とする混成集積回路装置。
5. A thick film substrate (1), a first conductor group (A (or B)) composed of a plurality of strip-shaped conductors (2) arranged in parallel on the thick film substrate, and the thick film. A second conductor group (C (or D)) composed of a plurality of strip-shaped conductors that are arranged in parallel on the substrate so as to be separated from the first conductor group, and a part of each of the conductors is exposed. An insulating film (3) formed on the thick film substrate, and a semiconductor element (4) in which an electrode (5) is soldered on the exposed conductor, the insulating film is formed of each of the conductors. It has openings (7, 7a to 7d, 7e to 7r) for exposing a part,
Further, the opening is formed so that both ends of the opening are located on the respective conductors in the longitudinal direction of the conductors.
【請求項6】 前記開口部(7)は、枠状のものであっ
て、その1辺が前記第1の導体群を横切り、他の1辺が
前記第2の導体群を横切るように形成されていることを
特徴とする請求項5に記載の混成集積回路装置。
6. The opening (7) has a frame-like shape, and one side of the opening (7) crosses the first conductor group and the other side thereof crosses the second conductor group. The hybrid integrated circuit device according to claim 5, wherein
【請求項7】 前記開口部は、前記第1の導体群を横切
るように形成された第1の開口部(7a(又は7b))
と、前記第2の導体群を横切るように形成された第2の
開口部(7c(又は7d))を有していることを特徴と
する請求項5に記載の混成集積回路装置。
7. The first opening (7a (or 7b)) formed so as to cross the first conductor group.
And a second opening (7c (or 7d)) formed so as to traverse the second conductor group, the hybrid integrated circuit device according to claim 5.
【請求項8】 厚膜基板(1)と、 この厚膜基板上に、四角形における4辺の位置関係で形
成され、それぞれの辺において並列配置された複数の帯
状の導体(2)からなる第1乃至第4の導体群(A〜
D)と、 前記それぞれの導体の一部が露出するように前記厚膜基
板上に形成された絶縁膜(3)と、 前記露出した導体上に電極(5)がはんだ付けされた半
導体素子(4)とを備え、 前記絶縁膜は、前記それぞれの導体の一部を露出させる
ための開口部(7、7a〜7d、7e〜7r)を有し、
かつ前記開口部は、前記それぞれの導体上で導体の長手
方向において両端が位置するように形成されていること
を特徴とする混成集積回路装置。
8. A thick film substrate (1) and a plurality of strip-shaped conductors (2) formed on the thick film substrate in a positional relationship of four sides in a quadrangle and arranged in parallel on each side. 1 to 4 conductor groups (A to
D), an insulating film (3) formed on the thick film substrate so that a part of each of the conductors is exposed, and a semiconductor element in which an electrode (5) is soldered on the exposed conductor ( 4), the insulating film has openings (7, 7a to 7d, 7e to 7r) for exposing a part of each of the conductors,
Further, the opening is formed so that both ends of the opening are located on the respective conductors in the longitudinal direction of the conductors.
【請求項9】 前記開口部は前記第1乃至第4の導体群
を横切るようにして形成された1つの開口部(7)から
なることを特徴とする請求項8に記載の混成集積回路装
置。
9. The hybrid integrated circuit device according to claim 8, wherein the opening comprises one opening formed so as to cross the first to fourth conductor groups. .
【請求項10】 前記開口部は前記第1乃至第4の導体
群の導体群毎に分離して形成された4つの開口部(7a
〜7d)からなることを特徴とする請求項8に記載の混
成集積回路装置。
10. The four openings (7a) formed separately for each conductor group of the first to fourth conductor groups.
~ 7d), the hybrid integrated circuit device according to claim 8.
【請求項11】 前記4つの開口部は四角形状の4辺の
位置関係あり、それぞれのコーナー部において前記第1
乃至第4群のいずれかに属する導体が形成されているこ
とを特徴とする請求項10に記載の混成集積回路装置。
11. The four openings have a positional relationship of four sides having a quadrangular shape, and the first opening is provided at each corner.
11. The hybrid integrated circuit device according to claim 10, wherein a conductor belonging to any one of the fourth to fourth groups is formed.
【請求項12】 前記開口部(7e〜7r)は、前記そ
れぞれの導体上で導体の長手方向と幅方向に両端を有す
る多角形のものであることを特徴とする請求項5又は8
に記載の混成集積回路装置。
12. The opening (7e-7r) is a polygonal shape having both ends in the longitudinal direction and the width direction of the conductor on the respective conductors.
The hybrid integrated circuit device according to.
【請求項13】 前記開口部(7e〜7r)は、前記そ
れぞれの導体上に位置するように形成された円形のもの
であることを特徴とする請求項5又は8に記載の混成集
積回路装置。
13. The hybrid integrated circuit device according to claim 5, wherein the openings (7e to 7r) are circular ones formed so as to be located on the respective conductors. .
【請求項14】 前記保護膜は、上部に前記半導体素子
が位置する領域において前記厚膜導体が露出するように
形成されていることを特徴とする請求項1乃至13のい
ずれか1つに記載の混成集積回路装置。
14. The protective film is formed so that the thick film conductor is exposed in a region where the semiconductor element is located above. Integrated circuit device.
【請求項15】 厚膜基板(1)上に導体(2)を印刷
形成し、導体の一部が露出するように絶縁膜(3)を前
記厚膜基板上に印刷形成し、前記露出した導体上に半導
体素子(4)の電極(5)をはんだ付けするようにした
混成集積回路装置の製造方法において、 前記絶縁膜を前記導体の長手方向において前記導体上に
両端を有して開口形成したことを特徴とする混成集積回
路装置の製造方法。
15. A conductor (2) is formed by printing on a thick film substrate (1), and an insulating film (3) is formed by printing on the thick film substrate so that a part of the conductor is exposed. A method of manufacturing a hybrid integrated circuit device, wherein electrodes (5) of a semiconductor element (4) are soldered on a conductor, wherein an opening is formed in the insulating film having both ends on the conductor in a longitudinal direction of the conductor. A method for manufacturing a hybrid integrated circuit device characterized by the above.
JP02143296A 1996-02-07 1996-02-07 Hybrid integrated circuit device and manufacturing method thereof Expired - Fee Related JP3656307B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP02143296A JP3656307B2 (en) 1996-02-07 1996-02-07 Hybrid integrated circuit device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02143296A JP3656307B2 (en) 1996-02-07 1996-02-07 Hybrid integrated circuit device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH09213881A true JPH09213881A (en) 1997-08-15
JP3656307B2 JP3656307B2 (en) 2005-06-08

Family

ID=12054829

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3656307B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103733A (en) * 2005-10-05 2007-04-19 Nec Electronics Corp Substrate and semiconductor device using the same
JP2007227731A (en) * 2006-02-24 2007-09-06 Matsushita Electric Ind Co Ltd Printed circuit board and electronic instrument employing it
JP2015138925A (en) * 2014-01-24 2015-07-30 株式会社村田製作所 Multilayer wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103733A (en) * 2005-10-05 2007-04-19 Nec Electronics Corp Substrate and semiconductor device using the same
JP2007227731A (en) * 2006-02-24 2007-09-06 Matsushita Electric Ind Co Ltd Printed circuit board and electronic instrument employing it
JP2015138925A (en) * 2014-01-24 2015-07-30 株式会社村田製作所 Multilayer wiring board
US9370092B2 (en) 2014-01-24 2016-06-14 Murata Manufacturing Co., Ltd. Multilayer wiring board

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