JPH09153557A - Manufacture of floating gate-type non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a floating gate-type non-volatile semiconductor memory including a silicide layer optimized according to each necessary characteristic in source and drain regions. SOLUTION: A field oxide film 12 is formed selectively on a silicon substrate 11. A gate oxide film 13 is formed on the silicon substrate 11. A gate electrode made of polysilicon film is formed on the gate oxide film 13. A silicide layer 15 is formed on the gate electrode, and spacer oxide films 16 and 17 are formed on the side faces of the gate electrode 15. Then, a source region 19 and a drain region 20 are formed with a channel region 18 in between. Each silicide layer 21 or 22 is formed in the source or drain region 19 or 20. In this case, the depth D2 of the silicide layer 22 on the drain side is smaller than the depth D1 of the silicide layer 21 on the source side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a floating gate type nonvolatile semiconductor memory device having a silicide layer as a low resistance layer.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, it has become necessary to further reduce the sheet resistance and contact resistance of impurity diffusion layers. A leading technology that meets this requirement is the silicide technology.

The silicide technology is, for example, as follows. First, the surface of the impurity diffusion layer formed in the semiconductor substrate is exposed, and a refractory metal such as Ti, Co, or Ni is deposited on the exposed surface. Then, heat treatment is applied to the semiconductor substrate. As a result, the silicon (S
i) reacts with the metal to form a silicide layer such as TiSi ₂ . If this silicide layer is thick enough, the sheet resistance and contact resistance will be reduced by an order of magnitude as compared with the case without the silicide layer. Therefore, the silicide technology is becoming indispensable in the submicron MOS technology.

In the MOS transistor, the diffusion layer becomes shallower with the miniaturization, and the sheet resistance of the diffusion layer becomes low.
As a result, the contact resistance between the diffusion layer and the metal wiring layer increases. In order to prevent this increase in resistance, a salicide structure in which a silicide layer is formed on the polysilicon gate, the source region and the drain region has been put into practical use. In the salicide structure, a refractory metal is deposited on the polysilicon gate, the source region and the drain region, and then heat treatment is applied to form a silicide layer.

[0005]

However, with the miniaturization of semiconductor elements, the depth of the impurity diffusion layer is becoming shallower. If heat treatment is performed on a relatively shallow (eg, 0.2 μm) impurity diffusion layer with a metal for forming a silicide layer deposited too thick (eg, titanium 0.1 μm), silicidation occurs The reaction proceeds too much and the formed silicide breaks the pn junction. In such a state, the leak becomes too large to be used as a semiconductor device.

On the other hand, it is conceivable to reduce the film thickness of the metal according to the depth of the impurity diffusion layer, or to shorten the heat treatment time even if the film thickness of the metal is thick to form a thin silicide layer. However, in this case, the reduction of the sheet resistance is insufficient and the merit of silicidation is reduced.

The disadvantage of thinning the silicide layer is that there is a problem in that the sheet resistance of the wiring layer made of polysilicon in the multilayer wiring structure and the contact resistance at the connection between the wiring layers are reduced.

Further, in forming a salicide structure in a conventional MOS transistor, a polysilicon gate,
A refractory metal having a uniform film thickness is deposited on the source region and the drain region, and a substantially uniform heat treatment is applied to the substrate to form a silicide layer. Therefore, the silicide layer is formed at the same depth in the source region and the drain region.

However, in the MOS type transistor, the source side and the drain side have different tolerances to the leakage current at the source / drain junction surface. More specifically, normally, a voltage is applied to the drain region of the MOS transistor, but the source region is floating or grounded. Therefore, the junction leak is severely limited in the drain region, but is tolerant in the source region.

Therefore, it is desired to form a thin silicide layer in the drain region to suppress erosion of the diffusion layer by the silicide and prevent junction leakage. On the other hand, in the source region, it is preferable that the silicide layer is formed thicker than the drain region to reduce the contact resistance between the diffusion layer and the upper wiring layer.

However, in the conventional MOS type transistor having the salicide structure, as described above, the silicide layer having the same depth is formed in the source region and the drain region. Therefore, a silicide layer optimized according to the characteristics required for the source region and the drain region is not formed. Further, in the conventional method for manufacturing a MOS transistor having a salicide structure, it is not possible to form a silicide layer that is optimized according to the characteristics required for the source region and the drain region.

It is an object of the present invention to provide a method of manufacturing a floating gate type non-volatile semiconductor memory device capable of forming a silicide layer optimized according to the characteristics required in the source region and the drain region. And

[0013]

According to the present invention, a source region and a drain region formed with a channel region sandwiched therebetween are provided.
Forming a first metal layer made of a silicide forming metal capable of forming a silicide by a reaction with silicon on a silicon substrate having a floating gate made of silicon provided above the channel region; Forming a reaction suppression layer that suppresses a silicidation reaction in a region on the first metal layer that includes at least the upper side of the drain region and excludes the upper side of the source region;
Forming a second metal layer composed of the silicide forming metal on the first metal layer including the reaction suppressing layer; heat treating the silicon substrate to form the source region, the first metal layer and the first metal layer; Two metal layers, between the drain region and the first metal layer, and between the floating gate and the first metal layer or both the first metal layer and the second metal layer and the first polysilicon. Forming a silicide layer in each of the source region, the drain region and the floating gate by a silicidation reaction with a layer, forming an insulating layer on the silicide layer formed on the surface of the floating gate,
And a method of manufacturing a floating gate non-volatile semiconductor memory device, comprising the step of forming a floating gate on the insulating layer.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. In FIG. 1, 11 indicates a silicon substrate. A field oxide film 12 is selectively formed on the silicon substrate 11. A gate oxide film 13 is formed on the silicon substrate 11. A gate electrode 14 made of a polysilicon film is formed on the gate oxide film 13. A silicide layer 15 is formed on the surface of the gate electrode 14. The drain side portion 15a of the silicide layer 15 is formed to be thinner than the source side portion 15b. Spacer oxide films 16 and 17 are formed on the side surfaces of the gate electrode 14.

The silicon substrate 11 has a channel region 1
A source region 19 and a drain region 20 are formed with 8 in between. Source region 19 and drain region 20
Are respectively composed of the low-concentration impurity diffusion regions n ⁻ and the high-concentration impurity diffusion regions n ⁺ formed adjacent to the n ⁻ . The LDD structure is constituted by the low concentration impurity diffusion region n ⁻ and the high concentration impurity diffusion region n ⁺ .

Silicide layers 21 and 22 are formed in the source region 19 and the drain region 20, respectively.
As shown in FIG. 2, the depths D ₁ and D ₂ of the source-side silicide layer 21 and the drain-side silicide layer 22 from the surface S ₀ of the silicon substrate 11 to the source region 19 and the drain region 20 are different from each other. That is,
The depth D ₂ of the drain side silicide layer 22 is formed shallower than the depth D ₁ of the source side silicide layer 21.

In the MOS transistor 10 described above, it is required that the source side silicide layer 21 and the drain side silicide layer 22 have different depths D ₁ and D ₂ in the source region 19 and the drain region 20. It is excellent in that it can satisfy different characteristics. That is, the MOS transistor 10 has a source / source
The tolerance for the leak current at the drain junction surface is different. Normally, a voltage is applied to the drain region 20 of the MOS transistor 10, but the source region 19 is floating or grounded.
For this reason, the drain region 20 is severely limited in junction leakage, but the source region 19 is tolerant. Therefore, it is preferable to form the drain side silicide layer 22 shallowly to suppress the erosion of the diffusion layer by the silicide and prevent the junction leak. On the other hand, in the source region 19, even if the source-side silicide layer 21 is deeply formed and the junction leak easily occurs, there is no problem because the junction leak is tolerant. Therefore, the depth D of the source-side silicide layer 21
₁ is formed thicker than the drain region 22, and the source region 1 is formed.
It is preferable to lower the contact resistance between 9 and the upper wiring layer (not shown) and the sheet resistance of the source region 19.

Further, in order to achieve the high density of the MOS transistor 10, the depth D ₃ of the high concentration impurity diffusion region n ⁺ of the source region 19 and the drain region 20 is sufficiently thin, and the source side silicide layer is provided. It is preferable that the depths D ₁ and D _{2 of the} drain silicide layer 21 and the drain side silicide layer 22 are optimized values. Specifically, the silicide layer 21 with respect to the depth D ₃ of the high-concentration impurity diffusion region n ⁺ ,
It is preferable that the depths D ₁ and D _{2 of} 22 have the following relationship.

D ₁ : D ₃ = 0.2: 1 to 0.8: 1 D ₂ : D ₃ = 0: 1 to 0.6: 1 When the depths D _{1 to} D ₃ satisfy the above relationship, , Even if the high-concentration impurity diffusion region n ⁺ becomes shallow and the sheet resistance becomes high,
The silicide layers 21 and 22 provided in the source region 19 and the drain region 20, respectively, reduce the resistance.
Further, the drain region 20 is more severely restricted in terms of junction leakage than the source region 19, but since the drain side silicide layer 22 is formed to have a shallow depth D ₂ , the occurrence of junction leakage is suppressed. On the other hand, in the source region 19, the restriction on the junction leakage is tolerant, and therefore,
By forming the source-side silicide layer 22 to have a large depth D ₁ , that is, to form the source-side silicide layer 22 to have a large thickness, it is possible to further reduce the resistance.

The source side silicide layer 21 and the drain side silicide layer 22 are composed of the same or different silicides. Here, the silicide includes tungsten silicide, titanium silicide, cobalt silicide, and nickel silicide.

The silicide layer 15 formed on the surface of the gate electrode 14 may be made of the same silicide as the source side silicide layer 21 and the drain side silicide layer 22. Further, the silicide layer 15, the source-side silicide layer 21, and the drain-side silicide layer 22 may all have a salicide structure formed in the same process.

In this embodiment, the gate electrode 14 is made of a single polysilicon, but at least the uppermost layer of the gate electrode 14 may be made of silicon.
Further, the silicide layer does not necessarily have to be formed on the gate electrode 14. Further, the silicide layer 15 may have a uniform film thickness.

MOS type transistor 1 of the above embodiment
0 is formed as follows, for example. As shown in FIG. 3 (A), a silicon substrate 11 is formed on the silicon substrate 11 by a selective thermal oxidation method (L
The field oxide film 12 is formed according to the OCOS method. Further, a gate oxide film 13 having a film thickness of 150 angstrom (A), for example, is formed in the active region defined by the field oxide film 12 by a thermal oxidation method.

Next, a polysilicon film 31 having a film thickness of 3000 A, for example, is deposited on the gate oxide film 13. The polysilicon film 31 is doped with phosphorus (P) as an impurity according to the vapor phase diffusion method in order to increase the conductivity.

After that, a resist pattern (not shown) is formed on the polysilicon film 31, and reactive ion etching (RIE) using hydrogen bromide gas and chlorine gas as etching gas is performed to form a polysilicon film. 31 and the exposed gate oxide film 13 are patterned. As a result, as shown in FIG. 3B, the gate electrode 14 is formed above the channel region 18 of the silicon substrate 11.

P ions are implanted at a low concentration into the silicon substrate 11 on which the gate electrode 14 is formed in this manner to form a low concentration diffusion layer n ⁻ .

Next, as shown in FIG. 3C, a silicon oxide film 32 is formed on the silicon substrate 11 by the CVD method, and the silicon oxide film 32 is etched by anisotropic RIE. As a result, spacer oxide films 16 and 17 are formed on the side surfaces of the gate electrode 14 as shown in FIG.

Then, as shown in FIG. 3 (E), As ions are implanted into the exposed silicon substrate 11 at a high concentration to form a high-concentration diffusion layer n ^+, and the source region 19 of the so-called LDD structure is formed. And the drain region 20 is formed.

As shown in FIG. 4, a first metal layer 41 is formed on the entire surface of the silicon substrate 11 including the source region 19, the drain region 20 and the gate electrode 14. Here the first
The metal forming the metal layer is a metal capable of forming a silicide by the reaction with silicon (hereinafter referred to as a silicide forming metal). This silicide forming metal is, for example, a refractory metal, and more specifically, it is at least one selected from tungsten (W), cobalt (Co), titanium (Ti), and nickel (Ni). The first metal layer 41 can be formed by using a known thin film forming technique such as sputtering or CVD.

Specifically, the first metal layer 41 has a film thickness of 50.
A titanium layer having a thickness of not more than 10 nm, specifically 10 nm, is formed by CVD using sputtering.

Next, the reaction suppressing layer 42 is formed on the first metal layer 41.
It is formed in a region including at least the upper side of the drain region 20 and excluding the upper side of the source region 19 above. Specifically, the field oxide film 12 on the drain side, the drain region 20, the spacer oxide film 17 on the drain side, and
The reaction suppressing layer 42 is formed in a region extending to about half the surface of the gate electrode 14. The reaction suppressing layer 42 is a low resistance material that does not cause a silicidation reaction with silicon at all or causes a silicidation reaction but has a lower reactivity than the metal. An example of the reaction suppression layer is metal nitride. This metal nitride may be, for example, a nitride of the above-mentioned silicide forming metal. More specifically, it is at least one selected from the group consisting of titanium nitride, cobalt nitride, nickel nitride, and tungsten nitride. The reaction suppression layer is
When it is a metal nitride, it does not necessarily have to be a nitride of the same metal as the first metal layer. When the reaction suppressing layer is a metal nitride, it is formed by, for example, CVD or sputtering.

The reaction suppressing layer 42 has, for example, a film thickness of 2
A titanium nitride film having a thickness of 0 nm or less, preferably 0.5 to 20 nm is formed on the first metal layer 41 by N ₂ 0.5 to 3%,
It is formed by reactive sputtering of Ar 97 to 99.5%.

A second metal layer 43 is formed on the entire surface of the first metal layer 41 including the reaction suppressing layer 42. Like the first metal layer 41, the second metal layer 43 is made of a silicide forming metal. The first metal layer 41 and the second metal layer 43 do not necessarily have to be made of the same metal.

After that, the silicon substrate 11 is heat-treated. More specifically, RTN (Rapid thermal Nitrization) is performed in a nitrogen or ammonia atmosphere. By this heat treatment, as shown in FIG. 5, a silicidation reaction proceeds between the source region 19 and the first metal layer 41 and the second metal layer 43 to form a thick source-side silicide layer 21.

On the other hand, a first metal layer 41, a reaction suppressing layer 42 and a second metal layer 43 are sequentially laminated on the drain region 20. When heat treatment is applied to this laminated structure,
Silicon constituting the drain region 20 and the first metal layer 41
A silicidation reaction occurs between them. However, the reaction suppressing layer 42 is provided on the first metal layer 41. As described above, the reaction suppressing layer 42 does not cause a silicidation reaction with silicon or causes a silicidation reaction with silicon, but the reactivity thereof is the first metal layer 4.
The first and second metal layers 43 are made of a material lower than that of the metal. Therefore, the first metal layer 41 reacts with silicon to promote silicidation, but the first metal layer 4
After all 1 are silicified and used up, the silicidation reaction stops or becomes significantly slowed in the reaction suppressing layer 42. Therefore, if the first metal layer 41 is entirely silicidized, the thickness of the drain side silicide layer 22 does not become thicker. Therefore, the shallow silicide layer 22 is formed in the drain region 20. Moreover, the film thickness of the silicide layer 22 depends on the film thickness of the first metal layer 41 and does not depend on the temperature and time of the heat treatment. Further, the reaction suppressing layer 42 is formed on the surface of the gate electrode 14 only in about half of the drain side. Therefore, the reaction suppression layer 42 of the gate electrode 14
In the region where is formed, the silicidation reaction occurs only between the silicon forming the gate electrode 14 and the first metal layer 41, and the thin drain side portion 15a is formed.
On the other hand, the reaction suppression layer 42 is not formed in the remaining source-side region of the gate electrode 14. Therefore, in the region on the source side, silicon and the first metal layer 41 and the second metal layer 41 are formed.
A silicidation reaction occurs with the metal layer 42. As a result, a thick source side portion 15b is formed on the gate electrode 14.

However, the reaction suppressing layer 42 may be formed on the entire surface of the gate electrode 14 or may be heat-treated without being formed on the gate electrode 14 to form a silicide layer having a uniform film thickness. .

Then, etching is performed with NH ₄ OH,
The unreacted first metal layer 41, reaction suppression layer 42, and second metal layer 43 are removed. After that, an interlayer insulating film, an upper wiring layer, etc. are formed according to a normal process, and finally a MO film is formed.
The S-type transistor 10 is obtained.

In the method of manufacturing the MOS transistor 10 described above, the film thickness of the source side silicide layer 21 and the drain side silicide layer 22 is controlled by changing the film thicknesses of the first metal layer 41 and the second metal layer 43. it can. For example, the junction depth X _Sj of the source region 19 and the drain region 20
_Are defined as the junction depth X _Dj , the thickness t _{1 of} the first metal layer 41, and the thickness t ₂ of the second metal layer 43.
When the metal layer is composed of titanium, these four values preferably satisfy the following relationships.

T ₁ <X _Dj /2.25 [∵ The thickness of silicon consumed for the thickness t ₁ of the first metal layer is 2.24, and the formed silicide (Ti
The thickness of Si) is 2.50. ] T ₁ + t ₂ <X _sj /2.25 t ₁ = 0 or 0 <t ₁ <100 (nm) [∵ Junction depth is assumed to be 0.23 μm or less. ] T ₁ <t ₁ + t ₂ More preferably, t ₁ ≦ 0.7 × X _Dj /2.25(n
m), that is, the condition of 0 ≦ t ₁ ≦ 70 (nm) is satisfied.

By appropriately setting the film thickness of the first metal layer 41 as described above, the depth D ₂ of the drain side silicide layer 22 formed in the drain region 20 can be optimized.
By making the depth D ₂ of the drain side silicide layer 22 sufficiently shallow, it is possible to prevent junction leakage from occurring due to excessive erosion of the silicide.

As a method for controlling the film thickness of the silicide layer, electrically inactive ions such as silicon ions, oxygen ions and nitrogen ions are ion-implanted only in the source region,
There is known a method of selectively increasing the thickness of the silicide layer formed in the source region by damaging the surface of the silicon layer with crystallinity and smoothly performing the silicidation reaction. However, according to this method, plasma damage and heavy metal contamination are always likely to occur due to ion implantation. For this reason, it is common to form an oxide film or the like on the source region as a protective layer before ion implantation. In this case, it is necessary to remove the oxide film after the ion implantation.

Further, in this method, the source region is damaged by the ion implantation. Therefore, before forming the silicide layer, dilute HF cleaning or the like is generally performed to expose the surface of the silicon substrate. At this time, if the silicon layer is damaged by the ion implantation, there arises a disadvantage that the layer becomes chemically unstable and a layer that is not normally etched is etched.
For this reason, it is necessary to perform heat treatment for recovering damage after the ion implantation.

According to the method of manufacturing the semiconductor device of the present embodiment described above, the source region 1 is formed without performing ion implantation.
It is possible to prevent the problems associated with the ion implantation such as the silicide layers 21 and 22 having different film thicknesses in the 9 and the drain region 20 as in the conventional method for controlling the film thickness of the silicide layer.

FIG. 6 is a sectional view showing a memory cell transistor of a flash EPROM according to the second embodiment of the present invention. 6, the same components as those of the MOS transistor 10 shown in FIG. 1 are designated by the same reference numerals.

In the second embodiment, the floating gate 61 of the memory cell transistor 40 has the same structure as the gate electrode 14 of the MOS transistor 10 of the first embodiment shown in FIG. On the surfaces of the silicide layer 15, the source side silicide layer 21 and the drain side silicide layer 22 formed on the floating gate 61, a silicon oxide film 62, a silicon nitride film 63 and a silicon oxide film 64 are sequentially formed as a second gate oxide film. It is stacked. A control gate 65 made of a polysilicon film is formed on the silicon oxide film 64. The silicon oxide film 62, the silicon nitride film 63, the silicon oxide film 64, and the control gate 65 can be formed by a conventional method.

As a modification of the memory cell transistor of the second embodiment, as shown in FIG. 7, the surfaces of the silicide layer 15, the source side silicide layer 21 and the drain side silicide layer 22 formed on the floating gate 61. A silicon oxide film 71 is formed thereover by CVD. Next, the silicon oxide film 71 is etched back and flattened until the surface of the silicide layer 15 is exposed. After that, a silicon oxide film 62, a silicon nitride film 63, and a silicon oxide film 64 are sequentially stacked on the surfaces of the silicide layer 15 and the silicon oxide film 71 to form a second gate insulating film, and the surface of the silicon oxide film 64 is formed. A control gate 65 is formed on the substrate. In this case, since there is a thick insulating film on the source region 19 and the drain region 20, the control gate 65 and the source region 19 or the drain region 2 are formed.
There is an advantage that leakage between 0s can be suppressed.

A flash EPR having the memory cell transistors 60 and 70 shown in FIGS. 6 and 7 as described above.
OM is excellent in the following points. Single power supply flash EPR
F-N programming and F-N erasing are the main techniques in OM. If the state in which the threshold voltage of the memory cell transistor is high is set to the erased state, a positive voltage is applied to the drain during programming, and the source region becomes floating or grounded. During erasing, an additional voltage is applied to the source region and the silicon substrate. As described above, the junction between the source region and the silicon substrate has the same potential or only the floating potential is applied to the source region.
Therefore, there is no need to worry about an increase in junction leakage due to the voltage application between the source region and the silicon substrate. Even if a thick silicide layer is formed in the source region, there is no need to worry about junction leakage. Therefore, as shown in FIGS. 6 and 7, the depth D ₁ of the source-side silicide layer 21 formed in the source region 19 with respect to the source region 19 is increased to reduce the sheet resistance and the contact resistance of the source region 19. .

On the other hand, in the drain region 20, since a voltage is applied, it is necessary to worry about an increase in junction leak. Therefore, as shown in FIG. 6 and FIG. 7, in the memory cell transistors 60 and 70 of this embodiment, the depth D ₂ of the drain side silicide layer 22 formed in the drain region 20 with respect to the drain region 20 is made shallow to form the drain region. It is possible to prevent a junction leak between the semiconductor substrate 20 and the silicon substrate 11.

Further, in the flash EPROM, the source line is shared with many cells for batch erasing.
Therefore, the total length of the source line becomes long. In the memory cell transistors 60 and 70 of this embodiment, since the depth D ₁ of the source side silicide layer 21 with respect to the source region 19 is deep and the sheet resistance and the contact resistance in the source region 19 are reduced, the gap between the cells is reduced. Reduces the variation in threshold value. Further, as a result, the number of cells that can be connected to one source line can be increased, so that the area of the memory cell array can be reduced.

Further, on the gate electrode 14, a silicide layer 15 having different film thicknesses is formed on the drain side portion 15a and the source side portion 15b. Therefore, the surface area of the floating gate 61 is increased by the amount of the step, as compared with the case where the silicide layer having a uniform film thickness is formed. As a result, the gate couple ratio can be increased. This is excellent in that the writing and erasing characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a main part of the semiconductor device according to the first embodiment of the present invention.

3A to 3E are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 6 is a sectional view showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 is a sectional view showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

[Explanation of symbols]

10 ... MOS type transistor, 11 ... Silicon substrate, 1
2 ... Field oxide film, 13 ... Gate oxide film, 14 ... Gate electrode, 15 ... Silicide layer, 16, 17 ... Spacer oxide film, 18 ... Channel region, 19 ... Source region,
20 ... Drain region, 21 ... Source side silicide layer, 2
2 ... Drain side silicide layer, 31 ... Polysilicon layer,
32 ... Silicon oxide film, 41 ... First metal layer, 42 ... Reaction suppression layer, 43 ... Second metal layer, 60, 70 ... Memory cell transistor, 61 ... Floating gate, 62, 64
... Silicon oxide film, 63 ... Silicon nitride film, 65 ... Control gate, 71 ... Silicon oxide film.

Claims (1)

[Claims] 1. A silicide is formed by a reaction with silicon on a silicon substrate having a source region and a drain region formed with a channel region sandwiched therebetween, and a floating gate made of silicon provided above the channel region. Forming a first metal layer composed of a silicide-forming metal that can be formed, suppressing a silicidation reaction in a region on the first metal layer including at least the upper side of the drain region and excluding the upper side of the source region Forming a reaction suppressing layer, forming a second metal layer composed of the silicide forming metal on the first metal layer including the reaction suppressing layer, heat-treating the silicon substrate to form the source region. Between the first metal layer and the second metal layer, between the drain region and the first metal layer, and The source region, the drain region and the floating gate are formed on the source region, the drain region and the floating gate by a silicidation reaction between the loading gate and the first metal layer or both the first metal layer and the second metal layer and the first polysilicon layer. A floating process comprising: forming a silicide layer respectively; forming an insulating layer on the silicide layer formed on the surface of the floating gate; and forming a floating gate on the insulating layer. Method of manufacturing gate type non-volatile semiconductor memory device.