JPH09101917A - Cache memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate memory access by monitoring the type and configuration of a main memory and preferentially allocating a cache memory to a low-speed access component. SOLUTION: First of all, a CPU 101 requests the memory access and simultaneously outputs a CPU address 102. This CPU address 102 is applied to an address comparator circuit 106 inside a cache control circuit part 103 and compared with a tag address 118 outputted from a tag SRAM 111, and a discriminate signal 107 is outputted. At the same time, a cache mapping control circuit part 104 outputs a mapping signal 105 corresponding to the constitutive form of the main memory and the address area of the memory access requested by the CPU 101. This mapping signal 105 performs the access control of a data SRAM 110, tag SRAM 111 and DRAM control circuit part 119.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control method and an information processing apparatus using the method, and more particularly to a static random access memory (hereinafter referred to as SRAM) used as a cache memory as an information recording medium. The present invention relates to the capacity of the main memory when a dynamic random access memory (hereinafter referred to as DRAM) is used as the memory and the control of an address area targeted for the cache memory according to the configuration.

[0002]

2. Description of the Related Art Conventionally, as a main memory control method in which the cache memory is mounted, a DRAM which is a main memory is disclosed, for example, in Japanese Patent Laid-Open No. 3-296992.
SRAM has a built-in cache memory inside the chip, and by using a part of the DRAM column address as the SRAM address, the number of data block entries is increased, and the cache hit rate is improved. Are known.

FIG. 7 is a block diagram showing the configuration of a semiconductor memory device equipped with a main memory having a built-in cache memory, which is disclosed in Japanese Patent Laid-Open No. 3-296992.

In FIG. 7, 701 is a multiprocessor (hereinafter referred to as CPU), 702 is a cache control circuit, and 703.
Is a tag unit, 704 is a multiplexer, 705 is a DRAM control circuit,
706 is a main memory unit with a built-in cache memory (hereinafter referred to as main memory unit), 707 is a DRAM unit, and 707a to 707d are DRAs.
M data bit plane part, 707e parity bit plane part, 708 SRAM part, 708a to 708d SRAM data bit plane part, 709 ECC circuit part, 710 CPU address A0-A1
7, 711 is way address WA0, WA1, 712 is cache hit signal CH, 713 is memory address A0-A8, A9-A17, 71
4 is RAS-N / CAS-N signal, 715 is UCE flag, 716 is EF flag, 717 is transfer control signal BT, 718 is data bus DQ1-DQ4
It is.

FIG. 8 is a timing chart showing the operation of the semiconductor memory device shown in FIG.

The outline of the operation of the conventional semiconductor memory device shown in FIGS. 7 and 8 will be described below.

In FIG. 7, the tag unit 703 includes a tag memory, a comparator, and a replacement logic execution unit.
The tag unit 103 includes 64 sets of row address signals RA0 to RA8.
Is stored as a tag address. Each set includes four sets of tag addresses corresponding to the four ways W1 to W4.
The CPU 701 generates address signals A0 to A17 710. The address signals A0 to A8 710 are input as tag addresses, and the address signals A9 to A14 are input as set addresses to the comparator of the tag unit 703. The comparator compares the four sets of row address signals RA0 to RA8 (entry addresses) stored in the set corresponding to the set addresses A9 to A14 710 with the input tag address 710. When the tag addresses A0 to A8 710 match any of the four sets of row address signals RA0 to RA8, the way addresses WA0 and WA1 711 corresponding to the row address signals RA0 to RA8 are output and the "H" level signal is output. The cache hit signal 712 is output.

While the comparator of the tag unit 703 is performing the comparison, the multiplexer 704 inputs the memory address signals A9 to A17 713 to the SRAM unit 708 inside the main memory unit 706 as a cache address, and the SR
AM section 708 is accessed at the same time. As a result, 16 of 4 ways corresponding to the memory address signals A9 to A17 713
Bit data is output.

As shown in the timing chart of FIG.
If a cache hit occurs in that cycle, the tag unit 103 outputs the way addresses WA0 and WA1 711.
In response to the way addresses WA0 and WA1 711, the four ways are decoded by the way decoder in the main memory 706.
One way is selected from W1 to W4. This allows
4-bit data 718 is output in total. in this way,
In the case of a cache hit, high speed access is realized.

If a cache miss occurs in that cycle, a row address strobe signal and a column address strobe signal generated by the DRAM control circuit 705 are generated.
714 (hereinafter referred to as RAS-N / CAS-N signals) DRAM section 70
7 accesses will be made. In this case, the cache hit signal 712 becomes "L" level.

The column address buffer inside the main memory unit 706 is provided with the cache hit signal 712 of "L" level.
In response, the memory addresses A9 to A17 713 provided from the multiplexer 704 are latched. Next, the multiplexer 704 gives the memory addresses A0 to A8 713 to the main memory unit 706.

The row address buffer in the main memory unit 706 responds to the falling edge of the RAS-N signal 714 and outputs the memory addresses A0 to A8 713 as row address signals RA0 to RA8 to the row decoder in the main memory unit 706. give.

After that, the column address buffer inside the main memory unit 706 responds to the fall of the CAS-N signal 714 with the latched memory addresses A9-A17 713 as column address signals CA0 to CA8. It is given to the column decoder inside the memory unit 706. As a result, an 8-bit data block is read from each DRAM data bit plane section 707a to 707d.

Four DRAM data bit plane sections 707a
The 32-bit total data read from ˜707d is transferred to the ECC circuit unit 709 together with the 8-bit check bits read from the parity bit plane unit 707e. When there is no error in the transferred data or when there is a correctable error, the UCE flag 715 holds "L" level as shown in the timing chart of FIG.

If there is no error, the EF flag 716 is "L".
The level is held, and if there is a correctable error, the EF flag 716 rises to "H" level. If there is an error that cannot be transferred in the transferred data, the UCE
The flag 715 and the EF flag 716 rise to "H" level. In this case, data including an error is output.
The data transfer from the DRAM block 707 to the SRAM block 708 at the time of misread and write is performed by the cache control circuit 7
It is controlled by the transfer control signal BT 717 given by 02. The address signal signals A0 to A8 and A9 shown in FIG.
A17 indicates the memory address 713 output from the multiplexer 704.

As described above, in the prior art, the DRAM used as the main memory and the SRAM used as the cache memory are formed on the same chip, and a part of the column address of the DRAM is used as the address of the SRAM which is the cache memory. By increasing the number of data block entries in the cache, the main memory can be processed at high speed.

[0017]

However, in the above-mentioned prior art, since the DRAM as the main memory and the SRAM for the cache memory are formed on the same chip, the cache SRAM built in one chip is allocated to another chip. I can't. Therefore, there is a problem in that the speed-up effect by the cache memory does not appear when the memory chip is speeded up only by the DRAM by the bank interleaved structure or the like.

Further, in the above-mentioned prior art, although the DRAM and the SRAM for cache memory are constructed on the same chip as the main memory and the mounting area is not increased, the capacity of the cache memory or the main memory is reduced. To increase or decrease the number, both memory capacities are increased or decreased, which makes it difficult to achieve a desired memory configuration.

An object of the present invention is to provide a cache memory control method capable of high-speed access by changing the allocation address of the cache memory according to the type and configuration of the DRAM used as the main memory.

It is another object of the present invention that, in a certain type of DRAM used as a main memory, the SRAM that is the cache memory can be allocated only to the area that is accessed at a low speed. An object of the present invention is to provide an information processing apparatus equipped with a cache memory control method capable of realizing a downsized configuration and cost reduction.

[0021]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the type and configuration of the DRAM used as the main memory is monitored, and the SRAM, which is the cache memory, is preferentially allocated to the low-speed access constituent parts to realize the high-speed memory access. It was done like this.

Further, a cache mapping control circuit having a cache mapping register for holding an allocation area of SRAM which is a cache memory, a CPU address decoder, an address comparison circuit for comparing a CPU address and a tag address, and a main memory. It is provided with a control circuit, a DRAM used as a main memory, and an SRAM used for cache data and tags.

According to the above means, the cache memory is preferentially given to the area having the low speed access configuration according to the type and configuration of the DRAM used as the main memory.
Since SRAM is allocated, the main memory can be accessed at high speed. Also, by not allocating the SRAM, which is the cache memory, to the area that has the high-speed access configuration, it is possible to reduce the number of the SRAM that is the cache memory used while realizing the high-speed access of the main memory. Can also realize cost reduction

[0025].

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the schematic arrangement of an information processing apparatus equipped with a cache control circuit according to an embodiment of the present invention.

In FIG. 1, 101 is a central processing unit (hereinafter referred to as CPU), and 102 is a CPU output from the CPU 101.
An address, 103 is a cache control circuit unit, 104 is a cache mapping control circuit unit that controls the main control in this development, and 105 is a cache mapping control signal output from the cache mapping control circuit unit (hereinafter referred to as a mapping signal). , 106 is an address comparison circuit section for judging a cache hit / miss in each memory access, 107 is a signal output from the address comparison circuit section 106 showing the result of the address comparison judgment (hereinafter, judgment signal 1
, 108 is an AND gate, 109 is the judgment signal 1 107
, A signal indicating the result of the address comparison determination reflecting the state of the mapping signal 105 (hereinafter referred to as determination signal 2),
110 is a static random access memory for cache data (hereinafter referred to as data SRAM), 111 is a static random access memory for cache tag that holds a cache address (hereinafter referred to as tag SRAM), and 112 is the data SRAM 110. A chip select signal (hereinafter, referred to as CS1) output by the cache control circuit unit 103 for selecting, a 113 is a chip select signal (hereinafter, CS2) output by the cache control circuit unit 103 for selecting the tag SRAM 111. , 114 is a NAND gate 1, 115 is a NAND gate 2, and 116 is the NAND gate 1 114.
A chip select signal (hereinafter referred to as CS1-N) that is output from the NAND gate 2 115 and is output from the NAND gate 2 115 and is supplied to the tag SRAM 111 (hereinafter referred to as CS2-N). , 118 is the tag SR
The tag address output from the AM 111, 119 is a main memory control circuit unit (hereinafter, referred to as DRAM control circuit unit), 120 is a main memory (hereinafter, referred to as DRAM), 121 is output from the DRAM control circuit unit 119. DRAM 120 control signals (hereinafter referred to as DRAM control signals) are shown.

The information processing apparatus according to the present embodiment has the above-described configuration, and has a system configuration that enables high-speed access by preferentially allocating a cache memory to a DRAM whose main memory is non-interleaved.

The outline of the operation of the information processing apparatus of this embodiment will be described below with reference to FIG.

As shown in FIG. 1, first, the CPU 101 issues a memory access request and, at the same time, outputs the CPU address 102. This CPU address 102 is the cache control circuit section 10
3 The tag SRAM provided to the internal address comparison circuit unit 106
It is compared with the tag address 118 output from 111, and the determination signal 1107 is output. At the same time, the cache mapping control circuit unit 104 outputs the mapping signal 105 according to the configuration of the main memory and the address area of the memory access requested by the CPU 101. The mapping signal 105 controls access to the data SRAM 110, the tag SRAM 111, and the DRAM control circuit unit 119. For the data SRAM 110, the cache control circuit unit 1
The CS1-N signal 116 is generated by using the CS1 signal 112 output from 03 and the NAND gate 114. For the tag SRAM 111, the CS output from the cache control circuit unit 103
2 The signal 113 and the NAND gate 115 are used to generate the CS2-N signal 117. Further, for the DRAM control circuit unit 119, the judgment signal 1 107 and the judgment signal 2 using the AND gate 108 are used.
109 is generated, and the above D
The RAM control circuit section 119 is a DRAM control signal for the DRAM 120.
Output control of 1.

Table 1 is a list showing the memory access targets in each signal state in the schematic configuration diagram of the information processing apparatus shown in FIG. Here, in order to simplify the description, consideration of the sameness between the main memory and the cache memory is omitted, and only access performance is considered. Therefore, in the operation at the time of cache miss in the memory read cycle of Table 1, the read cycle from the main memory is the access target, and the write operation to the cache memory, which is originally performed at the same time for the sake of data identity, is omitted. As a result, even in the cache hit cycle, access to the cache memory is prohibited and access to the main memory is performed depending on the result of confirmation of the configuration state of the DRAM 120 by the cache mapping control circuit unit 104.

FIG. 2 is a detailed configuration diagram of the cache mapping control circuit unit 104 which controls the main control in the present development.

In FIG. 2, 201 is a cache mapping register, 202 to 207 are AND gates, and 208 to 21.
0 indicates each OR gate.

Table 2 shows operation modes according to the type and configuration of the DRAM 120 in the detailed configuration diagram shown in FIG. In Table 2, as memory type, 256kB, 1MB, 4MB and 16M
B In addition, although the bank configuration of the memory is shown as having a total of 6 banks of bank 0 to bank 5, the memory type of 256 kB will be described as an example in the following description.

First, the operation in the case of the non-interleaved configuration as the first memory configuration will be described. In this case, Table 2 above
Bit 1 of the cache mapping register at
Both 0 and 0 are "0" (low), there is no identification address, and the cache mapping is the start address (0MB ~)
Done by In this operation, in FIG. 2, the memory configuration is determined at the time of system startup, and the cache mapping
Bits 1 and 0 of the register 201 are both set to "0" (low). As a result, the output of the AND gate 202 becomes a valid state (high), and the mapping signal 105 is validated through the OR gate 208. In this case, the mapping signal
Since the CPU address 102 is irrelevant to the condition for enabling 105, the DRAM 102 of all banks are targeted for cache.

FIG. 3 is a cache memory mapping diagram for this operation, and FIG. 6 is an operation timing chart. 3 and 6, all banks (bank 0 to bank 5) have a non-interleaved configuration.
The burst cycle number for the DRAM 120 requires 10 CLK cycles, but if the cache is a hit cycle, the burst cycle number can be processed in 6 CLK cycles.

As a second memory configuration, an operation will be shown in the case where only banks 0 and 1 are interleaved and the other banks are non-interleaved. In this case, each bit of the cache mapping register in Table 2 is “0, 0, 0, 1” from the upper bit, and A19 and A20 in the CPU address 102 are used as the identification address, and the cache mapping is It is performed from 512kB. In this operation, in FIG. 2, the memory configuration is discriminated at the time of system startup, and each bit of the cache mapping register 201 is set to “0, 0, 0, 1” from the higher order. Accordingly, the output of AND gate 203 is A19 in CPU address 102 or
If any of A20 is “1” (high), it becomes valid (high) and the mapping signal is output through the OR gate 208.
Enable 105. In this case, the CPU address 102 is A
If either 19 or A20 is "1" (high), cache control is enabled, so DRAM 1 in bank 2 and later
02 will be cached.

FIG. 4 shows a mapping diagram of the cache memory for this operation.

In the operation timing chart shown in FIG. 6, in the interleaved configuration of bank 0 and bank 1, independent column address
Since strobe signals (CASX-N, CASY-N) are given, they can be accessed using each other's precharge period,
The number of burst cycles is 6 CLK cycles, and it is possible to process the same number of cycles as the number of cycles by the cache. In other words, even if the cache mapping is performed on the interleaved DRAM 102, the processing time is not shortened. Therefore, the DRAM 102 which has a non-interleaved configuration by the CPU address (A19, A20) 102 which is an identification address here.
By shortening the processing time in the cache hit cycle, the bank 2 and subsequent banks are cached.

As a third memory configuration, the operation in the case where banks 0 and 1 and banks 2 and 3 are interleaved and the other banks are non-interleaved, the operation is the same as the case where only banks 0 and 1 are interleaved. And the CPU address that is an identification address (A19, A20)
The D that is non-interleaved by 102
By shortening the processing time in the cache hit cycle, the banks 4 and later of the RAM 102 are cached.

As a fourth memory configuration, banks 0 and 1,
Banks 2 and 3 and banks 4 and 5, the DR
The operation when all the AM 102 have the interleaved configuration will be described. In this case, bits 1 and 0 of the cache mapping register in Table 2 are both "1".
(High), there is no identification address, and cache mapping is performed from the start address (0MB-). In this operation, in FIG. 2, the memory configuration is discriminated when the system is started, and both bits 1 and 0 of the cache mapping register 201 are set to "1" (high). Along with this, the output of the AND gate 207 becomes the valid state (high), and the mapping signal 105 is validated through the OR gate 208. In this case, since the CPU address 102 is irrelevant to the condition for validating the mapping signal 105, the DRAMs 102 of all the interleaved banks are cached.

FIG. 5 shows a mapping diagram of the cache memory for this operation.

In the operation timing chart shown in FIG. 6, the number of burst cycles of interleaved DRAM and the number of burst cycles of cache SRAM are 6 CLK.
Since the cycles are the same, the reduction of the processing time by the cache memory when all the DRAMs 102 have the interleaved structure cannot be recognized.

Furthermore, when the write-back control method is used as the write method of the cache memory, the cache address information stored in the tag SRAM 111 is conventionally set by limiting the DRAM 120 area to be cached as in the present development. It is possible to add information for speeding up access during write miss cycles and information for maintaining the sameness between the data of DRAM 120 and data SRAM 110 due to the smaller number of technologies. Becomes Table 3 shows a function list of the tag SRAM 111 for holding the cache address of the data SRAM 110. In this table, as an example, the cache memory size is 128 kB,
On the other hand, when the capacity of the main memory is set in the range of 8 MB to 64 MB and the number of banks is 4, the set value of the tag address 118 in each of the valid and invalid states of the developed circuit is shown.
The symbols shown by D and V in the table have the following meanings.

D (Dirty bit): Indicates whether the data in the data SRAM 110 and the data in the DRAM 120 at the same address are the same.

V (valid bit): Indicates whether or not all the data in each line of the data SRAM 110 is valid.

These two bits contribute to the speeding up of memory access and the identity of memory data, and are made to be cached by enabling the developed circuit.
The capacity of the DRAM 102 can be reduced, and the dirty bit (D) or the valid bit (V) can be added to the tag address. By performing cache mapping on the non-interleaved DRAM 102, the memory can be reduced by reducing the number of cycles. In addition to speeding up the access, it is possible to realize further speeding up of the memory access and securing of data identity.

Table 1 shows a memory access target list for the states of the control signals of the cache control circuit according to the present development.

[0049]

[Table 1]

Table 2 shows a list of operation modes of the cache mapping control circuit according to the present development.

[0051]

[Table 2]

Table 3 shows a list of tag address set values of the cache control circuit according to the present development.

[0053]

[Table 3]

[0054]

As described above, according to the present invention, the following effects can be obtained.

(1) Depending on the type and configuration of the main memory DRAM, the cache memory is preferentially given to the main memory area having the low speed access configuration.
Since SRAM is allocated, a redundant circuit can be eliminated with respect to the access performance of the main memory, and high-speed access can be realized.

(2) By limiting the area of the main memory to be cached to the low speed area of the non-interleaved structure, it becomes possible to add D (dirty) and V (valid) information inside the tag SRAM, Above (1)
In addition to this, it is possible to further speed up access and ensure data identity.

(3) In order to lower the allocation order of the SRAM, which is the cache memory, to the part where the DRAM, which is the main memory, has a structure capable of high-speed access, the system is not loaded with more cache memory than necessary. It is possible to realize the miniaturization of.

(4) Furthermore, since the number of high-speed and expensive SRAM that is a cache memory is suppressed by the above (3), power saving and cost reduction can be performed.

[0059]

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus to which the present invention has been applied.

FIG. 2 is a detailed configuration diagram of a cache mapping control circuit that controls a main part of the cache control circuit according to the present development.

FIG. 3 is an address mapping diagram of a cache memory according to a first memory configuration of the cache control circuit according to the present development.

FIG. 4 is an address mapping diagram of a cache memory according to a second memory configuration of the cache control circuit according to the present development.

FIG. 5 is an address mapping diagram of a cache memory according to a fourth memory configuration of the cache control circuit according to the present development.

FIG. 6 is an operation timing chart of the cache control circuit according to the present development.

FIG. 7 is a schematic configuration diagram of a semiconductor memory device having a cache memory according to a conventional technique.

FIG. 8 is a timing chart showing an operation of a semiconductor memory device having a cache memory according to a conventional technique.

[Explanation of symbols]

101 ... CPU 102 ... CPU address 103 ... Cache control circuit unit 104 ... Cache mapping control circuit unit 105 ...
Mapping signal 106 ... Address comparison circuit section 107 ... Judgment signal 1 108 ... AND gate 109 ... Judgment signal 2 110 ... Data SRAM 111 ... Tag SRAM 112 ... CS1 signal 113 ... CS2 signal
114 ... NAND gate 1 115 ... NAND gate 2 116 ... CS1-N signal 117 ... CS2-N signal 118 ... Tag address
119 ... DRAM control circuit section 120 ... DRAM 121 ... DRAM control signal 201 ... Cache mapping register 202-207 ... AND gate 208-210 ... O
R gate 701 ... CPU 702 ... Cache control circuit 703 ... Tag section 704 ... Multiplexer 705 ... DRAM control circuit 706 ... Main memory section 707 ... DRAM section 707a to 707d ...
DRAM data bit plane part 707e ... Parity bit plane part 708 ... SRAM part 708a to 708d ... SRAM data bit plane part 709 ... ECC circuit part 710 ... CPU address 71
1 ... Way address 712 ... Cache hit signal 713
… Memory address 714… RAS-N / CAS-N signal 715… UCE flag 716… EF flag 717… Transfer control signal BT

Front page continuation (72) Inventor Kanichi Nagashima 810 Shimoimaizumi, Ebina City, Kanagawa Prefecture Hitachi Office Systems Division

Claims (2)

[Claims] 1. A main memory, which is a large-capacity, low-speed storage medium, and a cache memory that can be accessed faster than the main memory, and responds to a memory access request from a central processing unit or an external master unit. A method of controlling a cache memory of a memory control device for performing data transfer according to claim 1, wherein a high-speed memory access is realized by switching an address area targeted by the cache memory according to a type and a configuration of the main memory. And a cache memory control method. 2. By limiting the area of the main memory that is the target of the cache memory, it is possible to add information other than the cache address information, thereby realizing high-speed memory access and ensuring data identity. The cache memory control method according to claim 1, further comprising: