JPH0833869B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention selects a main storage device and one of data transfer requests connected to a plurality of channels in accordance with a predetermined priority order for data transfer. The present invention relates to a data processing device having an input / output processing device for performing and an input / output buffer device between the input / output processing device and a main storage device for temporarily holding transfer data of these devices.

[Conventional technology]

Conventionally, in this type of data processing device, as a method of selecting requests from a plurality of channels, a method of fixedly assigning priorities to channels according to a symbol has been generally used.

[Problems to be Solved by the Invention]

In the conventional method described above, when a request for a channel having the highest priority causes a delay for some reason (for example, a buffer is full or empty, contention with another device), another channel has a delay reason. There is a drawback that processing of all channels is delayed even if it is not necessary.

It is an object of the present invention to provide a data processing device which transfers data with a short waiting time when multiple channels are multiplexed.

[Means for Solving the Problems] In the data processing device of the present invention, the input / output buffer device includes an input data buffer and an output data buffer in a fixed area provided for each channel, and a read / write address of the main storage device. Address buffer with increment function to hold for each channel, prefetch data pointer with +1 increment function to indicate write address in each channel area of input data buffer and output data buffer, and input data buffer and output data buffer A reply data pointer with a +1 increment function that indicates a read address in the channel area, and a flag that identifies whether the operation is a data read operation from the main memory device or a data write operation to the main memory device. , Address buffer positive When a control stack having a flag for indicating a negative increment direction for each channel and a data read instruction from the main storage device are received, data is read from the output data buffer and output to the input / output processing device, and at the same time, the main storage device outputs the address buffer. When the address indicated by is written as a start address for one word and written in the output data buffer and a data write instruction to the main storage device is received, the write data from the input / output processing device is written to the input / output data buffer and then the main storage A control circuit that writes 1-word data read from the input data buffer to the device, using the address indicated by the address buffer as the start address, a data presence / absence display bit provided for each channel, a prefetch data pointer, and a reply data pointer Input and output data The data input / output processing device includes an input / output port for each channel and read data from the output data buffer. Output data register to hold and output to the I / O port of the channel, input data register to hold write data from I / O port to input data buffer, and access request to main memory from each I / O port Input the data presence / absence display bit, there is an access request,
In addition, a priority determination circuit that selects one channel from the channels whose data presence / absence display bits indicate that there is data, and an input data buffer that selects the channel selected by the priority determination circuit. , Control to output channel number to output data buffer, pyrifetch data pointer, reply data pointer, write data transfer start address to address buffer, set control stack flag, and output data write / read request to control circuit Contains the circuit.

[Action]

Since the presence / absence of data in the input / output data buffer is input as the information for determining the priority between the channels and the priority order of the data transfer is determined, the data transfer with a short waiting time becomes possible during the multiplexing operation of a plurality of channels.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data processing device which is an embodiment of the present invention.

This data processing device is connected to the main storage device 1 and eight channels (not shown), selects one of the data transfer requests from these channels in accordance with a predetermined priority order, and selects one of the main storage device 1 and the channel. An input / output processing device 3 for performing data transfer between the main memory device 1 and the input / output processing device 3, and an input / output buffer device 2 for temporarily storing transfer data in the input data buffer 21 or the output data buffer 22. It consists of

The input / output buffer device 2 includes an input data buffer 21 and
Output data buffer 22 and reply data pointer 23
A prefetch data pointer 24, a control stack 25, a control circuit 26, a data presence / absence determination circuit 27,
It is composed of a data presence / absence display bit group 28. The input / output processing device 3 includes an AND gate group 31, a control circuit 32,
An input data register 33, an output data register 34, input-output ports 35 _0, 35 _0, ..., and a 35 _7.

The input data buffer 21 is a buffer that holds write data from the input / output processing device 3 to the main storage device 1, and the output data buffer 22 is a buffer that stores read data from the main storage device 1 to the input / output processing device 3. Also, an area of 8 bytes × 4 words is assigned to one channel, and there are eight channels, and the channel number 26b is used to select which channel the area corresponding to is used. The address buffer 29 holds the address of the main memory 1 and is incremented by +8 or decremented by -8. The control stack 25 consists of 1 bit each for out 25 ₁ and plus 25 _{2. When} out 25 ₁ = “1”, the operation of reading data from the main memory device 1, out 25 ₁
Write operation to main memory 1 when = "0", plus 25 ₂
When = "1", the address of the address buffer 29 is incremented by 8 and
When plus 25 ₂ = “0”, it indicates that the address of the address buffer 29 is set to −8. Prefetch data pointer
24 is 2 bits and exists for each channel, and indicates which word is written in one channel of buffers 21 and 22,
It is incremented by 1 each time writing is performed. The reply data pointer 23 is 2 bits and exists for each channel.
It indicates which word is read from within one channel of 1,22, and is incremented by 1 every time reading is performed. The data presence / absence display bit group 28 is made up of 1 bit for each channel, and a total of 8 bits. Out 25 _{1 of} data presence / absence determination circuit 27 is "1"
At the time of the data read operation from the main memory 1, (prefetch data pointer 24-reply data pointer 23) is calculated, and if it is not zero, the bit corresponding to the channel of the data presence / absence display bit group 28 is set to "1". "I will. The control circuit 26 receives a prefetch data pointer 24 and a reply data pointer 23 according to an instruction from the input / output processing device 3.
Are both set to "00", and the address read from the address buffer 29 is sent to the main storage device 1 in response to the access request 26a to the main storage device 1 so that the data is read from the main storage device 1 or sent to the main storage device 1. Write data.

 Next, the inside of the input / output processing device 3 will be described.

Output ports 35 _0, 35 _1, ..., 35 ₇ corresponding to each channel has a data buffer of 8 bytes × 4 words therein. Input data register 33 is input / output port 35
Holding data from ₁ to 35 ₇ to the input data buffer 21. The output data register 34 holds the data from the output data buffer 22 to the input / output ports 35 _{0 to} 35 ₇ . AND gate group 31 is a data transfer request from the output port 35 _{0-35 7}
The logical product of 37 and the data presence / absence display bit group 28 is taken for each channel. The output of the AND gate group 31 of the priority determination circuit 36 is "1".
Channels are selected according to a predetermined priority. Control circuit
The numeral 32 outputs the channel number 26b of the channel selected by the priority judgment circuit 36 and the data transfer request 26a to the input / output buffer device 2.

 Next, the operation of this embodiment will be described.

The address is forward (continuous in the plus direction) in the output data transfer. First, the control circuit 32 of the input / output processing device 3 obtains a data address in the main memory device 1 (this is stored in advance in a control structure called a channel program in the main memory device 1), and the signal line 41. The data transfer start address is written to the address buffer 29 via the, and the control information of the data transfer to the control stack 25 (in this case, out 25 ₁ = “1”, plus 25 ₂ = “1”) is connected to the signal line 42. Writing is done and the pointers 23 and 24 are cleared to 0. These operations are always performed when starting data transfer,
The control circuit 26 requests the main memory 1 to read data. At this time, the contents of the address buffer 29 are read and used as the address. The read data is stored in the output data buffer 22, the pointer 24 is incremented by 1 and written back. As a result, the data presence / absence determination circuit 27 recognizes that the data is stored in the output data buffer 22, and stores the data presence / absence. The corresponding bit of the bit group 28 is set to "1". For a channel in which data is not stored in the output data buffer 22, the corresponding bit remains "0". Now, the data corresponding to channel 0 is still output data buffer 22
, The corresponding bit of the data presence / absence display bit group 28 is “0”, the data of channel 1 is stored in the output data buffer 22, and the corresponding bit of the data presence / absence display bit group 28 is “1”. The case where there is is explained.

When data transfer requests from channel 0 and channel 1 are simultaneously output from input / output ports 35 ₀ and 35 ₁ , channel 0 is always prioritized and processed unless the present invention is used. Since the required data is not yet present in the output data buffer 22, both channels 0 and 1 are kept waiting until the data arrives from the main memory 1. However, the data transfer request from the output O port 35 _{0-35 7} from the data storing the presence or absence bit group 28 according to the present invention is the AND by the AND gate group 31, if the case, the channel 0 The request is suppressed, and only the request from channel 1 passes and is input to the priority determination circuit 36. The priority determination circuit 36 determines that the request from channel 1 is the highest priority,
The channel number “1” and the data transfer request are notified to the control circuit 32. The control circuit 32 sends the request and the channel number “1” to the output data buffer 22, and the output data buffer 22
One cycle of data transfer is completed by reading out the necessary data from and returning the data to the input / output port 35 ₁ via the output data register 34. At this time, the reply data pointer 23 is incremented by 1 and written back. As a result, if the data of the channel 1 becomes empty in the output data buffer 22, the control circuit 26 instructs the reading of the next data, and the data is replenished.

The case of output data transfer has been described above. However, in the case of input data transfer, the corresponding bit of the data presence / absence display bit group 28 is set to "1" while the input data buffer 21 has a space, and data is input / output. input data register 33 from the port 35 _{0-35 7} is written through the input buffer 21 to the main storage unit 1.

〔The invention's effect〕

As described above, according to the present invention, by inputting the presence / absence of data in the input / output data buffer as the information for the priority determination between the channels, it is possible to perform the data transfer with less waiting time in the multiplex operation of the plurality of channels, and to improve the efficiency. The effect is that good data transfer can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of a data processing device showing an embodiment of the present invention. 1 ... Main storage device, 2 ... Input / output buffer device, 3 ...
Input / output processing device, 21 ... Input data buffer, 22 ... Output data buffer, 23 ... Reply data pointer, 24
...... Prefetch data pointer, 25 …… Control stack, 26 …… Control circuit, 26a …… Data transfer request, 2
6b ... Channel number, 27 ... Data presence / absence determination circuit, 28 ...
… Data presence / absence display bit group, 29 …… Address buffer,
31 …… And gate group, 32 …… Control circuit, 33 …… Input data register, 34 …… Output data register, 35 _{0 to} 35 ₇ …
... I / O port, 36 ... Priority determination circuit, 37 ... Data transfer request, 41, 42 ... Signal line.

Claims (1)

[Claims] 1. A main storage device, an input / output processing device which is connected to a plurality of channels and selects one of data transfer requests from the channels in accordance with a predetermined priority order and transfers the data, and the input / output processing device. And an input / output buffer device for temporarily holding transfer data of these devices between the main storage device and the main storage device, wherein the input / output buffer device is a fixed area provided for each channel. Input data buffer and output data buffer, address buffer with increment function that holds read / write address of main memory for each channel, and write address in each channel area of input data buffer and output data buffer, +1 Prefetch data pointer with increment function, input data buffer and Reply data pointer with +1 increment function, which indicates the read address in each channel area of the output data buffer, and whether the operation is to read data from the main memory or write data to the main memory. Control stack having, for each channel, a flag for identifying the address buffer and a flag for instructing the positive and negative increment directions of the address buffer, and when a data read instruction is received from the main storage device, the data is read from the output data buffer to the input / output processing device. When the data is output, one word is read from the main memory using the address indicated by the address buffer as the start address and written to the output data buffer, and when the data write instruction to the main memory is received, the write data from the input / output processor is changed to the input / output data. After writing to the buffer, main memory A control circuit that writes 1-word data read from the input data buffer using the address indicated by the address buffer as the start address, a data presence / absence display bit provided for each channel, a prefetch data pointer, and a reply data pointer are input. And a data presence / absence determination circuit that turns on the data presence / absence display bit of the channel if the output data buffer stores data, the input / output processing device includes an input / output port for each channel, and an output data buffer. The output data register that holds the read data from the I / O port and outputs it to the input / output port of the channel, the input data register that holds the write data from the I / O port to the input data buffer, and the main memory device from each I / O port Enter the access request to the Access request, and the data presence / absence display bit indicates that there is data. A priority determination circuit that selects one channel according to a predetermined priority order, and a channel that is selected by the priority determination circuit. To
Sends channel number to input data buffer, output data buffer, prefetch data pointer, reply data pointer, writes data transfer start address to address buffer, sets control stack flag, and outputs data write / read request to control circuit Data processing apparatus including a control circuit for performing the data processing.