JPH08274745A - Demodulation device - Google Patents

Abstract

PURPOSE: To provide a demodulation device which can correctly regenerate a time window signal for DFT essential to demodulate a transmitted signal of an OFDM system. CONSTITUTION: A time window signal adjusting circuit 30 generates a time window adjustment signal W showing the timing wherein a time window signal is generated by, for example, the number of frames from the head of a transmitted frame based on a numeral WINDOW showing the number of symbols at the part by excluding a guard interval from the frame of the transmitted signal, i.e., the length of the time window signal, a numeral Guard showing the length of the guard interval of the frame of the transmitted signal, a numeral (k) showing steps of adjustment of the timing of the time window signal by the time window signal adjusting circuit 30, symbols I' and Q' for regeneration which are inputted from a specific frequency component extracting circuit 250, and supplies the generated time window adjustment signal to a time window signal generating circuit 252.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an Orthogonal Frequency Division Multiplex (OFDM) system.
xing) demodulating device for demodulating a signal.

[0002]

2. Description of the Related Art When transmitting digital data,
A phase modulation method (PSK) in which the phase of one carrier signal corresponds to the value of transmission data to be transmitted, or
A quadrature modulation method (QAM) has been generally used in which a phase and an amplitude correspond to values of transmission data. These systems are sometimes called single carrier modulation systems because they use a single carrier signal.

In contrast to this single carrier system, a multicarrier modulation system such as an orthogonal frequency multiplexing (OFDM) system for transmitting digital data using carrier signals of a plurality of frequencies has come to be used. OF
In the DM method, since the transmission band is divided using a large number of carrier signals, the band per carrier is narrowed and the modulation speed becomes slow. However, since there are a large number of carriers, the overall transmission speed is the same as in the QAM system where the same bandwidth is used. On the other hand, since a large number of carrier signals are transmitted in parallel, the symbol speed becomes slower and the symbol length The time length of multipath can be relatively shortened.
Therefore, when applied to terrestrial data transmission where multipath interference is likely to occur, it is expected that the effects of multipath interference can be reduced.

Further, in the OFDM system, a discrete Fourier inverse transform (IDFT) is used to generate a transmission signal, and a discrete Fourier transform (DF) is used to demodulate the transmission signal.
T) is used. With the recent development of semiconductor elements, it has become possible to perform these conversion processes at high speed by hardware, and it has become extremely easy to realize an apparatus used for OFDM data transmission. In addition to the above-mentioned excellent characteristics, this point is one of the reasons why the OFDM system has been receiving attention in the communication field in recent years.

[0005]

In order to receive and correctly demodulate an OFDM transmission signal, it is necessary to establish synchronization of various signals on the receiving side and the transmitting side. That is,
A clock signal used when performing IDFT processing on the transmitting side and a clock signal performing DFT processing on the receiving side; and a carrier signal used for quadrature modulating the signal after IDFT processing on the transmitting side, It is necessary to synchronize with a carrier signal used for converting a transmission signal received by the receiving side into a baseband signal, and further, a time window signal used for DFT processing on the receiving side is transmitted to the IDFT on the transmitting side.
It is necessary to reproduce in time with the timing window signal used for processing.

Conventionally, in order to reproduce a time window signal used for DFT on the receiving side, a synchronizing symbol having an amplitude of 0 (no signal) is provided at the beginning of a frame of a transmission signal on the transmitting side, and this synchronizing symbol is used. The carrier wave signal, the clock signal, and the time window signal for DFT are detected and detected by a PLL circuit or the like.

However, when a transmission signal is transmitted through a transmission line in which multipath interference or the like has occurred, signal components of adjacent symbols leak to the synchronization symbols or noise is mixed into the synchronization symbols. As a result, it may be difficult to detect the sync symbol, and the time window signal for DFT may not be reproduced correctly. Further, when the time window signal for DFT is generated using the PLL circuit, it is better to lengthen the period of the synchronization symbol from the viewpoint of the stability of the operation of the PLL circuit. On the other hand, from the viewpoint of data transmission efficiency, it is desirable to shorten the period of synchronization symbols that cannot be used for effective data transmission as much as possible.

The present invention has been made in view of the above-mentioned problems of the prior art. Even when a transmission signal is transmitted through a transmission line in which multipath interference, noise or the like occurs, OFDM is used. An object of the present invention is to provide a demodulation device capable of correctly reproducing a time window signal for DFT, which is indispensable for demodulating a transmission signal of a standard system. Further, according to the present invention, the data transmission efficiency can be improved by synchronizing the DFT time window signal by using the originally existing specific frequency component without providing a synchronization pattern (no signal portion) in the transmission signal other than the specific frequency component. It is an object of the present invention to provide a demodulation device that can correctly reproduce a time window signal for DFT without reducing the noise. It is another object of the present invention to provide a demodulation device capable of demodulating an OFDM transmission signal with a low error rate by correctly reproducing a DFT time window signal.

[0009]

In order to achieve the above object, a demodulation device according to the present invention includes a predetermined frequency having two or more orthogonal signal components including one or more specific frequency components having an amplitude of zero. A demodulator for demodulating a time domain signal whose domain data is inversely Fourier transformed, wherein the time domain signal is Fourier transformed using a predetermined time window signal, and a Fourier transform unit for demodulating the frequency domain data, and Amplitude data calculating means for calculating amplitude data indicating the amplitude of all or part of specific frequency components of frequency domain data, and the time of the Fourier transforming means by adjusting the timing so that the value of the amplitude data becomes small. And a time window signal generating means for generating a window signal.

The time window signal generating means compares the signal generating means for generating the time window signal with a value of the amplitude data corresponding to all or part of the specific frequency component and a predetermined threshold value. And a timing adjustment for adjusting the timing at which the signal generating means generates the time window signal when the value of the amplitude data corresponding to all or part of the specific frequency component exceeds the predetermined threshold value. And means. Preferably, the time window signal generation means is a signal generation means for generating the time window signal, a value of the amplitude data corresponding to all or a part of the specific frequency component, and a range of values of the amplitude data. And a signal generating means for comparing the amplitude data corresponding to all or a part of the specific frequency component with a value outside the range indicated by the predetermined threshold value. And timing adjusting means for adjusting the timing of generating the time window signal.

[0011]

The demodulator according to the present invention includes a time domain signal obtained by inverse Fourier transforming predetermined frequency domain data having two or more orthogonal signal components including one or more specific frequency components whose amplitude is always 0. That is, the OFDM transmission signal is demodulated. In the demodulation device according to the present invention, the Fourier transform means uses the predetermined time window signal, that is, the time window signal generated by the time window signal generation means described later to perform OFDM.
The transmission signal of the system is cut out, the time domain signal is Fourier transformed, and two orthogonal signal components of the frequency domain data are demodulated.

The amplitude data calculation means is amplitude data indicating the amplitude of all or part of the specific frequency component of the frequency domain data, for example, the absolute value or square value of the symbol corresponding to each specific frequency component included in the decoded signal. To calculate. The time window signal generation means is arranged so that the value of the amplitude data calculated by the amplitude data calculation means becomes small, that is,
The amplitude of the specific frequency component demodulated by the Fourier transform means is
The time window signal is generated by adjusting the timing so that it is closest to the original amplitude value of 0, and is supplied to the Fourier transform means.

[0013]

First Embodiment A first embodiment of the present invention will be described below.
FIG. 1 is a diagram showing a configuration of an OFDM transmitter 6 that transmits an OFDM transmission signal in which the amplitude of a specific frequency component is set to zero. As shown in FIG. 1, the OFDM transmitter 6
Is composed of an orthogonal frequency multiplexing circuit 60, an orthogonal modulation circuit 140, and a transmission circuit 130. The orthogonal frequency multiplexing circuit 60 includes a memory circuit (MEM) 104, a multiplexing circuit (MUX) 106, and a serial / parallel conversion circuit ( S /
P circuits) 108 ₁ and 108 ₂ , discrete Fourier inverse transform circuit (IDFT circuit) 110, parallel / serial conversion circuits (P / S circuits) 112 ₁ and 112 ₂ , buffer memories (BM) 114 ₁ and 114 ₂ and digital / Analog conversion circuit (D / A circuit) 116 ₁ and 116 ₂ and transmission data to be transmitted (I component data and Q
Component data; frequency domain data according to the present invention) is subjected to orthogonal frequency multiplexing (OFDM) and transmitted as a transmission signal TXS to a wireless communication line.

In the orthogonal frequency multiplexing circuit 60, the memory circuit 104 stores the data of the synchronization symbol and the reference symbol for setting the amplitude of the signal component (specific frequency component) of one or more specific frequencies of the transmission signal TXS to 0. It is stored and output to the multiplexing circuit 106. Multiplexing circuit 106
Is controlled by a predetermined control circuit (not shown), and the I-symbol data and the Q-component data input in a serial format have a constant interval, for example, a synchronization symbol input from the memory circuit 104 every few symbols. Are time-division multiplexed and inserted, and S / P circuits 108 ₁ and 108 ₂ are respectively inserted.
Output to

The S / P circuits 108 ₁ and 108 ₂ respectively convert the I component data and the Q component data in which the reproduction symbols and the like are inserted into parallel format data, and output it to the IDFT circuit 110. The IDFT circuit 110 is S
The data input from the / P circuits 108 ₁ and 108 ₂ are subjected to inverse discrete Fourier transform (IDFT), converted into time domain signals, and output to the buffer memories 114 ₁ and 114 ₂ .

The buffer memories 114 ₁ and 114 ₂ are I
Data corresponding to a so-called guard interval is added to the data input from the DFT circuit 110 and output to the D / A circuits 116 ₁ and 116 ₂ . D / A circuit 1
16 ₁ , 116 ₂ are buffer memories 114 ₁ , 114
_The data input from ₂ is converted into an analog signal and output to the quadrature modulation circuit 140.

The quadrature modulation circuit 140 includes a D / A circuit 116.
₁, 116₂Filter the signal input from
Generates a baseband signal (baseband signal) and generates a carrier signal
Is used for quadrature modulation to transmit the transmission circuit 130 and the transmission antenna.
Output to the wireless communication line via the wireless LAN 138. What
In the OFDM transmitter 6, the memory circuit 104
D / A circuit 116 ₁, 116₂Each component up to
It operates in synchronization with a predetermined clock signal, and this clock
Clock signal and a carrier signal used in the quadrature modulation circuit 140
Is in sync with.

FIG. 2 relates to the present invention in the first embodiment.
Of the OFDM receiver 8 to which the demodulator 80 is applied
FIG. As shown in FIG. 2, an OFDM receiver
Reference numeral 8 is a receiving circuit 20, a quadrature detection circuit 22, and a demodulation device.
The demodulator 80 is an analog / digital converter.
Digital conversion circuit (A / D circuit) 228₁, 22
8₂, Serial / parallel conversion circuit (S / P circuit) 23
0₁, 230₂, Discrete Fourier transform circuit (DFT times
) 232, parallel / serial conversion circuit (P / S times
Road) 234₁, 234₂, Clock generation circuit 236, carrying
Transmission frequency control circuit (CR) 238, clock frequency control
Control circuit (BTR) 240, data correction circuit (CMP) 2
42, buffer memory 244 ₁, 244₂And reference
Symbol detection circuit (Detec) 246, specific frequency component
Extraction circuit (EX) 250, time window signal generation circuit 252
And a time window signal conditioning circuit (WG) 30.
For the configuration of the time window signal adjusting circuit 30, refer to FIG.
See below. These components allow the OFDM receiver
The device 8 is connected to the wireless communication line from the OFDM transmitter 6, for example.
OFDM transmission signal TXS transmitted via
Received and transmitted data (I component data and Q component data
Demodulation).

The receiving circuit 20 receives the transmission signal TXS via the receiving antenna 200 and outputs it to the quadrature detection circuit 22. The quadrature detection circuit 22 reproduces a carrier signal under the control of the carrier frequency control circuit 238, performs quadrature detection of the transmission signal TXS using the reproduced carrier signal, generates a baseband signal, and outputs the baseband signal to the demodulator 80. .

In the demodulation circuit 80, the A / D circuit 228
Reference numerals ₁ and 228 ₂ respectively convert the base band signal into a serial format digital signal in synchronization with the clock signal input from the clock generation circuit 236, and the S / P
It outputs to the circuits 230 ₁ and 230 ₂ . The S / P circuits 230 ₁ and 230 ₂ are respectively the A / D circuits 228 ₁ and
The signal input from 228 ₂ is converted into a parallel format signal and output to the DFT circuit 232.

The DFT circuit 232 uses the time window signal W input from the time window signal adjusting circuit 30 to output the S / P circuit 2
The signals input from 30 ₁ and 230 ₂ are cut out, subjected to discrete Fourier transform (DFT), and converted into the frequency domain to demodulate transmission data (I component data and Q component data), and the P / S circuit 234 ₁ , 234 ₂ . The P / S circuits 234 ₁ and 234 ₂ are DFTs, respectively.
The signal input from the circuit 232 is converted into a serial format, and as a demodulation signal, the specific frequency component extraction circuit 250, the carrier frequency control circuit 238, the clock frequency control circuit 2
40, the data correction circuit 242, and the reference symbol detection circuit 246.

The reference symbol detection circuit 246 receives the OFD signals from the P / S circuits 234 ₁ and 234 _2.
The reference symbol inserted on the M transmitter 6 side is detected and output to the data correction circuit 242. The specific frequency component extraction circuit 250 extracts each of the reproduction symbols I ′ and Q ′ corresponding to one or more specific frequency components included in the transmission signal from the demodulated signal and outputs them to the time window signal adjustment circuit 30. To do.

The data correction circuit 242 determines the position of the symbol of the transmission data input from the P / S circuits 234 ₁ and 234 _{2 in} the signal plane based on the value of the reference symbol input from the reference symbol detection circuit 246. By correcting, the influence of the transmission signal TXS on the wireless communication line is removed, the transmission data including the data corresponding to the guard interval is decoded, and the decoded data is output to the buffer memories 244 ₁ and 244 ₂ respectively. . The buffer memories 244 ₁ and 244 ₂ remove the data corresponding to the guard interval from the decoded data input from the data correction circuit 242 and output it.

The carrier frequency control circuit 238 is, for example, a Costas loop circuit, and the carrier signal generated by the carrier signal generation circuit 220 and the P / S circuits 234 ₁ and 234 _2.
The carrier wave signal generation circuit 22 detects the phase error of the symbol included in the specific carrier wave signal of the signals input from
Control 0 to match the phase of these signals. The clock frequency control circuit 240 is, for example, a Costas loop circuit, and is a symbol included in a specific carrier signal among the carrier signals generated by the clock generation circuit 236 and the signals input from the P / S circuits 234 ₁ and 234 _2. Of the signal is detected and the clock generation circuit 236 is controlled to match the phases of these signals.

FIG. 3 is a diagram showing the configuration of the time window signal adjustment circuit 30 of the demodulation circuit 80 according to the present invention shown in FIG. As shown in FIG. 3, the time window signal adjustment circuit 30 includes multiplication circuits 300 ₁ and 300 ₂ and addition circuits 306 and 314.
322, subtraction circuits 310 and 312, buffer circuit (BU
FF) 302, comparison circuit 304, counter circuit (CNT)
R) 308, 318 and selection circuit (MUX) 316.
320, which is the number of symbols in the portion of the transmission signal frame excluding the guard interval, that is, the number Window that indicates the length of the time window signal, and the number Guard that indicates the length of the guard interval of the transmission signal frame.
A numerical value k (k is an integer) indicating a step of adjusting the timing of the time window signal by the time window signal adjusting circuit 30, the reproduction symbol I ′ input from the specific frequency component extracting circuit 250,
Q ', and a clock generation circuit 236 generates, based on the clock signal of the same period as the symbol of the transmission signal,
The timing of generating the time window signal is generated, for example, by generating a time window adjustment signal W indicated by the number of frames from the beginning of the transmission frame and supplying the time window signal generation circuit 252.

The multiplication circuits 300 ₁ and 300 ₂ square the reproduction symbols I ′ and Q ′ input from the specific frequency component extraction circuit 250, respectively, and output them to the addition circuit 322. The adder circuit 322 includes the multiplier circuits 300 ₁ and 300.
₂ The square values of the reproduction symbols I ′ and Q ′ input from each of them are added, and the buffer circuit 302 is added as amplitude data.
And to the comparison circuit 304.

The buffer circuit 302 adds the adder circuit 322 only when the load signal LD of the comparator circuit 304 is activated.
The output signal of is stored. As described below, the comparison circuit 304
The load signal LD is activated only when the amplitude data has become the minimum by then, so the amplitude data stored in the buffer circuit 302 becomes the minimum. Comparison circuit 304
Is the amplitude data of the latest signal frame and the buffer circuit 3
02, the load signal LD is activated if the value of the amplitude data of the latest signal frame is less than the value of the amplitude data stored in the buffer circuit 302, and otherwise. Outputs the load signal LD to the load signal input terminal of the counter circuit 318 while keeping it inactive.

The adding circuit 306 indicates the time length of the time window signal supplied to the DFT circuit 232 by a numerical value Wi indicating the number of periods of the clock signal generated by the clock generating circuit 236, for example.
and the numerical value Guard that similarly indicates the time length of the guard interval of the transmission signal are added to generate frame length data and the subtraction circuits 310 and 312 and the selection circuit 320 are generated.
And to the adder circuit 314. The counter circuit 308 subtracts the frame length data input from the adder circuit 306 for each cycle of the clock signal, that is, for each symbol, activates the enable signal when the count value becomes 0, and in other cases. Keep the enable signal inactive and the counter circuit 318 and the selection circuit 316
Output to That is, each time the counter circuit 308 counts the clock signal by the number of symbols included in one frame, the enable signal of the counter circuit 308 is activated. The count value of the counter circuit 308 indicates, in symbol units, the position of the symbol currently received from the beginning of the frame.

The subtraction circuit 310 subtracts the count value of the counter circuit 308 from the frame length data to obtain the counter circuit 3
Output to 18. The subtraction circuit 312 is the addition circuit 3
The numerical value k is subtracted from the frame length data input from 06, and the value of the frame length data −k is output to the selection circuit 316. The adder circuit 314 adds the frame length data input from the adder circuit 306 and the numerical value k, and outputs the value of the frame length data + k to the selection circuit 316. The selection circuit 316 receives the frame length data -k when the enable signal from the counter circuit 308 is activated.
Value of frame length data + k is selected and output to the multiplexing circuit 320 when the value of frame length data + k is selected.

The counter circuit 318 is provided for the subtraction circuit 3 when the load signal input from the comparison circuit 304 is activated.
A value obtained by subtracting the count value of the counter circuit 308 from the frame length data input from 10 is loaded, the loaded value is subtracted for each cycle of the clock signal, and when the count value becomes 0, the enable signal is activated. Select circuit 320
Output to The count value of the counter circuit 318 indicates the distance from the end of the frame to the minimum value.

The selection circuit 320 selects the frame length data -k or the frame length data + k output by the selection circuit 316 when the enable signal input from the counter circuit 318 is activated, and in other cases. The frame length data input from the adder circuit 306 is set in the time window signal generation circuit 252 as the time window adjustment signal W. In this way, the selector circuit 320 is controlled such that the timing when the count value of the counter circuit 318 becomes 0 is the timing when the time window signal can be correctly synchronized, and the time window adjustment signal W is set to the frame length data at this timing. This is because they must be equal. The time window signal generation circuit 252 generates a time window signal at the timing indicated by the time window adjustment signal W, and supplies the time window signal to the DFT circuit 232.

Hereinafter, the OFDM transmitter 6 and the OFDM transmitter
The operation of the data transmission system using the receiving device 8 will be described. The transmission data (I component data and Q component data) input to the OFDM transmission device 6 has reference symbols inserted by the memory circuit 104 and the multiplexing circuit 106, and S /
The P circuits 108 ₁ and 108 ₂ , the IDFT circuit 110 and the P / S circuits 112 ₁ and 112 ₂ are converted into the time domain, the buffer memories 114 ₁ and 114 ₂ insert guard intervals, and the buffer memories 114 ₁ and 11 are inserted.
4 ₂ and the quadrature modulation circuit 140 perform quadrature modulation to form a transmission signal TXS, which is transmitted by the transmission circuit 130 to the wireless communication line.

The transmission signal TXS transmitted from the OFDM transmitter 6 via the wireless communication line is received by the receiver circuit 20 in the OFDM receiver 8, quadrature detected by the quadrature detection circuit 22, and the A / D circuit 228. ₁ , 2
28 ₂ and S / P circuits 230 ₁ and 230 ₂ through D
It is input to the FT circuit 232. Time window signal generation circuit 25
A time window signal is generated at the timing indicated by the time window adjustment signal W input from the DFT circuit 232. The DFT circuit 232 and the P / S circuits 234 ₁ and 234 ₂ perform DFT using the time window signal and generate a demodulated signal.

The specific frequency component extraction circuit 250 extracts the reproduction symbols I'and Q'from the demodulated signal and outputs them to the time window signal adjustment circuit 30.
Generates the time window adjustment signal W so that the amplitudes of the reproduction symbols I ′ and Q ′ are minimized, and the time window signal generation circuit 25
Set to 2. When the time window adjustment signal W is updated, the frame length period (Window + Guard-
k) At the time of performing the processing, and thereafter, the period from the end of the frame to the position where the minimum value is detected (Windo
(w + Guard + k) processing is performed, and thereafter, the processing is updated for each frame length (Window + Guard). Further, the reference symbol detection circuit 246 detects the reference symbol from the demodulated signal, and the data correction circuit 242.
Corrects the demodulated signal based on the detected reference symbol, decodes it, and outputs the decoded signal to the buffer memories 244 ₁ and 244 ₂ . Buffer memory 244 _1, 244 _2, removes the guard interval from the demodulated signal, and outputs only the transmission data.

The carrier frequency control circuit 238 and the clock frequency control circuit 240 respectively include a symbol of a specific carrier signal included in the demodulated signal, a carrier signal generated in the quadrature detection circuit 22, and a clock generated by the clock generation circuit 236. The phase error of the signal is detected, the quadrature detection circuit 22 and the clock generation circuit 236 are controlled based on the detected phase error, and the carrier wave signal and the clock signal on the OFDM transmitter 6 side and the OFDM receiver 8
Establish phase synchronization with the carrier and clock signals on the side.

As described above, the time window signal adjusting circuit 30 of the demodulator 80 according to the present invention is used for reproduction corresponding to the amplitude of the specific frequency component contained in the received transmission signal and originally supposed to have an amplitude of 0. Since the timing of the time window signal used by the DFT circuit 232 is adjusted so that the values of the symbols I ′ and Q ′ are minimized, the timing of the time window signal is optimized. Therefore, the demodulation device 80 can accurately demodulate the transmission signal, and the error rate of the data obtained as a result of the demodulation is low. Further, the time window signal adjusting circuit 30 of the demodulator 80 always adaptively adjusts to D according to the state of the transmission path.
Since the timing of the time window signal used by the FT circuit 232 is adjusted, the timing of generation of the time window signal can always be kept optimal even if the state of the transmission path changes.
In the time window signal adjustment circuit 30, the multiplication circuit 30
Instead of 0 ₁ , 300 ₂ and the addition circuit 322, a circuit for calculating the sum of the absolute values of the reproduction symbols I ′, Q ′ may be used.

[0037]

[Second Embodiment] A second embodiment of the present invention will be described below.
FIG. 4 shows that when the transmission signal includes a plurality of specific frequency components,
FIG. 4 is a diagram showing a configuration of a square sum calculation circuit 34 used in place of the multiplication circuits 300 ₁ and 300 ₂ and the addition circuit 322 shown in FIG. 3. The specific frequency component extraction circuit 250
Reproducing symbols I ₁ corresponding to each specific frequency component included more in the demodulated signal _{', Q 1' ~I n '} , Q n'
When (n is an integer) is extracted and modified so as to be output to the time window signal adjusting circuit 30 (FIGS. 2 and 3) in parallel, the multiplication of the time window signal adjusting circuit 30 shown in FIG. The circuits 300 ₁ and 300 ₂ and the addition circuit 322 are
By replacing the sum of squares calculation circuit 34, the time window adjustment signal W can be generated.

As shown in FIG. 4, the sum of squares calculation circuit 34
Are the specific frequency component extractions modified as described above.
Reproduction symbol I input in parallel from the output circuit 250
₁’、 Q₁’～ I_n’、 Q_n’Calculate each sum of squares
Multiplication circuit 340₁₁, 340 ₁₂~ 340_n1, 340_n2
And adder circuit 342₁~ 342_nAnd the addition circuit 342
₁~ 342_nCalculate the sum of the sum of squares calculated by each
It is composed of an adder circuit 344. That is, for playback
Symbol multiplication circuit 340₁₁, 340₁₂~ 340_n1, 34
0_n2Corresponding to each, the multiplication circuit 30 shown in FIG.
0₁, 300₂And the same circuit as the buffer circuit 302
It has a configuration provided.

The sum of the square sums of the reproduction symbols I ₁ ', Q ₁ ' -I _n ', Q _n ' calculated by the adder circuit 344 is supplied to the buffer circuit 302 and the comparison circuit 304 of the time window signal adjusting circuit 30. by entering Te, the time window signal conditioning circuit 30 is reproduced symbol I ₁ corresponding to each of a plurality of specific frequency component _{', Q 1' ~I n '} , Q n'
The time window adjustment signal W can be generated based on the above, and can be supplied to the time window signal generation circuit 252, and the timing of the time window signal supplied to the DFT circuit 232 can be further optimized. Square sum calculation circuit 34 shown in the second embodiment.
Also, as in the first embodiment, the reproduction symbol I ₁ ′,
Q ₁ '~I _n', may be configured to calculate the sum of the absolute value of Q _n ', respectively.

[0040]

Third Embodiment A third embodiment of the present invention will be described below.
5 is between the adder circuit 322 and the buffer circuit 302 and the comparison circuit 304 of the time window signal adjustment circuit 30 shown in FIG. 3, or the square sum calculation circuit 34 and the buffer circuit 302 and the comparison circuit shown in FIG. FIG. 4 is a diagram showing a configuration of a filter circuit 36 which is inserted between the filter circuit 304 and the filter 304.

As shown in FIG. 5, the filter circuit 36 includes
Register circuit 360₁~ 360_mA constant composed of
Period, for example, one symbol period (shown in FIGS. 2 and 3
(Same as the cycle of the clock signal of the time window signal adjustment circuit 30)
For each time, the addition times of the time window signal adjustment circuit 30 shown in FIG.
Path 322 or addition circuit 344 of sum of squares calculation circuit 34
A shift register for shifting the added value and a filter circuit 3
6 input signal and register circuit 360₁~ 360_mof
Filtering coefficient A for each output signal₁~ A_{m + 1}
Multiplication circuit 362 for multiplying by₁~ 362_{m + 1}, Multiplication circuit 3
62₁~ 362 _{m + 1}Addition times to calculate the sum of multiplication results of
A predetermined value is added to the sum calculated by the path 364 and the adder circuit 364.
It is composed of a multiplication circuit 366 for multiplying the coefficient B,
Operates as a transversal filter circuit.

As described above, by filtering the output of the adder circuit 322 of the time window signal adjustment circuit 30 or the sum of squares calculation circuit 34 by the filter circuit 36, noise generated in the transmission signal on the transmission line is reduced to the time window signal. The influence of other components of the adjustment circuit 30 on the generation of the time window adjustment signal W can be reduced.

The number of stages of the filter circuit 36, that is,
The number of register circuits 360 _{1 to} 360 _{m + 1} is preferably equal to or less than the number of symbols included in the guard interval (k ≧ m). The position where the values of the reproduction symbols I ′ and Q ′ are minimum is the register circuit 360 of the filter circuit 36.
_This is because all of _{1 to} 360 _m are the case where the reproduction symbol of the guard interval is held. On the other hand, the smaller the number of stages of the filter circuit 36, the wider the range in which the output signal of the filter circuit 36 becomes the minimum and the larger the error. Therefore, after all, it is optimal to set the number of stages of the filter circuit 36 to be the same as the number of symbols included in the guard interval (k = m). Further, the values of the filtering coefficients A _{1 to} Am _{+ 1} and the coefficient B are arbitrary, and may be set to optimum values for the transmission path of the OFDM receiver 8 to which the filter circuit 36 is applied and the like by experiments or the like.

In addition to using a transversal filter like the filter circuit 36 shown in the third embodiment, in order to filter the output data of the adder circuit 322 or the sum of squares calculation circuit 34, for example, another format is used. It is also possible to adopt a method using a digital filter, or a method of once returning to analog format data and then filtering with an analog filter.

[0045]

[Fourth Embodiment] A fourth embodiment of the present invention will be described below.
FIG. 6 is a diagram showing the configuration of the time window signal adjusting circuit 40 according to the present invention in the fourth embodiment. 6, the same components as those of the time window signal adjusting circuit 30 shown in FIG. 3 are designated by the same reference numerals. As shown in FIG. 6, the time window signal adjustment circuit 40 is used for the OFDM receiver 8
2 is used instead of the time window signal adjustment circuit 30 (FIGS. 2 and 3), and includes a buffer circuit 302 and a comparison circuit 3 of the time window signal adjustment circuit 30.
04 is replaced with a load signal generation circuit 400 including a comparison circuit 402, a buffer circuit 404, a comparison circuit 406, and an OR circuit 408.

The multiplication circuits 300 ₁ and 300 ₂ and the addition circuit 322 calculate the sum of squares of the reproduction symbols I ′ and Q ′, and the sum of squares is input to the load signal generation circuit 400. In the load signal generation circuit 400, the comparison circuit 402 has the reproduction symbols I ′ and Q ′ output from the addition circuit 322.
The sum of squares of the reproduction symbols I ′ and Q ′ output from the adder circuit 322 is compared with the threshold TH1.
When it is H1 or more, the comparison result is set to the logical value 1, and in other cases, it is set to the logical value 0 and output to the buffer circuit 404.

The buffer circuit 404 sequentially stores the comparison result of the comparison circuit 402 for each cycle of the clock signal. That is, the buffer circuit 404 stores the comparison result of the cycle of the immediately preceding clock signal.
The comparison circuit 406 compares the sum of squares of the reproduction symbols I ′ and Q ′ with the threshold TH2, and compares when the sum of squares of the reproduction symbols I ′ and Q ′ output from the addition circuit 322 is less than the threshold TH1. The result is set to a logical value 1, and otherwise set to a logical value 0 and output to the logical sum circuit 408. The buffer circuit 404 stores the comparison result input from the comparison circuit 402 and outputs it to the OR circuit 408.

The OR circuit 408 is the buffer circuit 404.
When the logical value of the output signal of the comparison circuit 406 becomes 1, the load signal LD is activated (logical value 1) and output to the counter circuit 318. When the load signal LD is activated, the subtractor circuit 31 is added to the counter circuit 318.
The value of the data output by 0 is loaded. Since the values of the reproduction symbols I ′ and Q ′ of the specific frequency component fluctuate in a constant pattern, the time window adjustment signal W is updated at the timing when the sum of squares of the reproduction symbols I ′ and Q ′ in this fluctuation pattern is the minimum. It is desirable to do.

Therefore, the value of the threshold TH2 is greater than or equal to the minimum value of the sum of squares of the reproduced symbols I'and Q'of the specific frequency component, and the sum of squares of the reproduced symbols I'and Q'in each frame. The threshold TH1 is set to a value that is not less than the minimum value of the sum of squares of the reproduced symbols I ′ and Q ′ of the specific frequency component and is close to the minimum value, and the sum of squares of the reproduced symbols I ′ and Q ′ is set. Value is less than or equal to the threshold value TH2, once becomes less than or equal to the threshold value TH1 and again exceeds the threshold value TH1, and the time window adjustment is performed at the timing at which the sum of squares of the reproduced symbols I ′ and Q ′ becomes the minimum. The signal W is updated.

The specific frequency component extraction circuit 250 may be modified appropriately so that the time window signal adjustment circuit 40 uses the square sum calculation circuit 34 instead of the multiplication circuits 300 ₁ and 300 ₂ and the addition circuit 322, or It is also possible to use a circuit that calculates the sum of absolute values. Further, a filter circuit 36 (FIG. 5) may be added after the addition circuit 322 or the sum of squares calculation circuit 34.

[0051]

[Fifth Embodiment] A fifth embodiment of the present invention will be described below.
FIG. 7 is a diagram showing the configuration of the time window signal adjustment circuit 42 according to the present invention in the fifth embodiment. In FIG. 7, the time window signal adjusting circuit 3 shown in FIGS.
The same components as 0 and 40 are designated by the same reference numerals. As shown in FIG. 7, the time window signal adjustment circuit 42 is
The OFDM receiver 8 (FIG. 2) is used in place of the time window signal adjustment circuit 30 (FIGS. 2 and 3) and includes a comparison circuit 422 in the time window signal adjustment circuit 30.
And a load signal generation circuit 420 including an OR circuit 424 is added so that the counter circuit 318 loads the value of the data output from the addition circuit 306 when the load signal from the load signal generation circuit 420 is activated. It has a structure that

The multiplication circuits 300 ₁ and 300 ₂ and the addition circuit 322 calculate the sum of squares of the reproduction symbols I ′ and Q ′, and the sum of squares is input to the load signal generation circuit 400. In the load signal generation circuit 420, the comparison circuit 402 causes the reproduction symbols I ′ and Q ′ output from the addition circuit 322.
The sum of squares of the reproducing symbols I ′ and Q ′ output from the adding circuit 322 is compared with the threshold TH.
In the above cases, the comparison result is set to the logical value 1, and in other cases, it is set to the logical value 0 and output to the logical sum circuit 424. The OR circuit 424 loads the counter circuit 308 when the count value of the counter circuit 308 becomes 0, the enable signal is activated (logical value 1), and the logical value of the comparison result of the comparison circuit 402 becomes 1. The signal LD is activated (to a logical value 1).

By configuring the time window signal adjusting circuit 42 in this way, the time window adjusting signal W can be updated even when the sum of squares of the reproduced symbols I'and Q'exceeds the threshold value TH. Will be done. Therefore, according to the time window signal adjusting circuit 42, when the state of the transmission path through which the OFDM receiving apparatus 8 receives the transmission signal changes significantly and the timing of the time window signal which has been optimal until then is not optimal, or In the OFDM receiver 8, it is possible to deal with a case where the reception mode changes such as channel switching. In order for the time window signal adjusting circuit 42 to operate optimally, it is optimal that the value of the threshold value TH is slightly larger than the value that the minimum sum of squares of the reproduced symbols I ′ and Q ′ can take. Is.

The time window signal adjusting circuit 42 shown in the fifth embodiment may be configured to use a plurality of threshold values TH according to the state of the transmission path. The time window signal adjustment circuit 42 is used by the OFDM receiver 8 in addition to the case where the sum of squares of the reproduced symbols I ′ and Q ′ exceeds the threshold TH.
The time window adjustment signal W is also changed when the reception mode is changed or when the transmission parameter of the transmission signal is changed.
May be configured to be updated. Further, similarly to the time window signal adjusting circuit 40 shown in the fourth embodiment, the time window signal adjusting circuit 42 also has the multiplication circuits 300 ₁ and 30.
0 ₂ and adder circuit 322 instead of sum of squares calculation circuit 3
4 or a circuit that calculates the sum of absolute values,
It is also possible to add the filter circuit 36 (FIG. 5) to the adder circuit 322 or the sum of squares calculation circuit 34, or to add it further.

[0055]

[Sixth Embodiment] A sixth embodiment of the present invention will be described below.
FIG. 8 is a diagram showing the configuration of the time window signal adjusting circuit 44 according to the present invention in the sixth embodiment. In FIG. 8, the same components as those of the time window signal adjusting circuits 30, 40 and 42 shown in FIGS. 3, 6 and 7 are designated by the same reference numerals.

As shown in FIG. 8, the time window signal adjusting circuit 4
4 is used in place of the time window signal adjusting circuits 30, 40, 42 in the OFDM receiver 8 (FIG. 2), and is a multiplication circuit 300 ₁ , 300 of the time window signal adjusting circuits 30, 40, 42. Any of the time window signal adjusting circuits 30, 40, 42 is replaced by the CPU 440 (ROM, RAM, peripheral circuits and the like are omitted for simplification of the illustration) except for the components other than ₂ and the adding circuit 322. The operation of each component other than the multiplication circuits 300 ₁ and 300 ₂ and the addition circuit 322 is realized by software. By performing these functions with the CPU 440,
It is possible to flexibly deal with a change in the configuration of the OFDM receiver 8.

Although the mode setting input of the OFDM receiver 8 is not shown in FIG.
The CPU 440 can change the processing contents in response to the mode setting input, or can be modified so as to output a signal indicating the reception state of the transmission signal to the user. Further, the same modification as that of the modifications shown in the fourth and fifth embodiments can be applied to the time window signal adjusting circuit 44.

[0058]

As described above, according to the demodulation apparatus of the present invention, even when the transmission signal is transmitted through the transmission line in which multipath interference or noise is generated, the OFDM system is used. The time window signal for DFT, which is indispensable for demodulating the transmission signal of, can be correctly reproduced. Also, according to the demodulation device of the present invention, the time window signal for DFT can be correctly reproduced without lowering the data transmission efficiency. Also,
According to the demodulation device of the present invention, the OFDM window transmission signal can be demodulated with a low error rate by correctly reproducing the DFT time window signal.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an OFDM transmitter that transmits an OFDM transmission signal in which the amplitude of a specific frequency component is set to 0.

FIG. 2 is a diagram showing a configuration of an OFDM receiving apparatus to which a demodulating apparatus according to the present invention in a first embodiment is applied.

FIG. 3 is a diagram showing a configuration of a time window signal adjustment circuit of the demodulation circuit according to the present invention shown in FIG.

FIG. 4 shows a case where a transmission signal includes a plurality of specific frequency components,
The multiplication circuit (300 ₁, 300₂) And addition
Square sum calculation circuit used in place of the calculation circuit (322)
It is a figure which shows the structure of.

5 is between the adder circuit (322) and the buffer circuit (302) and the comparison circuit (304) of the time window signal adjustment circuit shown in FIG. 3 or the square sum calculation circuit (34) shown in FIG. It is a figure which shows the structure of the filter circuit put between the buffer circuit (302) and the comparison circuit (304).

FIG. 6 is a diagram showing a configuration of a time window signal adjustment circuit according to the present invention in a fourth embodiment.

FIG. 7 is a diagram showing a configuration of a time window signal adjustment circuit according to the present invention in a fifth embodiment.

FIG. 8 is a diagram showing a configuration of a time window signal adjustment circuit according to the present invention in a sixth embodiment.

[Explanation of symbols]

6 ... OFDM transmitter, 60 ... Orthogonal frequency multiplexing circuit,
104 ... Memory circuit, 106 ... Multiplexing circuit, 108 ₁ ,
108 ₂ ... S / P circuit, 110 ... IDFT circuit, 112
₁ , 112 ₂ ... P / S circuit, 114 ₁ , 114 ₂ ... Buffer memory, 116 ₁ , 116 ₂ ... D / A circuit, 140
... Quadrature modulation circuit, 130 ... Transmission circuit, 138 ... Transmission antenna, 8 ... OFDM receiving device, 20 ... Reception circuit, 200
... receiving antenna, 22 ... orthogonal detection circuit, 80 ... demodulation _{unit, 228 1, 228 2 ... A} / D circuit, 230 _1, 23
0 ₂ ... S / P circuit, 232 ... DFT circuit, 234 ₁ , 2
34 ₂ ... P / S circuit, 236 ... Clock generation circuit, 23
8 ... Carrier frequency control circuit, 242 ... Data correction circuit,
244 _1, 244 ₂ ... buffer memory, 246 ... reference symbol detection circuit, 30,40,42,44 ... time window signal conditioning circuit, 300 _1, 300 _2, 340 _11, 240 ₁₂ -
340 _n1 , 340 _n2 , 362 _{1 to} 362 _{m + 1} , 366 ...
Multiplier circuit, 34, 306, 314, 316, 340 ₁ ~
340 _n , 344, 364 ... Addition circuit, 310, 312
... subtraction circuit, 302, 404 ... buffer circuit, 304,
402, 406, 422 ... Comparison circuits, 308, 318 ...
Counter circuit, 316, 320 ... Selection circuit, 408, 4
24 ... OR circuit, 440 ... CPU, 36 ... Filter circuit

Claims (4)

[Claims] 1. A demodulator for demodulating a time domain signal obtained by inverse Fourier transforming predetermined frequency domain data, which includes one or more specific frequency components having an amplitude of 0 and has two orthogonal signal components, Fourier transforming the time domain signal using a predetermined time window signal, Fourier transforming means for demodulating the frequency domain data, and amplitude data indicating the amplitude of all or part of specific frequency components of the frequency domain data. A demodulator having amplitude data calculating means for calculating and time window signal generating means for adjusting the timing so that the value of the amplitude data becomes small and generating the time window signal of the Fourier transforming means. 2. The demodulator according to claim 1, further comprising a filtering unit that filters the amplitude data based on a predetermined number of the amplitude data and outputs the filtered amplitude data to the time window generating unit. 3. The time window signal generation means compares the signal generation means for generating the time window signal with a value of the amplitude data corresponding to all or a part of the specific frequency component and a predetermined threshold value. Comparing means, the value of the amplitude data corresponding to all or a part of the specific frequency component, when the predetermined threshold value or more,
The demodulator according to claim 1, further comprising a timing adjusting unit that adjusts a timing at which the signal generating unit generates the time window signal. 4. The time window signal generating means includes a signal generating means for generating the time window signal, a value of the amplitude data corresponding to all or a part of the specific frequency component, and a value of the amplitude data. Comparing means for comparing two threshold values indicating a range, and the signal generation when the value of the amplitude data corresponding to all or part of the specific frequency component is outside the range indicated by the predetermined threshold value. The demodulation device according to claim 1, wherein the means comprises timing adjusting means for adjusting the timing of generating the time window signal.