JPH08148989A - Superconducting fpga device - Google Patents

Abstract

PURPOSE: To configure the FPGA device with low power consumption at a high speed by using a Josephson integrated circuit. CONSTITUTION: The device is provided with logic units having a prescribed logic function arranged as a matrix and a wiring unit 812 located between logic units 812 in the vertical direction and the horizontal direction and connected to the logic unit 8, and the connection between the logic unit 812 and the wiring unit and the connection between the vertical and horizontal wires are made by using a superconducting multiplexer 811 and an objective logic function is realized between input terminals and output terminals being parts of the wiring unit 812.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field programmable gate array (Field Programmable Gate Array) capable of setting logic functions in an LSI mounted on a board.
y. Hereinafter, the present invention relates to an FPGA device, and more particularly to a superconducting FPGA device using Josephson elements for logic elements and program elements.

[0002]

2. Description of the Related Art A large number of products have been hitherto announced as FPGA devices capable of setting logic functions in an LSI mounted on a board. Among them, the typical Xilinx (Xi
linx) FPGA device is Nikkei Microdevice No.1
08, p. 60, (1994).

The Xilinx FPGA device can realize an arbitrary logic function desired by the user in the LSI chip by selectively connecting the input / output terminals of the variable logic unit to the horizontal or vertical wiring channels.

FIG. 5 shows the overall configuration of the logic emulation device. In the figure, 101 is an LSI chip that accommodates the entire emulation device, 102 is a variable logic unit, and 1 is a variable logic unit.
03 is an I / O unit, 104 is horizontal wiring, and 105
Is a vertical wiring. By selectively connecting the input / output terminals of the variable logic unit to horizontal or vertical wiring,
Any desired logic function can be realized in the LSI chip. It should be noted that by using a superconducting wire for the wiring of the device, the signal delay is reduced, and the speed and power consumption are reduced.

The structure of the variable logic unit is shown in FIG. In the figure, 201 is a user programmable lookup table, 202 is a user programmable multiplexer, and 2
03 is a flip-flop, 204 is an input signal line, 205
Is an output signal line.

The contents of the user programmable lookup table 201 and the switching of the user programmable multiplexer 202 are controlled by the RAM cell group 206. The input / output wiring of the variable logic unit is connected to the horizontal wiring or the vertical wiring by a switch matrix. Similarly, the horizontal wiring and the vertical wiring are connected by a switch matrix. The switch matrix is an array of switches between wirings arranged in a grid pattern.

The configuration of the inter-wiring switch 305 is shown in FIG. In the figure, 401 is a CMOS switch, which connects the horizontal wiring 104 and the vertical wiring 105. The connection control is performed by the RAM cell 402. If the content of the RAM cell 402 is "1", the horizontal wiring 104
The vertical wiring 105 is connected, and when it is '0', the two are separated. Since the CMOS switch 401 can realize an almost infinite resistance value when it is off, it can operate as an ideal bidirectional switch.

The above FPGA device can realize an arbitrary function by switching the inter-wiring switch 305.
With the progress of CMOS integration technology, the scale of a logic circuit that can be equivalently realized in one LSI reaches several thousand gates. For this reason, such an FPGA device is widely used as an operation verification and logic emulation device for a board before an LSI is prototyped.

[0009]

Problems to be solved by the invention: Verification of a voice or image LSI needs to be performed in real time. The speed required at that time is from 200 MHz to 500 MHz or more. Furthermore, since the target cannot be expanded in parallel, it is impossible to perform parallel processing or distributed processing.

A limitation of the logic emulation device to which the conventional FPGA device is applied is that the operation speed is slow compared with the case where the equivalent logic is optimally realized on the originally intended LSI. For example, the current submicron C
Clock 100 MH if optimized design in MOS process
Although it is possible to realize a logic circuit of about z, the speed that can be realized by the logic emulation device is about 10 MHz.

This is because when a CMOS or a flash memory is used as an element for inter-wiring switch as a means for realizing programmability, the parasitic capacitance and parasitic resistance of the wiring channel and the inter-wiring switch interposed between the logic gates are Because it is big. Therefore, the difference from real time is 2
It is 0 times or more, which makes it difficult to verify the logical netlist in real time.

On the other hand, when a bipolar or GaAs element SRAM is used as an element for switching between wirings, SR
Since the AM is composed of six or more flip-flop circuits, the number of elements becomes enormous, so that high integration is difficult. Furthermore, when a CMOS, a bipolar element or a flash memory is used, since the element driving voltage is 1 V or more, power consumption increases, high integration cannot be achieved, and it is difficult to apply to a portable device for communication. Further, the conventional FPGA device using the SRAM has a problem that the written program is erased when the power is turned off.

A first object of the present invention is to provide an FPGA device which can operate at high speed.

A second object of the present invention is to provide an FPGA device that can operate with low power consumption.

A third object of the present invention is to keep the selected state in logic execution even if the power is turned off.
It is to provide a GA device.

[0016]

These objects of the present invention are provided between a logic unit arranged in a grid and having a certain logical function, and between the vertical and horizontal directions of the logical unit. A wiring unit connected to the logic unit, a superconducting multiplexer is used for the connection between the logical unit and the wiring unit, and the connection between the vertical side and the horizontal side wiring, and the wiring is controlled by the switching control of the superconducting multiplexer. This is accomplished by implementing the desired logic function between the input and output terminals that are part of the unit. The present invention is a CMO for FPGA devices.
By using not the S technology but a higher speed superconducting integrated circuit technology, it is intended to realize a performance higher than that achieved in the optimum form on an LSI intended for an equivalent logic.

[0017]

In the Josephson integrated circuit, which is a typical superconducting integrated circuit, 1 GHz is obtained even if a process of about 2 μm is used.
The above operation clock can be realized. As a means for realizing programmability, an operation clock of 100 MHz or more can be realized even if wiring channels or wiring switches are interposed between logic gates. Further, by selecting a specific input of the superconducting multiplexer, the superconducting loop current is set at the time of logic programming for setting the logic function, and the selected state can be maintained even when the power is turned off at the time of executing the logic.

However, it is impossible to make the resistance value of the Josephson element in the off state infinite. Instead, the on-resistance can be zero. Therefore, CMOS
Instead of using a bidirectional switch like this, only multiplexers are combined to ensure the programmability of interconnections. Therefore, the configuration method of the entire FPGA device differs.

[0019]

1 shows the configuration of a superconducting programmable multi-input multiplexer which is a basic element of a superconducting FPGA device of the present invention. In the figure, 501 to 503 are positive input side Josephson elements, 511 to 513 are negative input side Josephson elements, 521 and 522 are load resistors, and 523 is a power source stabilizing resistor.

The loop signal S1 is applied in the positive direction to both the first positive input side (positive side) Josephson element 501 and the first negative input side (reverse side) Josephson element 511. Further, the input signal A1 is applied to the Josephson elements 501 and 511 in the forward and reverse directions, respectively. On the other hand, the direct current Ib is also supplied to the programming Josephson element 531, the reset Josephson element 532, the wiring loop 533 connected in series, and the damping resistor 534 connected in parallel. The program signal P1 is supplied to the programming Josephson element 531. A reset signal R1 is supplied to the reset Josephson element 532.

By supplying the program signal P1 with the DC current Ib being supplied, a DC current flows through the wiring loop 533, and the loop signal applied to the Josephson elements 501 and 511 is turned on. Since the wiring loop 533 forms a superconducting loop together with the programming Josephson element 531 and the reset Josephson element 532, the loop signal does not disappear even if the direct current Ib is interrupted. That is, the superconducting loop has a non-volatile function. To eliminate the loop signal, the reset signal R
1 is applied.

Similarly, the second positive input side Josephson element 502 and the second negative input side Josephson element 512.
, The loop signal S2 is applied in the positive direction.
Further, the input signal A2 is applied to the Josephson elements 502 and 512 in the forward and reverse directions, respectively.
On the other hand, by supplying the program signal P2 to the programming Josephson element 535, the Josephson element 5
The loop signal applied to 02 and 512 is turned on.

Similarly, the Nth positive input side Josephson element 503 and the Nth negative input side Josephson element 513.
, The loop signal SN is applied in the positive direction.
Further, the input signals AN are applied to the Josephson elements 503 and 513 in the forward and reverse directions, respectively.
On the other hand, by supplying the program signal PN to the programming Josephson element 536, the Josephson element 5
The loop signal applied to 03 and 513 is turned on.

Josephson elements 501-503, 511
˜513 is enabled (valid selection) only when the loop signal is turned on, the output signal is turned on when the input signal applied to the enabled element is on, and the output signal is turned on when the input signal is off. Will also be off. That is, an output signal corresponding to the input signal applied to the enabled element is generated. However, only one loop signal is selected from N loop signals. Since the loop signal is generated by the program signal, the input signal selected by the program signal appears at the output. That is, it operates as a programmable multi-input multiplexer.

FIG. 2 shows a symbol diagram of a programmable multi-input multiplexer used in the description of the embodiments below. Unless otherwise specified, program signals and power supply currents are omitted and only the input signals and output signals OUT of A1 to AN are shown as in the symbol diagram 601. When the input signals A1 to AN are also used in the next stage, they are written as 602. When the input signal A0 is used only in that stage, it is noted as 603.

FIG. 3 shows the configuration of the logic / wiring unit which is the basic unit of the superconducting FPGA device of the present invention. In the figure, 701 is N input buses to the relevant stage, and 702 is N output buses to the next stage. Reference numeral 703 denotes M internal buses. Reference numeral 711 is a variable logic unit, which is composed of a plurality of OR's and Joseph's composed of Josephson elements.
Arbitrary logic can be formed by wiring connection of these OR and AND.

Some of the inputs of variable logic unit 711 are provided as program inputs 712. Remaining inputs 71
3 is obtained by selectively connecting the input bus with the N input multiplexer 714. The output signal line of the variable logic unit 711 constitutes one of the output buses. Input bus 701 to the stage
From the i-th row and M internal buses 703 of the output bus 702 to the next stage by the (M + 1) input multiplexer.
The row is selected. The portion 716 of the N (M + 1) input multiplexers is used as an N × M multiplexer for other portions.

In this embodiment, the logic is formed by the variable logic unit, but the variable logic unit may be formed by the superconducting loop of the programmable multi-input multiplexer and the multiplexer may be used to form the logic.

FIG. 4 shows the overall structure of the superconducting FPGA device of the present invention. In the figure, reference numeral 801 denotes an input bus to the entire device,
There are N. On the other hand, 802 is an output bus from the entire device,
There are M books. The output bus is a flip-flop unit 80
Returned to 4. The flip-flop unit 804 is a parallel arrangement of M flip-flops supplied with a clock. Flip-flop unit 804
M outputs 805 of are connected to the internal bus of the N × M multiplexer 811.

The input bus 801 to the entire device is connected to the input bus of the N × M multiplexer 811. There are M N × M multiplexers 811 and the internal configuration is 7 in FIG.
16 shows. The core of this device is a logic / wiring unit 812 arranged in M rows and K columns. First row M
The logic / wiring units are M internal buses 81 to each other.
3, and each of the N output buses 814 of the N × M multiplexer 811 is received as an input bus.

Similarly, the M logic / wiring units in the second column accept the output bus 815 in the first column as an input bus. Similarly, the M logic / wiring units in the Kth column, which is the last column, receive the output bus 816 in the (K−1) th column as an input bus. The internal buses of the M logic / wiring units in the Kth column are connected to the output bus 802 from the entire device.

In the FPGA device of the present invention, the semiconductor FPG
Since a programmable multi-input multiplexer is used instead of the CMOS switch in the A device, it is not possible to send and receive signals bidirectionally within the array of logic / wiring units. The output of the logic / wiring unit in the i-th column is (i +
1) It is inherited by the column and cannot propagate in the opposite direction. Therefore, the number of logic stages between latches of the logic circuit to be simulated is
It must be within the number of logic stages in the variable logic unit × the number of logic / wiring unit columns (K). Since the variable logic unit is a combinational circuit, a latch is required when simulating an arbitrary sequential circuit. In the present invention, the sequential circuit is realized by using the flip-flop unit 804. Since the output 805 of the flip-flop unit 804 is fed back to the head of the array of logic / wiring units via the N × M multiplexer 811, it is possible to simulate a circuit including both a combinational circuit of a certain scale and a sequential circuit. It will be possible.

By connecting the superconducting FPGA device of FIG. 4 in a larger scale and arranging P rows in the X direction and Q rows in the Y direction, the logic scale that can be simulated as a whole is expanded by (P × Q) times. be able to. This makes it possible to realize a large-scale logic function, for example, a logic emulation device.

According to this embodiment, since the FPGA device can be constructed by using the superconducting programmable multi-input multiplexer, it is possible to realize the FPGA device which operates at high speed and low power consumption. Also, high integration can be achieved. Another object of the present invention is to provide a non-volatile FPGA device that retains the selected state during logic execution even when the power is turned off. By using the superconducting FPGA device of this embodiment, it is possible to easily realize the operation verification of the board before the trial manufacture of the LSI and the logic emulation device.

[0035]

According to the present invention, since the FPGA device can be constructed by using the superconducting programmable multi-input multiplexer, it is possible to realize the FPGA device which operates at high speed with low power consumption. Also, high integration can be achieved. Furthermore, it is possible to provide an FPGA device that performs a non-volatile operation in which the selected state is held during logic execution even when the power is turned off.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a superconducting programmable multi-input multiplexer of the present invention.

FIG. 2 is an explanatory diagram of symbols of the multi-input multiplexer of the present invention.

FIG. 3 is a system diagram showing a configuration of a logic / wiring unit of the superconducting FPGA device of the present invention.

FIG. 4 is a system diagram showing the overall configuration of a superconducting FPGA device of the present invention.

FIG. 5 is an explanatory diagram showing the overall configuration of a conventional FPGA device.

FIG. 6 is a system diagram showing a configuration of a variable logic unit in a conventional FPGA device.

FIG. 7 is an explanatory diagram showing a configuration of an inter-wiring switch in a conventional FPGA device.

[Explanation of symbols]

801 ... Input bus, 802 ... Output bus, 804 ... Flip-flop unit, 805 ... Output, 811 ... N × M multiplexer, 812 ... Logic / wiring unit, 813 ...
Internal bus, 814 ... Output bus, 815 ... Output bus, 81
6 ... Output bus.

Claims (4)

[Claims] 1. A logic unit having a certain logic function arranged in a grid pattern, and a wiring unit provided between the vertical and horizontal directions of the logical unit and connected to the logical unit. A superconducting multiplexer is used for connecting the logic unit and the wiring unit, and for connecting vertical wiring and horizontal wiring, and an input terminal and an output terminal which are part of the wiring unit are controlled by switching control of the superconducting multiplexer. A superconducting FPGA device, which realizes a desired logical function between and. 2. The superconducting multiplexer according to claim 1, wherein one signal line and a positive Josephson element in which an enable line of the signal line is input in a positive direction and the signal line in a reverse direction are input. A pair of reverse-side Josephson elements to which the enable wirings of the signal wirings are input in the forward direction are set, and a plurality of these sets are connected in cascade, and an enable input is given to one of the plurality of sets. Thus, a superconducting FPGA device in which the input of the same set of signal lines as that set appears at the output. 3. The enable input according to claim 2,
It is supplied as a loop current of a superconducting loop composed of two Josephson elements and a superconducting wiring connecting them in series, and the loop current is set at the time of a logic program for setting a logic function in the FPGA device to identify the superconducting multiplexer A superconducting FPGA device that realizes input selection and retains the selected state during logic execution. 4. A flip-flop unit having a function of simulating a sequential circuit according to claim 1, wherein the output of the flip-flop unit is fed back to the head of the array of logic units and wiring units via the superconducting multiplexer. Superconducting FPGA device.