JPH0782313B2 - Display controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention is a display control for smoothly controlling display information such as character display in an image display device, which is divided into display sections and units of rows and columns. Regarding the device.

[Conventional technology]

Information such as sentences (hereinafter referred to as text), graphics / images (hereinafter referred to as graphics), etc. stored in a memory (for example, a fresh memory using a dynamic memory) using a raster scanning cathode ray tube (hereinafter referred to as CRT) as a display device. The function to display is one of the important functions of the image processing device.
Is one.

With conventional devices such as character terminals, simple display of alphanumeric characters was the main focus, but recent business personal computers and word processors use interactive processing to display a menu in a certain area on the screen. Advanced functions such as scrolling the screen smoothly are needed.

The sulcall function is a function that moves the data on the CRT screen up and down or left and right. There are jump scroll that moves in line or character units and smooth scroll that moves smoothly in 1 raster or dot units. . Compared to jump scrolling, smooth scrolling has the advantage of being easier to see and being able to follow the display data with the eyes even during the scrolling period, and more and more devices have this function.

Conventionally, in order to realize this smooth scroll,
It was necessary to attach a circuit externally to the display control device and process the software by the central processing unit of the equipment. But,
Then, the number of parts increases and the processing capability of the central processing unit is sacrificed. Therefore, a display control device having this function is desired.

[Problems to be solved by the invention]

In order to realize such smooth scroll display, conventionally, an external circuit has been added to the display control device, and special processing for controlling the circuit has been performed by the central processing unit of the device.

5 (a) and 5 (b) show the smoothness of the conventional device.
In the time chart of the scroll operation, an example in which the number of rasters in one line is 6 rasters is shown, and the reference signal SS generated by the display control device and the character line number ROW and the raster number of the display signal generated in synchronization with each other. In addition to RAS correspondence, a vertical synchronizing signal VS for determining the vertical position of the CRT screen and a blanking signal VB indicating a period during which a video signal to the CRT screen is not generated are shown. Although not included in the timing chart, there are also horizontal synchronizing signals and blanking signals.

First, when the scroll operation is not performed, as shown in FIG. 5 (a), the reference signal generated by the display control device is generated.
A synchronizing signal VS and a blanking signal VB are generated in synchronism with SS, and after a suitable time has elapsed, a display information storage address (ROW) and a raster number (RAS) are generated to generate a display signal.

After a certain time (indicated by T in the figure) from the reference signal SS, a display signal corresponding to the 0th raster of the 0th row is generated, and the raster number RAS or the display row ROW is updated every horizontal scanning, A first raster of the 0th row, ..., A fifth raster of the 0th row, and then a 0th raster of the first row and a display signal are generated. Here, when the blanking signal VB is controlled by the external circuit and the predetermined time T has passed, the signal is set to the "0" level. As a result, on the CRT screen, the video signal is generated from that time, and the CRT screen is displayed from the 0th row and the 0th raster.

Next, even when smooth / scrolling is performed, as shown in FIG. 5 (b), a display signal is generated from the 0th raster of the 0th row in synchronization with the reference signal of the display control device. Here, the vertical synchronizing signal and the blanking signal are delayed by the external circuit, and the timing of both signals is generated by the external circuit as compared with VS2 and VB2 in FIG. Thus, if the timing is delayed by one raster, the first and subsequent rasters in the 0th row are displayed. In addition, the timing of the sync signal and the blanking signal can be set to VS3, VB3, VS
By gradually delaying 4 and VB4, ..., From the second raster onward, the third raster onward to the final raster are displayed, and the display of one line is scrolled. After delaying the signal to the final raster of one row, return to the state of delay time 0 (VS7 and VB7) again, and perform the same one-row scroll operation as the jump scroll to display from the 0th raster of the first row. Was starting. By repeating such an operation, smooth scrolling over a plurality of lines has been realized.

Here, the central processing unit sets the delay time value of the VS signal and the VB signal in the external circuit every time one raster is scrolled, checks the delay time value of the signal, and scrolls the first line. When the completion is detected, the delay time must be reset to 0, which causes a problem that the central processing unit, such as editing and communication, has a reduced ability to perform the original processing. Furthermore, when an urgent interrupt occurs when updating the delay time of the signal to the next value, the update of the delay time may be delayed due to the interrupt process, resulting in non-smooth scrolling.

Also, when the CRT screen is divided and displayed, smooth scrolling of only one split screen in the middle cannot be realized by the method of using the synchronization signal or blanking signal related to the CRT scanning. There has been a demand for a means capable of smoothly scrolling even in a scene.

An object of the present invention is to solve these problems and to provide a display control device capable of smoothly scrolling on a CRT screen.

[Means for solving problems]

According to the configuration of the present invention, a display timing control unit that generates display timing including horizontal scanning and vertical scanning timing, a display data storage unit that stores display information displayed on the display unit, and an address of the display data storage unit are provided. The display control device includes a display address designating unit for designating and updating a designated value according to the display timing, a raster counter for designating a raster position of the display information, and a control processor for processing the display information. The processor includes a plurality of program counters for designating addresses of instruction words, a plurality of state registers for storing states of execution results of instructions, and means for selecting one set from the program counters and the state registers. , Selecting the program counter and status register in synchronization with the horizontal scanning timing, Determining the time and state of the scroll according to the contents read out by the serial addressing selected program counter, and performs the update process by the initial setting or operation of the raster counter.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a display system including an embodiment of the present invention. In the figure, a display system is configured by connecting a display memory 2, a video signal generating circuit 3 and a CRT 4 similar to those in the conventional art to a display control device 1 of this embodiment.

The display control device 1 includes a display timing control unit that generates a display timing, a display memory control unit that controls the address and data of the display memory, and display information of the display memory that receives commands from the central processing unit of the system. There is a control processor unit for processing the display timing and operating the display timing and the control unit of the memory, each of which is connected to the internal bus 21. It should be noted that although there is a portion for transferring commands and data to and from the central processing unit of the system, it is omitted because it is the same as the conventional one.

The control processor unit has two program counters 11 and 12 for specifying the address of the program to be executed, two status registers 13 and 14 for holding the operating state of the program, and temporary storage of processing data and addressing of the memory. General-purpose register 15 used for the operation and arithmetic circuit 16 that performs arithmetic logic operation
An instruction decoder 17 that takes in and decodes an instruction word to be executed to generate a control signal, a program memory 18 that stores a program, a data memory 19 that stores variables such as display control parameters, and program switching. And a control flag 20 for controlling the.

In the main program such as command processing from the central processing unit, the control flag 20 is reset and its output is passed through the inversion circuit 28 to the first program counter 11 and the first program counter 11.
Select the status register 13 of the
The instruction word read by addressing the program memory 18 in 11 is sent to the instruction decoder 17 via the internal bus 21,
Based on a control signal generated by the instruction decoder 17, processing data is transferred between the general-purpose register 15 or the data memory 19 and the arithmetic circuit 16 to perform arithmetic / judgment processing. Here, the first status register 13 is selected and stores a status such as a carry generated in the arithmetic circuit 16.

In the display memory control unit, a display address counter 22 that generates a display memory address of information to be displayed, a raster counter 23 that specifies the number of rasters in a display section, and a signal of an internal circuit are selected to display the display memory 2. There is an interface circuit 24 for transmitting an address and a data signal, and in the operation of the display data in the command processing, the data of the internal bus 21 is selected and used as the address and the data signal to the display memory 2, and the CR
When reading display information to T, display address counter 22
And the raster counter 23 as an output signal. The display address counter 22 is set to the value written by the control processor when the synchronization signal is generated, and the horizontal timing control unit
It increments in synchronization with the 25 display partition signals.

This display timing control unit is similar to the horizontal timing control circuit 25 that counts the number of horizontal dots in the display section and the number of display sections in addition to time parameters such as CRT horizontal scanning synchronization, erasure, effective display, and blanking. There is a vertical timing control circuit 27 for counting the vertical time parameter of the CRT and the vertical position, and each generates a timing signal for the display area.

Since the display parameters of the CRT are the same as the conventional ones, the explanation is omitted and the address control of the display memory will be explained. The display partition signal is generated by the horizontal timing control circuit 25 for each dot time of one display partition of the display memory, and is incremented by the display address counter 22 and the parallel-serial conversion is carried out by the video signal generating circuit 3 for one display. The display address counter 22 is updated to the address value of the information to be output next to the CRT 4 each time the division time has elapsed. The horizontal timing signal is generated by the horizontal timing control circuit 25 every time the horizontal display time of the CRT is over, sets the control flag 20, and outputs the flag to select the second program counter 12 and the status register 14. In this embodiment, the second program processing for counting and updating the display address and the raster address is performed by using the selected second program counter 12 and the status register 14.

FIG. 2 is a schematic diagram showing the correspondence between the contents of the display memory 2 of FIG. 1 and the screen image of the CRT 4, and FIG. 3 is a layout diagram of the device variables used in the second program processing on the data memory 19.
FIG. 4 shows a flowchart of the second program processing. A process for performing smooth scroll will be described.

As shown in FIG. 3, in the data memory 19, as a variable to be processed by the program, the maximum raster count MRC indicating the number of rasters in one line and the display start indicating the start address of the data to be displayed on the second CRT screen are displayed. Memory address SAD, display row address pitch PIT showing the number of data displayed on one line on the CRT screen, scroll offset SOF showing the number of rasters to be offset when scrolling, and the same screen to adjust the scrolling speed. Are allocated to a display screen counter SC that counts how many times are displayed, a maximum display screen number MSC that specifies the maximum value, and a scroll line counter CC that indicates the number of lines to be scrolled.

When the horizontal timing signal is generated from the horizontal timing control circuit 25, the control flag 20 is set, the second program counter 12 and the status register 14 are selected, and the processing of the flowchart of FIG. 4 is started. Since the first program counter 11 and the status register 13 are not selected,
It holds the execution state value of the main program immediately before register switching.

In the program activated by the horizontal timing signal, it is first determined in step 31 that the frame of the CRT screen is changed by determining whether or not the vertical synchronization signal is generated. If the vertical sync signal is detected and it is determined that the screen will change, the display screen counter SC and the maximum number of display screens are determined in step 32.
Compare with MSC. The display screen counter SC indicates how many times the same screen is displayed by incrementing and incrementing "1" each time the display of one screen is completed, and stores the number of times the same screen is desired to be displayed. Maximum number of display screens MSC
If it is determined whether or not to scroll by comparing with, scrolling can be performed at an arbitrary constant speed. If it is determined that the display screen counter SC and the maximum display screen number MSC are not equal to each other, that is, if the display is being performed the specified number of times, the display screen counter SC is incremented by 1 in step 33, Displayed at 41 Address counter
The MAC is returned to the same display start memory address SAD as the previous screen, the raster counter RC is returned to the same scroll offset value as the previous screen in step 42, and the second program processing is ended.

Display screen counter SC and maximum display screen number MSC in step 32
If and are equal to each other, the display screen counter SC is reset to 0 in step 34 at the time of scrolling. Then step
At 35, it is determined whether or not the scroll for the designated line is finished according to the value of the scroll line counter CC, and if CC is not 0 and the scroll is not finished, at step 36, the scroll offset SOF and the maximum raster counter MRC are next. Compare
Judge whether the scroll of a certain character line has ended,
If the comparison results do not match, scrolling of one character line has not ended, so in step 37, scroll offset SOF
After incrementing by 1, the display address counter MAC is returned to the same display start memory address SAD value as in the previous screen in step 41, and the scroll offset value updated in step 37 is stored in RC in step 42. The program processing of No. 2 is completed.

If the scroll offset SOF and the maximum raster counter MRC are equal in the determination in step 36, when the scroll for one line is completed, the scroll designated line number CC is decremented by 1 in step 38, and the scroll offset SOF value is determined in step 39. Back to 0, then step 4
At 0, the display row address pitch PIT is added to the display start address SAD to update the display start address value of the next row. Next, the value of the display start address SAD updated in step 41 is stored in the display address counter MAC, and the scroll offset value returned to 0 is stored in the raster counter RC in step 42.
RC is returned to the initial value, and the second program processing ends.
If CC is 0 in step 35, it is determined that the scrolling for the specified number of lines is completed, the display address counter MAC is returned to the display start memory address SAD, and the scroll offset SOF (always becomes 0 after the scrolling is completed). Value is stored in the raster counter RC (steps 41 and 42), and the second program processing ends.

If the vertical sync signal is not detected in the judgment in step 31, it is judged in step 43 whether or not it is the effective display area where the blanking signal is not generated.
If this is not the effective display area, the process for generating the display signal is not necessary, so the second program process is terminated. If it is a valid display area, the raster counter RC and the maximum raster counter MRC are compared in step 44 to determine the end of one character line, and when it is determined that the CRT display is within one character line due to mismatch, step 45 In step 46, add "1" to the raster counter RC to make it the next raster of the character line, and if it is judged that the display of the character line has ended by matching, add the display address pitch PIT to the display address counter MAC in step 46. And update to the next display line,
In step 47, the raster counter RC is initialized to "0" and the second
Ends the program processing of.

In this way, the number of times the same screen is displayed is counted for each vertical scan, and the raster address of the display start and the address of the display data are changed every predetermined number of times, and the initial value is also set for each horizontal scan during the effective display period. By smoothly updating the raster address and the display data address, it is possible to perform smooth scrolling.

In terms of hardware, only by providing the second program counter 12, the second status register 14 and the control flag 20, the arithmetic circuit 16 such as the control processor, the data memory 19 and the like can be shared for arithmetic operation and judgment. Therefore, it is not necessary to provide a special circuit such as a comparison circuit or an arithmetic circuit. Here, the processing of the main program is temporarily interrupted for screen division processing, but the processing time is short due to simple comparison and transfer, and the program can be switched simply by setting / resetting the control flag 20. , It is faster than a generally known interrupt that saves and restores the program counter and status register to the stack, and has the least effect on the processing capacity and performance of the main program.

〔The invention's effect〕

As described above, according to the present invention, the processing of smoothly scrolling the CRT screen can be performed by using the hardware of the control processor by simply adding the hardware that switches the program processing in synchronization with the horizontal scanning timing. Therefore, it is possible to provide an inexpensive display control device by sharing the minimum hardware.

Further, since the display control device performs all the processing for smoothly scrolling, the central processing unit does not need to perform the troublesome processing such as setting the delay time in the external circuit, and the processing of the central processing unit is concerned. It is possible to prevent unsmooth scrolling that has occurred in.

[Brief description of drawings]

FIG. 1 is a block diagram of a display system including an embodiment of the present invention, FIG. 2 is a schematic diagram showing a screen image of the display data memory 2 and CRT 4 of FIG. 1, and FIG. 3 is a data memory of FIG.
An arrangement diagram showing control variables to be assigned to 19, FIG. 4 is a flowchart of scroll processing of the present embodiment, FIG. 5 (a),
(B) is a time chart of a conventional smooth scroll operation. 1 ... Display control device, 2 ... Display memory, 3 ... Video signal generation circuit, 4 ... CRT, 11, 12 ... Program counter, 13, 14 ... Status register, 15 ... General-purpose register, 16
...... Arithmetic circuit, 17 ...... Instruction decoder, 18 ...... Program memory, 19 ...... Data memory, 20 ...... Control flag, 21 ...
… Internal bus, 22 …… Display address counter, 23 …… Raster counter, 24 …… Interface circuit, 25 …… Horizontal timing control circuit, 27 …… Vertical timing circuit, 28…
… Inversion circuit, 31-47 …… Processing steps.

Claims (1)

[Claims] 1. A display timing control section for generating display timing including horizontal scanning and vertical scanning timing, a display data storage section for storing display information displayed on the display section, and an address of this display data storage section. A display including a display address designating unit for updating a designated value according to the display timing, a raster counter for designating a raster position of the display information in synchronization with the display timing, and a control processor for processing the display information. In the control device, the control processor is provided with a plurality of program counters for designating an address of an instruction word, a plurality of state registers for storing a state of an execution result of an instruction, and one set of each program counter and each state register. Means for selecting, and the program counter and the counter in synchronization with the horizontal scanning timing. Select the status register, to determine the time and state of the scroll according to the content read by the addressing of the selected program counter,
A display control device characterized by performing initial setting or increment of the raster counter and initial value setting of the display address designating unit or update processing by calculation.