JPH07201692A - Wafer - Google Patents

Abstract

PURPOSE:To provide a wafer capable of preventing the generation of foreign matter due to chipping of a junction part between a contour line of a wafer and a wafer cutout part, and the generation of other various fails. CONSTITUTION:A junction part between a contour line and a cutout part 8 of a wafer 1 is chamfered. Thus, as there does not exist an acute angle part or a bent part in the junction part between the positioning cutout part 8 of the wafer 1 and the contour line of the wafer 1, it is possible to remarkably reduce fails caused by existence of the acute angle part or bent part such as foreign matter fails, carrying fails, and resist film thickness fails due to chipping of the wafer 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer, and more particularly to a wafer capable of preventing defects such as chipping at the joint between the contour of the wafer and the notch.

[0002]

2. Description of the Related Art Generally, transistors, integrated circuits (I
C) and the manufacture of semiconductor devices such as large scale integrated circuits (LSI), diffusion, resist coating, etching, etc. are performed on wafers made of semiconductor materials such as silicon (Si).
When processing such as vapor deposition, if foreign matter such as minute dust or chipping pieces adheres to the surface of the wafer, it may cause scratches on the surface of the wafer, uneven film thickness or defective transfer. Will end up.

There are various causes for the generation of such foreign matters. One of them is, for example, when the outer periphery of the wafer collides with some transport mechanism or the wafers come into contact with each other when the wafer is transported. It is known that a part of the outer peripheral portion of the wafer itself is damaged, and the chipping pieces caused by the damage adhere to the surface of the wafer as foreign matter, causing various defects. Therefore, it has been conventionally proposed to chamfer both main surfaces of the outer peripheral portion of the wafer by mechanical or chemical means in order to prevent such a defect in the outer peripheral portion of the wafer.

[0004]

However, the chipping of the wafer cannot be completely prevented only by chamfering both main surfaces of the outer peripheral portion of the wafer in this manner.

Therefore, as a result of the inventors of the present invention having conducted extensive studies to investigate the cause of such chipping, the following important facts have been found. That is, a flat portion called an orientation flat (main flat) is generally formed on a wafer by showing a crystal axis direction of the wafer and cutting a part of the wafer into a linear shape for positioning. However, due to the formation of such a flat portion, an acute-angled bent portion is formed at the joint between the flat portion and the outline of the wafer. As a result, the bonding portion is apt to cause chipping, and when the wafer is transported, the bonding portion collides with the guide of the air bearing or comes into contact with another wafer, so that the bonding portion is damaged and the chipping piece is removed. It will happen.

In addition to the linear cutting as described above for positioning the wafer, when a cutout is provided in a part of the wafer, an acute angle is formed at the joint between the outline of the wafer and the cutout. A bent portion is formed, and the same problem as described above occurs.

[0007] In particular, the present invention is directed to a wafer using a cutout portion. Therefore, the object of the present invention is to generate foreign matter due to chipping of the joint between the wafer outline and the cutout portion, and the like. It is an object of the present invention to provide a wafer capable of preventing the occurrence of various types of defects.

[0008]

The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the wafer is such that the joint between the outline of the wafer and the notch is chamfered in a plan view.

[0010]

According to the above-mentioned means, since the joint portion between the contour line of the wafer and the cutout portion is chamfered, there are no sharp corners or bent portions, and the joint portion causes chipping. Absent. Therefore, it is possible to prevent the generation of foreign matter and various other defects due to chipping.

[0011]

The present invention will be described in detail below with reference to the embodiments shown in the drawings.

1 and 2 show an embodiment of a wafer according to the present invention. FIG. 1 is its plan view and FIG. 2 is an enlarged sectional view.

The wafer 1 of the present embodiment has a circular shape formed by slicing a single crystal of silicon (Si), for example, a part of which shows the direction of the crystal axis and serves to position the wafer 1 in various processes. A main flat, that is, an orientation flat (O.F.) 2 is linearly cut and formed as a positioning removing portion for performing.

The outer peripheral portion 3 of the wafer 1 is chamfered, for example, in an arc shape, as can be seen from FIG. This chamfering prevents damage to the outer peripheral portion of the wafer and prevents chipping at the outer peripheral portion of the wafer.

Further, the wafer 1 in this embodiment is chamfered in an arc shape in which a corner area indicated by a chain double-dashed line is indicated by a solid line at a joint 4 between both ends of the orientation flat 2 and the outline of the wafer 1. The corner area of the bonding portion 4 is configured to prevent defects such as chipping during various processing of the wafer 1 and generation of foreign matter as chipping pieces due to chipping. That is, the chamfered region 5 of the bonding portion 4 in the embodiment of FIG. 1 is a region surrounded by a chain double-dashed line, and the inner edge of this chamfered region 5 is a common inner portion that is inscribed in the contour line of the wafer 1 and the orientation flat 2. It is defined by the arc of a tangent circle.

When chamfering the arcuate shape of the joint portion 4, a preferable chamfering range of the chamfering region 5 is determined as follows, which will be described in detail with reference to FIG.

In FIG. 3, the radius of the wafer 1 is R and its center is O ₁ . When the distance from the center O ₁ to the orientation flat 2 is y and a perpendicular is drawn from O ₁ to the orientation flat 2, the intersection point P is the midpoint of the orientation flat 2 and the entire length of the orientation flat 2 before chamfering. Orientation flat 2 from half
The distance from the contour line of the wafer 1 to the bonding portion 4 is b.

The relationship between the length of the orientation flat 2 and the thickness of the wafer 1 and the diameter of the wafer may be as shown in Table 1 in a mirror wafer (mirror surface wafer) state.
It is defined in the EMI standard.

[0019]

[Table 1]

On the other hand, since it is necessary to align the wafer 1 using the orientation flat 2, the orientation flat 2 has a minimum length of a flat portion that must be provided for accurate alignment. If half of the length is a, the length a is the distance from the point P to the inner contact point i ₁ between the common inscribed circle and the orientation flat 2. Reference numeral 6 is a positioning roller,
Other than that, a photoelectric conversion element or the like may be used as the alignment means.

When the inner contact point between the common inscribed circle and the outline of the wafer 1 is i ₂ , the center O ₂ of the common inscribed circle is the wafer 1
Is a straight line connecting the center O _{1 of the} and the inner contact i ₂ and the angle between this straight line and the straight line O ₁ P is represented by θ.

Therefore, the radius r of the common inscribed circle inscribed in both the outline of the wafer 1 and the orientation flat 2 is obtained as follows.

First, the minimum length that the roller 6 must have for alignment, that is, the length a (a = Pi ₂ ) of the flat portion of the orientation flat 2 that is not chamfered is

[0024]

[Equation 1]

Next, the length y of the vertical O ₁ P from the center O _{1 of the} wafer 1 to the orientation flat 2 is

[0026]

[Equation 2]

From the right-angled triangle O ₁ P4, y ² = R ²
Since it is −b ² ,

[0028]

[Equation 3]

Substituting the equation (3) into the equation (2),

[0030]

[Equation 4]

From the equation (1),

[0032]

[Equation 5]

From sin ² θ + cos ² θ = 1, from (Equation 4) and (Equation 5),

[0034]

[Equation 6]

Organizing equation (6),

[0036]

[Equation 7]

Therefore, in the present embodiment, the chamfered region 5 in the joining region between the contour line of the wafer 1 and the orientation flat 2 is as shown by the diagonal lines in FIG.
The chamfering may be performed along the circular arc of any radius as long as it is within the circular arc of the common inscribed circle having the radius r of the formula (7) or the region outside thereof.

That is, the radius r of the inscribed circle common to both the outline of the wafer 1 and the orientation flat 2
Is within the range shown by the following formula, and chamfering may be performed in an arc shape within the range of the radius r.

[0039]

[Equation 8]

As a result, according to the present embodiment, since no sharp corners or bent portions are present in the joining region between the outline of the wafer 1 and the orientation flat 2,
It is possible to prevent a chipping piece from being generated due to the bonding area colliding with a guide of an air bearing or being in contact with another wafer when the wafer 1 is transferred, for example. In addition to the foreign matter defect due to the generation of such chipping pieces, the conveyance failure due to the sharp corner portion being caught by the guide of the air bearing during the conveyance, and the air flow being disturbed at the sharp corner portion during the resist coating, It is possible to remarkably reduce defects such as a resist film thickness defect due to a partial variation of the resist film thickness, which is particularly suitable for a large-diameter wafer.

FIG. 4 is a plan view showing another embodiment of the wafer according to the present invention.

In this embodiment, the bonding area between the contour line of the wafer 1 and the orientation flat 2 is linearly chamfered within the range of the chamfered area 5.
In this case, the maximum chamfering range of the chamfered region 5 is, as described above with reference to FIG. 3, the inner contact i of the common inscribed circle with both the outline of the wafer 1 and the orientation flat 2.
It is defined by the straight line connecting ₁ and i ₂ . The radius r of this common inscribed circle can be selected within the same range as shown in the above formula (Equation 8).

Also in this embodiment, since there is no sharp corner or bent portion at the joint 4 between the outline of the wafer 1 and the orientation flat 2, defective foreign matter due to chipping pieces, defective conveyance, resist film. Thickness defects and the like can be greatly reduced.

The chamfering process according to the present invention is not limited to the arc shape or the linear shape of the above-described embodiment, but may be any chamfering shape as long as it can eliminate sharp corners such as various curved shapes or polygonal shapes. It can also be shaped. The present invention can also be applied to the case where a sub-flat, that is, a second flat is provided in addition to the above-mentioned main flat, that is, the orientation flat. That is, in this case, as shown in FIG. 5, the chamfering region 5 in the joining region between the both ends of the orientation flat 2 and the outline of the wafer 1 is chamfered, and both ends of the second flat 7 and the outline of the wafer 1 are processed. The joint area with the
A chamfering process is performed along an arc of a common inscribed circle that inscribes both the flat 7 and the outline of the wafer 1 or a straight line connecting the inner contacts or in an area outside thereof.

Further, in addition to the flat portions such as the orientation flat 2 and the second flat 7, the present invention is also applied to the case where a curved positioning notch is formed on the wafer 1 as illustrated by reference numeral 8 in FIG. can do. That is, in this case, the joint area between the both ends of the positioning notch 8 and the contour line of the wafer 1 is inscribed in both the positioning notch 8 and the contour line of the wafer 1 as shown by 5b. The chamfering may be performed along the arc of the tangent circle or the straight line connecting the inner contact points or in the area outside thereof.

The chamfering process of the present invention may be performed simultaneously with the formation of the orientation flat 2 or the chamfering process of the outer peripheral portion 3 in the thickness direction. Such simultaneous chamfering process is work-efficient. Very good, but may be chamfered separately. Of course, the present invention does not necessarily require chamfering of the outer peripheral portion 3 of the wafer 1 in the thickness direction.

Various devices are conceivable as the device that can be used for chamfering according to the present invention, and FIGS. 6 to 8 show an example thereof.

The chamfering device shown in FIG. 6 is of a so-called shape copying type. The grindstone 8 having the linear groove 9 is moved in the horizontal and vertical directions while being rotated to perform the chamfering process. Chamfering in the thickness direction can also be performed.

The chamfering device of FIG. 7 is of a so-called shape transfer type, and the grindstone 10 having the curved groove 11 matching the chamfered shape in the thickness direction of the outer peripheral portion 3 of the wafer 1 is moved horizontally while being rotated. Thus, the outer peripheral portion 3 of the wafer 1 can be chamfered as shown in FIG. 2, and the chamfered regions 5, 5a, 5b shown in FIGS. 3 to 5 can be chamfered.

As described above, the chamfering device of FIGS. 6 and 7 can perform both the chamfering of the chamfered regions 5, 5a and 5b and the chamfering of the outer peripheral portion 3 of the wafer 1. The processing may be performed separately, but it is efficient to perform them simultaneously.

The chamfering device shown in FIG. 8 chemically chamfers, and a large number of wafers 1 are attached to the rotary finger holder 12.
It is submerged in the etching solution 14 in the etching tank 13 by sandwiching it between the two, and the outer peripheral portion of the wafer 1 is etched by the etching solution 14 while being rotated together with the rotary finger holder 12. In this case, in order to perform the chamfering process only on the chamfered regions 5, 5a, 5b, the other outer peripheral portion of the wafer 1 is etched with the etching solution 1.
Although it is necessary to mask so as not to touch 4, the chamfered regions 5, 5a and 5b are chamfered by mechanical grinding in advance,
The corners of the entire outer peripheral portion may be chemically chamfered in the thickness direction with an etching solution. In the case of FIG. 8, the mechanical impact on the wafer 1 can be reduced.

The present invention is not limited to wafers made of silicon (Si) but can be applied to wafers made of germanium (Ge) or various compound semiconductor materials such as gallium arsenide (GaAs) and gallium garnet.

[0053]

As described above, according to the present invention,
Since there are no sharp corners or bends in the joint between the wafer positioning notch and the wafer outline, there are no sharp corners such as foreign matter defects due to wafer chipping, conveyance defects, or resist film thickness defects. Alternatively, defects due to the presence of the bent portion can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of a wafer according to the present invention.

FIG. 2 is an enlarged cross-sectional view of the wafer of FIG.

FIG. 3 is a plan view for explaining determination of a chamfered area in the wafer of FIG.

FIG. 4 is a plan view of another embodiment of the wafer according to the present invention.

FIG. 5 is a plan view showing still another embodiment of the present invention.

FIG. 6 is a view showing an example of a chamfering device that can be used for carrying out the wafer processing method according to the present invention.

FIG. 7 is a view showing an example of a chamfering device that can be used for carrying out the wafer processing method according to the present invention.

FIG. 8 is a view showing an example of a chamfering device that can be used to carry out the wafer processing method according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... Orientation flat, 3 ... Outer peripheral part, 4 ... Joining part of the wafer outline and orientation flat before chamfering, 5, 5a, 5b ... Chamfering area, 6 ... Positioning roller, 7 ... 2nd flat, 8
… Notches for positioning.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Etsuro Etsuka Nishinachiman, Ryuo-cho, Nakakoma-gun, Yamanashi (No. No.) Ltd. Hitachi, Ltd. Musashi Factory Kofu Branch Factory

Claims (3)

[Claims] 1. A wafer, characterized in that a joint between a contour line of the wafer and a cutout portion with respect to the contour of the wafer is chamfered in a planar shape. 2. The chamfering process is performed in a curved shape along a contour line of the wafer and a common inscribed circle of the cutout portion or in a region outside thereof. Wafer. 3. The chamfering process is performed linearly along a line connecting a contour line of a wafer and an inner contact point of a common inscribed circle of the cutout portion or in a region outside thereof. The wafer according to claim 1, wherein