JPH07101737B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH07101737B2 JPH07101737B2 JP60291399A JP29139985A JPH07101737B2 JP H07101737 B2 JPH07101737 B2 JP H07101737B2 JP 60291399 A JP60291399 A JP 60291399A JP 29139985 A JP29139985 A JP 29139985A JP H07101737 B2 JPH07101737 B2 JP H07101737B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- impurity concentration
- conductivity type
- concentration layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 title description 10
- 239000012535 impurity Substances 0.000 claims description 34
- 239000000126 substance Substances 0.000 claims description 2
- 108091006146 Channels Proteins 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は電力用スイッチング素子として用いる電導度変
調型の半導体装置に関する。Description: TECHNICAL FIELD The present invention relates to a conductivity modulation type semiconductor device used as a power switching element.
近年、電力用スイッチング素子として、絶縁ゲート型ト
ランジスタ、または電導度変調型MOSFETなどと呼ばれる
素子が注目されている。In recent years, an element called an insulated gate transistor or a conductivity modulation type MOSFET has been attracting attention as a power switching element.
この素子の基本構成を第２図に示す。この構造は、縦型
DMOSといわれるパワーMOSFETのドレイン領域となるn+層
をp+層に置き換えたものということができる。The basic structure of this element is shown in FIG. This structure is vertical
It can be said that the n + layer, which is the drain region of the power MOSFET called DMOS, is replaced with the p + layer.
即ち、p+基板１（第１領域）の上の低不純物濃度のn-層
２を形成し、このn-層２の表面部に選択的にｐ層３を、
さらにこのｐ層３の表面部に選択的にn+層４を形成し、
ｐ層３のn-層２とn+層４で挟まれた表面領域をチャネル
領域としてこの上にゲート絶縁膜５を介してゲート電極
６を形成する。さらに、ｐ層３とn+層４にまたがるよう
にソース電極７を形成し、ドレイン電極８を形成する。
この素子の動作を以下説明する。That is, a low impurity concentration n − layer 2 is formed on the p + substrate 1 (first region), and the p layer 3 is selectively formed on the surface of the n − layer 2.
Further, an n + layer 4 is selectively formed on the surface of the p layer 3,
A gate electrode 6 is formed on the surface region of the p layer 3 sandwiched by the n − layer 2 and the n + layer 4 as a channel region with a gate insulating film 5 interposed therebetween. Further, the source electrode 7 and the drain electrode 8 are formed so as to extend over the p layer 3 and the n + layer 4.
The operation of this element will be described below.
ソース電極７をアースし、ゲート電極６およびドレイン
電極８に正の電圧を加えると、ゲート電極６の直下のｐ
層３の表面部が反転してｎ型のチャネルができるため
に、電流が流れる。このときにドレイン側p+層１からn-
層２に少数キャリアの注入が起こることで電導度変調の
効果により、n-層２の領域の抵抗を低くする。この素子
はオン状態で、このように低いオン抵抗を提供するが、
反面その構造から寄生サイリスタ構造に基づくラッチン
グという現象が大きな欠点となっている。次にラッチン
グ現象について説明する。When the source electrode 7 is grounded and a positive voltage is applied to the gate electrode 6 and the drain electrode 8, p just below the gate electrode 6
An electric current flows because the surface of the layer 3 is inverted to form an n-type channel. At this time, drain side p + layer 1 to n −
The injection of minority carriers into the layer 2 lowers the resistance in the region of the n − layer 2 due to the effect of conductivity modulation. In the on-state, this device provides such a low on-resistance,
On the other hand, due to its structure, the phenomenon of latching based on the parasitic thyristor structure is a major drawback. Next, the latching phenomenon will be described.
第３図にこの素子の等価回路を示す。この素子中には２
つの寄生トランジスタTr1，Tr2が存在する。Tr1，Tr2に
よりできるサイリスタはTr1の電流増幅率α1とTr2の電
流増幅率α2の和がα1＋α2≧１となったときにサイリ
スタ機能によりラッチングしてしまう。このように寄生
のサイリスタがラッチングしてしまうと、電流はチャネ
ル領域域外のｐ層３の領域中を流れるので、ゲート電圧
による電流制御ができなくなる。このような現象を起き
にくくするためには第３図における抵抗Rbを小さくする
ことが有効である。すなわち抵抗Rbを下げることでα2
を小さくでき、ラッチングしにくい素子にすることが可
能となる。そのためには、抵抗Rbはｐ層３の横方向に流
れる電流の抵抗であるからｐ層３を高不純物濃度にして
抵抗を下げることが有効であるが、チャネル領域まで高
不純物濃度にしてしまうとゲート閾値電圧の上昇やオン
抵抗の上昇などデメリットも大きい。FIG. 3 shows an equivalent circuit of this element. 2 in this element
There are two parasitic transistors Tr 1 and Tr 2 . Thyristor can by Tr 1, Tr 2 ends up latching by thyristor function when the sum of the current amplification factor alpha 2 in the current gain alpha 1 and Tr 2 of Tr 1 becomes α 1 + α 2 ≧ 1. When the parasitic thyristor latches in this way, the current flows in the region of the p layer 3 outside the channel region, so that it becomes impossible to control the current by the gate voltage. In order to make such a phenomenon less likely to occur, it is effective to reduce the resistance R b in FIG. That is, by lowering the resistance R b , α 2
Can be made small, and it becomes possible to make an element which is difficult to latch. For that purpose, since the resistance R b is the resistance of the current flowing in the lateral direction of the p layer 3, it is effective to make the p layer 3 have a high impurity concentration to reduce the resistance, but the channel region also has a high impurity concentration. There are also major disadvantages such as an increase in gate threshold voltage and an increase in on-resistance.
これを解決する方法として第４図の絶縁ゲート型トラン
ジスタの断面図で示す構成のものが提案されている。こ
れによると、チャネル領域を覆わないようにp+層10をｐ
層３に重ねて形成することで、チャネル領域の不純物濃
度を上げることなく抵抗Rbを低減することができる。し
かし、この方法ではフォトエッチングの精度によってｐ
層３とp+層10との間隔が制限されてしまうので抵抗Rbの
低減には限界があった。As a method for solving this, the structure shown in the sectional view of the insulated gate transistor in FIG. 4 has been proposed. According to this, the p + layer 10 is p so as not to cover the channel region.
By forming it over the layer 3, the resistance R b can be reduced without increasing the impurity concentration of the channel region. However, in this method, p depends on the accuracy of photoetching.
Since the distance between the layer 3 and the p + layer 10 is limited, the reduction of the resistance R b is limited.
本発明は上記欠点を除去して、低いゲート閾値電圧と低
いオン電圧を維持しながら、十分に大きなラッチング電
流を可能にした電導度変調型の半導体装置の製造方法を
提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above drawbacks and provide a method of manufacturing a conductivity modulation type semiconductor device which enables a sufficiently large latching current while maintaining a low gate threshold voltage and a low ON voltage. .
〔発明の要点〕 本発明は、上述の目的を達成するため、第１導電型の第
１領域と、該第１領域の一面上に形成される第２導電型
の第２領域と、該第２領域の表面部に選択的に形成され
る第１導電型の第３領域と、該第３領域の表面部に選択
的に形成される第２導電型の第４領域と、前記第１領域
の他面に接続されるドレイン電極と、前記第２領域と第
４領域の間の第３領域の表面部をチャネル領域としてそ
の上に絶縁膜を介して形成されるゲート電極と、前記第
３領域及び第４領域の表面に接続されるソース電極とを
備え、前記チャネル領域の不純物濃度が前記第３領域の
他の部分より低濃度にされる半導体装置の製造方法にお
いて、前記第１領域の一面上に第２導電型の低不純物濃
度層を形成し、この低不純物濃度層上に第２導電型の高
不純物濃度層を全面に形成することにより低不純物濃度
層及び高不純物濃度層からなる前記第２領域を形成する
工程と、前記高不純物濃度層の表面から前記低不純物濃
度層内に達するように第１導電型の不純物を選択的に拡
散することにより前記第３領域を形成する工程と、この
第３領域の表面部に選択的に前記第４領域を形成する工
程とを備えることを特徴としている。In order to achieve the above object, the present invention provides a first region of the first conductivity type, a second region of the second conductivity type formed on one surface of the first region, and a second region of the first region. A third region of the first conductivity type selectively formed on the surface of the second region, a fourth region of the second conductivity type selectively formed on the surface of the third region, and the first region A drain electrode connected to the other surface, a gate electrode formed on the surface portion of the third region between the second region and the fourth region as a channel region with an insulating film therebetween, and the third electrode. A source electrode connected to the surfaces of the first region and the fourth region, wherein the impurity concentration of the channel region is lower than that of other portions of the third region. A second conductivity type low impurity concentration layer is formed on one surface, and a second conductivity type high impurity concentration layer is formed on this low impurity concentration layer. Forming a second region composed of a low impurity concentration layer and a high impurity concentration layer by forming a pure substance concentration layer on the entire surface; and so as to reach the inside of the low impurity concentration layer from the surface of the high impurity concentration layer. The method further comprises: a step of forming the third region by selectively diffusing an impurity of the first conductivity type; and a step of selectively forming the fourth region on a surface portion of the third region. There is.
以下、本発明の一実施例を図面を用いて詳細に説明す
る。An embodiment of the present invention will be described in detail below with reference to the drawings.
第１図，第５図は各々、本発明の半導体装置の異なる一
実施例の要部断面図であり、これを製造工程にそって説
明する。まず、第１図に示すようにp+基板１に不純物濃
度が１×1014cm-3n-層２を気相成長法によって形成す
る。次にn-層２の表面に１〜２μｍ厚程度で表面不純物
濃度が８×1017cm-3のn+層９をイオン注入法または気相
成長法によって形成する。次に選択拡散法によってドー
ズ量が３×1014atoms/cm2の条件でイオン注入し５μｍ
程度の深さにドライブ拡散してp+層11を形成する。この
段階で、チャネル領域がｐ型の導電型になり、その表面
不純物濃度を調べたところ２×1017cm-3程度であった。
このような構成をとることでn+層９の不純物濃度と深さ
を変更すれば、チャネル領域の抵抗および深さを任意に
設定することが可能となる。FIG. 1 and FIG. 5 are cross-sectional views of the essential parts of a semiconductor device according to another embodiment of the present invention, which will be described along with the manufacturing process. First, as shown in FIG. 1, an impurity concentration of 1 × 10 14 cm −3 n − layer 2 is formed on ap + substrate 1 by a vapor phase epitaxy method. Next, an n + layer 9 having a surface impurity concentration of 8 × 10 17 cm −3 and having a thickness of about 1 to 2 μm is formed on the surface of the n − layer 2 by an ion implantation method or a vapor phase growth method. Next, by selective diffusion method, ion implantation is performed under the condition of a dose amount of 3 × 10 14 atoms / cm 2 and 5 μm.
The p + layer 11 is formed by drive diffusion to a certain depth. At this stage, the channel region became a p-type conductivity type, and the surface impurity concentration thereof was examined and found to be about 2 × 10 17 cm −3 .
With such a structure, if the impurity concentration and the depth of the n + layer 9 are changed, the resistance and the depth of the channel region can be set arbitrarily.
さらに、p+層11の表面にn+層４を選択形成する。そして
ゲート絶縁膜５を形成し、ゲート絶縁膜５に選択的に穴
あけを行い、n+層４とp+層11に共通のソース電極７を形
成し、ゲート絶縁膜５を介してゲート電極６を形成す
る。最後にドレイン電極８を形成して完成する。Further, the n + layer 4 is selectively formed on the surface of the p + layer 11. Then, a gate insulating film 5 is formed, holes are selectively formed in the gate insulating film 5, a common source electrode 7 is formed in the n + layer 4 and the p + layer 11, and a gate electrode 6 is formed through the gate insulating film 5. To form. Finally, the drain electrode 8 is formed and completed.
n+層９は、その後のp+層11及びn+層４の形成にともなっ
て深く形成されていく。このn+層９によりn-層２の表面
は低抵抗化され、第３図の等価回路でいえば寄生トラン
ジスタTr2のベース抵抗を低くすることに相当し、チャ
ネル領域への電流をより流れやすくし、ドレイン・ソー
ス間のオン電圧を低減することができる。The n + layer 9 is formed deeper as the p + layer 11 and the n + layer 4 are subsequently formed. The surface of the n − layer 2 is made low in resistance by the n + layer 9, which is equivalent to lowering the base resistance of the parasitic transistor Tr 2 in the equivalent circuit of FIG. It is possible to make it easier and reduce the on-voltage between the drain and the source.
またp+層11の不純物濃度を高くすることで抵抗Rbを下げ
ラッチング電流の十分大きな素子をつくることができ、
ゲート電圧により制御できる電流の大きな素子とするこ
とができる。Further, by increasing the impurity concentration of the p + layer 11, it is possible to reduce the resistance Rb and to make a device with a sufficiently large latching current.
The device can have a large current that can be controlled by the gate voltage.
この実施例では、n+層９、p+層11及びn+層４の形成後に
ゲート絶縁膜５及びゲート電極６を形成しているが、n+
層９の形成後にゲート絶縁膜５及びゲート電極６を形成
しこのゲート電極６をマスクとして行うセルフアライン
によってp+層11及びn+層４を形成してもよい。In this embodiment, although a gate insulating film 5 and gate electrode 6 after formation of the n + layer 9, p + layer 11 and n + layer 4, n +
After forming the layer 9, the gate insulating film 5 and the gate electrode 6 may be formed, and the p + layer 11 and the n + layer 4 may be formed by self-alignment using the gate electrode 6 as a mask.
第５図は、本発明の異なる実施例である。本実施例で
は、p+層11のチャネル領域を覆わないようにp+層10を選
択的に形成している。これによってソース電極７との接
触部が低抵抗に維持できるために、オーミック接触が良
好になる。FIG. 5 is a different embodiment of the present invention. In this embodiment, the p + layer 10 is selectively formed so as not to cover the channel region of the p + layer 11. As a result, the contact portion with the source electrode 7 can be maintained at a low resistance, so that ohmic contact becomes good.
また、p+層10の深さをp+層11より深く設定することで、
オフ状態における電界集中を緩和でき、順方向耐圧の高
い構造とすることができる。Also, by setting the depth of the p + layer 10 deeper than that of the p + layer 11,
The electric field concentration in the off state can be relaxed, and the structure can have a high forward breakdown voltage.
以上のような本発明によれば、第１導電型の第１領域の
一面上に第２導電型の低不純物濃度層を形成し、この低
不純物濃度層上に第２導電型の高不純物濃度層を全面に
形成することにより低不純物濃度層及び高不純物濃度層
からなる第２導電型の第２領域を形成するようにしたの
で、複雑な工程を用いることなく従来の工程に第２導電
型の高不純物濃度層を全面に形成する工程を追加するこ
とで、第３領域に隣接する第２領域の表面部を低抵抗に
することができ、これは等価回路のPNPトランジスタの
ベース抵抗を低くすることに相当し、チャネル領域への
電流をより流れ易くしてドレイン・ソース間のオン電圧
を低減することができると共に、その工程によりチャネ
ル領域の抵抗及び深さを設定して低いゲート閾値電圧を
得ることができる。According to the present invention as described above, the second conductivity type low impurity concentration layer is formed on one surface of the first conductivity type first region, and the second conductivity type high impurity concentration is formed on the low impurity concentration layer. Since the second region of the second conductivity type composed of the low impurity concentration layer and the high impurity concentration layer is formed by forming the layer on the entire surface, the second conductivity type can be formed in the conventional process without using a complicated process. By adding the step of forming the high impurity concentration layer on the entire surface, the surface portion of the second region adjacent to the third region can have a low resistance, which lowers the base resistance of the PNP transistor of the equivalent circuit. The ON voltage between the drain and the source can be reduced by facilitating the flow of the current to the channel region, and the resistance and depth of the channel region can be set by the process to lower the gate threshold voltage. Can be obtained.
従って、低いオン電圧及び低いゲート閾値電圧を維持し
ながらラッチング電流を大きくしてゲート電圧による電
流制御能力を高めた半導体装置を製造することができ
る。Therefore, it is possible to manufacture a semiconductor device in which the latching current is increased while maintaining the low on-voltage and the low gate threshold voltage to enhance the current control capability by the gate voltage.
第１図は本発明の一実施例の電導度変調型絶縁ゲート型
トランジスタの要部断面図、第２図は従来の絶縁ゲート
型トランジスタの要部断面図、第３図は第２図のトラン
ジスタの等価回路図、第４図は従来の電導度変調型トラ
ンジスタの要部断面図、第５図は本発明の別の実施例を
示す図である。 １……p+基板（第１領域）、２……n-層（第２領域の高
不純物濃度）、３……ｐ層（第３領域）、４……n+層
（第４領域）、５……ゲート絶縁膜、６……ゲート電
極、７……ソース電極、８……ドレイン電極、９……n+
層（第２領域の高不純物濃度層）、11……p+層（第３領
域）。FIG. 1 is a sectional view of an essential part of an electric conductivity modulation type insulated gate transistor according to an embodiment of the present invention, FIG. 2 is a sectional view of an essential part of a conventional insulated gate transistor, and FIG. 3 is the transistor of FIG. Is an equivalent circuit diagram of FIG. 4, FIG. 4 is a sectional view of a main part of a conventional conductivity modulation type transistor, and FIG. 5 is a diagram showing another embodiment of the present invention. 1 ... p + substrate (first region), 2 ... n - layer (high impurity concentration in the second region), 3 ... p layer (third region), 4 ... n + layer (fourth region) 5 ... Gate insulating film, 6 ... Gate electrode, 7 ... Source electrode, 8 ... Drain electrode, 9 ... N +
Layer (high impurity concentration layer in the second region), 11 ... p + layer (third region).
Claims (1)
面上に形成される第２導電型の第２領域と、該第２領域
の表面部に選択的に形成される第１導電型の第３領域
と、該第３領域の表面部に選択的に形成される第２導電
型の第４領域と、前記第１領域の他面に接続されるドレ
イン電極と、前記第２領域と第４領域の間の第３領域の
表面部をチャネル領域としてその上に絶縁膜を介して形
成されるゲート電極と、前記第３領域及び第４領域の表
面に接続されるソース電極とを備え、前記チャネル領域
の不純物濃度が前記第３領域の他の部分より低濃度にさ
れる半導体装置の製造方法において、前記第１領域の一
面上に第２導電型の低不純物濃度層を形成し、この低不
純物濃度層上に第２導電型の高不純物濃度層を全面に形
成することにより低不純物濃度層及び高不純物濃度層か
らなる前記第２領域を形成する工程と、前記高不純物濃
度層の表面から前記低不純物濃度層内に達するように第
１導電型の不純物を選択的に拡散することにより前記第
３領域を形成する工程と、この第３領域の表面部に選択
的に前記第４領域を形成する工程とを備えることを特徴
とする半導体装置の製造方法。1. A first region of a first conductivity type, a second region of a second conductivity type formed on one surface of the first region, and selectively formed on a surface portion of the second region. A third region of the first conductivity type, a fourth region of the second conductivity type selectively formed on a surface portion of the third region, a drain electrode connected to the other surface of the first region, A gate electrode formed on the surface of the third region between the second region and the fourth region as a channel region via an insulating film, and a source connected to the surfaces of the third and fourth regions. A method of manufacturing a semiconductor device, comprising: an electrode, wherein the impurity concentration of the channel region is lower than that of other portions of the third region, wherein a second conductivity type low impurity concentration layer is formed on one surface of the first region. Is formed, and a second-conductivity-type high impurity concentration layer is formed on the entire surface of the low impurity concentration layer Forming the second region composed of a pure substance concentration layer and a high impurity concentration layer; and selectively diffusing impurities of the first conductivity type from the surface of the high impurity concentration layer to reach the low impurity concentration layer. A method of manufacturing a semiconductor device, comprising: a step of forming the third region by doing so; and a step of selectively forming the fourth region on a surface portion of the third region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60291399A JPH07101737B2 (en) | 1985-12-24 | 1985-12-24 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60291399A JPH07101737B2 (en) | 1985-12-24 | 1985-12-24 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62150769A JPS62150769A (en) | 1987-07-04 |
| JPH07101737B2 true JPH07101737B2 (en) | 1995-11-01 |
Family
ID=17768393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60291399A Expired - Fee Related JPH07101737B2 (en) | 1985-12-24 | 1985-12-24 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07101737B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6477173A (en) * | 1987-09-18 | 1989-03-23 | Nec Corp | Vertical mosfet |
| JP2604777B2 (en) * | 1988-01-18 | 1997-04-30 | 松下電工株式会社 | Manufacturing method of double diffusion type field effect semiconductor device. |
| JP2643966B2 (en) * | 1988-01-23 | 1997-08-25 | 松下電工株式会社 | Manufacturing method of double diffusion type field effect semiconductor device. |
| JP2771172B2 (en) * | 1988-04-01 | 1998-07-02 | 日本電気株式会社 | Vertical field-effect transistor |
| JPH01262668A (en) * | 1988-04-13 | 1989-10-19 | Mitsubishi Electric Corp | Field-effect type semiconductor device |
| JPH02163974A (en) * | 1988-12-16 | 1990-06-25 | Mitsubishi Electric Corp | Insulated-gate type bipolar transistor and its manufacture |
| JPH03129743A (en) * | 1989-07-07 | 1991-06-03 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| JPH05160407A (en) * | 1991-12-09 | 1993-06-25 | Nippondenso Co Ltd | Vertical insulating gate type semiconductor device and manufacture thereof |
| JP4304332B2 (en) * | 2003-10-03 | 2009-07-29 | 独立行政法人産業技術総合研究所 | Silicon carbide semiconductor device |
| EP2530721A4 (en) * | 2010-01-29 | 2017-11-29 | Fuji Electric Co., Ltd. | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IE55992B1 (en) * | 1982-04-05 | 1991-03-13 | Gen Electric | Insulated gate rectifier with improved current-carrying capability |
-
1985
- 1985-12-24 JP JP60291399A patent/JPH07101737B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62150769A (en) | 1987-07-04 |
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