JPH07104660B2 - Video RAM access control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] CRT displays, liquid crystal displays, etc. are used as computer display devices, but since both have different screen scanning methods, they are the same in the prior art. The control circuit and video RAM (hereinafter referred to as VRAM) cannot be used. On the other hand, personal computers and the like are becoming more portable and have lower power consumption, and there is an increasing demand for connection of flat displays (liquid crystal displays) in addition to conventional CRT displays.

[Object of the Invention]

The present invention meets the above-mentioned demand, and is the same VRAM used for the display of a CRT display.
It is an object of the present invention to provide a video RAM access control system that can be shared by other displays (for example, liquid crystal displays) having different screen scanning methods.

[Means for achieving the purpose]

Therefore, the video RAM access control system of the present invention comprises: a register (1) in which a display start address is set; an address counter (2) whose contents are incremented by 1 each time a clock is input; The latch (9) for latching the contents of (2), the addition value setting circuit (4) for setting the addition value to be added to the contents of the address counter (2), and the address counter (2) Specified by an adder (3) that adds the content and the value output by the addition value setting circuit (4), a video RAM (6), and the output of the adder (3) in the video RAM (6). Display (7,
8) and, provided that the content of the register (1) is synchronized with the clock, provided that the signal applied to the predetermined control terminal (LD) of the address counter (2) has a predetermined value.・
The content of the address counter (2) is synchronized with the clock, provided that the signal loaded in the counter (2) and applied to the predetermined control terminal (LD) of the latch (2) has a predetermined value. (9)
The signal applied to the other predetermined control terminal (OE) of the latch (9) has a predetermined value and the signal applied to the predetermined control terminal (LD) of the address counter (2) has a predetermined value. If the value is a value, the contents of the latch (9) are loaded into the address counter (2) in synchronization with the clock, and when the addition value output instruction signal has a predetermined value, the addition value setting circuit (4) The addition value set is output from the addition value setting circuit (4), and a 0 value is output from the addition value setting circuit (4) when the addition value output instruction signal is not a predetermined value. Is.

Example of Invention

Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. In FIG.
1 is a register, 2 is an address counter, 3 is an adder,
4 is an addition value setting circuit, 5 is a timing generator,
6 is VRAM, 7 is a CRT display, 8 is a liquid crystal display, and 9 is a latch. In FIG. 1, a register 1 is a register for setting a display start address SA of the VRAM 6 which holds data to be displayed on the displays 7 and 8, and a value is set by the processor via the information bus A. The output B of the register 1 is used as the start address of the screen display and the VRAM address and
The counter 2 is set, and the counter 2 is counted up by the timing signal a at a display interval of 1 word (16 bits). The VRAM 6 holds display data corresponding to the dots on the screen of the display device in a one-to-one correspondence. The address E given to the VRAM 6 is obtained as a result of adding the output C of the counter 2 and the output D from the addition value setting circuit 4 by the adder 3, and the VRAM corresponding to the address.
Output is displayed on the display device 7,8. Also,
The output C of the counter 2 is latched by the latch circuit 9 with the timing signals a and d, and at the same time the output F is generated with the timing signal c ', it is set again in the counter 2 by the timing signals c'and a. However, the resetting to the counter 2 is effective only when the display selection signal e is logic "1". Further, an addition value is set in advance in the adder setting circuit 4 by the processor via the information bus A, and the timing signal f is output to the bus D each time it is output from the timing generator 5. However, this output is also effective only when the display selection signal e is logic "1". The timing signals a, b, c (or c '), d, f are all generated by the timing generator 5. LD is a load terminal, CK is a clock terminal, and OE is an out enable terminal.

In order to make the explanation easy to understand, a CRT display is an example of a display device that does not require screen division,
Let us consider a liquid crystal display as an example of a display device that requires screen division, and each has a dot configuration of 640 × 200 dots. Second correspondence between VRAM and screen at this time
Shown in Figures and 3.

Reference numeral 6 in FIG. 2 indicates a VRAM, and when the display start address SA is set in the register 1 in FIG. 1, 640 × 200 dots = 8000
A region 6a corresponding to a word (one word is 16 dots) is designated.
The contents of the addresses from the display start address SA to SA + 7999 in the area 6a correspond to the display of 40 words in the horizontal direction and 200 lines in the vertical direction on the screen of FIG. In case of CRT display 7, SA + 7 in order from SA
The contents up to 999 are displayed. On the other hand, although there are various scanning methods for the liquid crystal display 8, as an example, it is assumed that the liquid crystal display 8 is divided into upper and lower parts and the upper and lower screens are displayed for each line. That is, SA + 4000 to SA + 4039 are displayed next to SA to SA + 39, and SA + 40 to SA + 79 are displayed in this order.

FIG. 4 is a diagram showing the timing of the embodiment of the present invention.
a is a timing clock, and b is a timing signal output each time the screen display is started to set SA in the counter 2. On the other hand, SA is set in the latch 9 by the clock a while the timing signal d is being output.
The output of the counter 2 is SA + 1, ... SA + 39 depending on the clock a.
The latch output F is set in the counter 2 by the clock a while the timing signal c is being output, and the process steps again to SA, SA + 1, ... SA + 79. When the output of the counter 2 is SA + 40, the timing signal d is output and SA + 40 is set in the latch 9, so that SA + 40 is set in the counter 2 again. When the timing signal f is logic "1", the added value 4000 ₁₀ is input to the adder 3, so the output E of the adder 3 is SA to SA + 39, SA + 4000 to SA + 403.
9, SA + 40 to SA + 79, etc. are displayed on the screen in the order of 1 line, 101 line, 2 line, 102 line. On the other hand, when the display selection signal e is set to logic "0", the timing signal c'is not output, and therefore the reset by the timing signal c of the counter 2 is not performed, and the added value is always 0. Output up to the line in order. This enables the CRT display 7 to be displayed. In this embodiment, one line is 40
Although words have been taken as an example, it is possible to realize an arbitrary number of words, and therefore, the present invention is not limited to two divisions and is similarly applicable to a display of a plurality of divisions (including vertical and horizontal).
In addition, by changing the addition value, the present invention can be applied to displays having different dot configurations.

〔The invention's effect〕

As is clear from the above description, according to the present invention, CR
A display that does not require screen division such as a T display and a display that requires screen division such as a liquid crystal display can be displayed using a common VRAM, and it is easy to select a display according to the application. Can be realized economically.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the correspondence between VRAMs and screens, and FIG. 4 is a diagram showing the timing of the embodiment of the present invention. 1 ... Register, 2 ... Address counter, 3 ... Adder, 4 ... Addition value setting circuit, 5 ... Timing generator, 6 ... VRAM, 7 ... CRT display, 8 ...
… Liquid crystal display, 9 …… Latch.

Claims (1)

[Claims] 1. A register (1) in which a display head address is set, an address counter (2) whose contents are incremented by 1 each time a clock is input, and contents of the address counter (2) are latched. Latch (9), an addition value setting circuit (4) for setting an addition value to be added to the contents of the address counter (2), the contents of the address counter (2) and the addition value setting circuit An adder (3) for adding the value output from (4), a video RAM (6), and the contents of the address designated by the output of the adder (3) in the video RAM (6) are displayed. Display (7,
8) and, provided that the content of the register (1) is synchronized with the clock, provided that the signal applied to the predetermined control terminal (LD) of the address counter (2) has a predetermined value.・
The content of the address counter (2) is synchronized with the clock, provided that the signal loaded in the counter (2) and applied to the predetermined control terminal (LD) of the latch (2) has a predetermined value. (9)
The signal applied to the other predetermined control terminal (OE) of the latch (9) has a predetermined value and the signal applied to the predetermined control terminal (LD) of the address counter (2) has a predetermined value. If the value is a value, the contents of the latch (9) are loaded into the address counter (2) in synchronization with the clock, and when the addition value output instruction signal has a predetermined value, the addition value setting circuit (4) The added value set is output from the added value setting circuit (4), and a 0 value is output from the added value setting circuit (4) when the added value output instruction signal is not a predetermined value. RAM access control method.