JPH0651863A - Serial data communication controller - Google Patents

Abstract

PURPOSE:To extremely easily inform a CPU of that operation clock stop setting becomes invalid during communication. CONSTITUTION:Data to be transmitted to a communication equipment 2 are previously written in a transmitting data buffer and in a normal operating state, however, a communication state signal 103 to be outputted from the communication equipment 2 is outputted at a '1' level and inputted to a clock controller 3 in the state of performing transmission/reception at the communication equipment 2 and in the case of remaining the transmitting data in the transmitting data buffer. In the case of inputting this communication state signal 103 at the '1' level to the clock controller 3 and setting the stop of an operation clock 101 from a CPU 1, an interruption request signal 102 inputted from the clock controller 3 to the CPU 1 is outputted at the '1' level and at the CPU 1, it is detected that the operation clock stop setting becomes invalid.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data communication control device, and more particularly to a serial data communication control device used for transmitting serial data in a microcomputer system.

[0002]

2. Description of the Related Art Generally, in a microcomputer system composed of CMOS, in order to reduce power consumption outside the operating time of the system, the operation of the operating clock is controlled during the outside of the operating time. It has a clock control circuit. Further, in recent years, application devices and the like using a plurality of microcomputers are increasing, and it is an essential condition to provide a network for mutual communication between systems using each microcomputer. . For this reason, each microcomputer system is generally equipped with a serial data communication function by the network.

FIG. 6 shows an example of the configuration of a serial data communication controller in a conventional microcomputer system. As shown in FIG. 6, the serial data communication control device includes a CPU 21, a communication device 22, and a clock control device 23 including a crystal oscillator 24, and a predetermined system reset signal 105. The operation is started by the initialization via the CPU, and the CPU 21 performs the data calculation and the control operation for the communication device 22 and the clock control device 23, which will be described later, based on a predetermined program. The communication device 22 is connected to the CPU 21 via the address / data bus 201,
Controlled by 1, the serial data is transmitted and received via the Tx terminal and the Rx terminal, respectively. Further, the communication device 22 has a transmission data buffer built therein, and if the data to be transmitted is written in the transmission data buffer in advance, these data are transmitted in a predetermined order. Is configured.

The clock controller 23 is connected to the CPU 21 via an address / data bus 201,
It is controlled and operated by the CPU 21. The clock control device 23 is provided with a crystal oscillator including a crystal oscillator 24, and an operation clock 101 used in the entire microcomputer system is generated and input to the CPU 21 and the communication device 22, respectively. Further, the clock control device 23 has a function of stopping the operation clock 101 in order to reduce power consumption.
When the state in which the operation clock 101 is stopped is set in the clock control device 23 by the control action of the CPU 21, the operation clock 101 is stopped, whereby the operation clock 101 is stopped.
The microcomputer system is in a low power consumption state. The stop state of the operation clock 101 is
The oscillation stop release signal 106 is input to release the oscillation stop release signal 106, and the supply of the operation clock 101 by the clock controller 23 is restarted.

[0005]

In the above conventional data communication control device, when the operation clock 101 is stopped by the control action of the CPU 21, the operations of the CPU 21 and the communication device 22 are also stopped. However,
In the communication device 22, the operation clock 101 cannot be stopped in operation during transmission or reception of serial data and in a state where data to be transmitted is written in the transmission data buffer. The reason is that if the receiving operation is stopped during transmission, the communication protocol is disturbed and the network is adversely affected. Further, since the data already written in the transmission data buffer is the data itself to be transmitted, it is necessary to stop the operation after transmitting all the data. Therefore, in the CPU 21, before the operation clock 101 is stopped, the communication device 2
From 2, it is necessary to confirm the communication state of transmission and reception and the presence or absence of transmission data in the transmission data buffer. In addition, a judgment circuit is required to prevent the next reception operation from being performed after the confirmation of these states and before the operation clock 101 is stopped. As a result, the control program in the CPU 21 becomes complicated and the control circuit itself has a complicated circuit configuration.

[0006]

A serial data communication control device of the present invention comprises a communication device for transmitting / receiving serial data, a CPU, and an operation clock signal supplied to the communication device and the CPU. In a serial data communication control device including at least a clock control device for generating, a transmission data storage means for storing transmission data scheduled for transmission in advance, and a transmission data storage means for storing the transmission data. Transmission data detecting means for detecting the presence or absence of transmission data and outputting a predetermined detection signal,
A transmission / reception control unit that performs an operation including transmission and reception of serial data, and outputs a transmission operation state signal and a reception operation state signal indicating respective operation states at the time of transmission and reception of the serial data. Detecting that either the detection signal output from the transmission data detection means or the transmission operation status signal or the reception operation status signal output from the transmission reception control means is output, and the communication operation status signal is output. At least the communication state detecting means for outputting is provided in at least the communication device, the clock signal generating means for generating and outputting the operation clock signal, and the operation clock signal by the CPU during the output of the communication operation state signal. Operation clock control means for invalidating the stop setting of the operation clock signal when the setting operation to stop is performed At least the clock control device includes an interrupt signal generation unit that outputs a predetermined interrupt request signal to the CPU when the operation clock control unit invalidates the stop setting of the operation clock signal. Consists of

The communication device includes a transmission data storage unit for storing transmission data scheduled for transmission in advance,
A transmission data detection unit that detects the presence or absence of transmission data stored in the transmission data storage unit and outputs a predetermined detection signal, and an operation including transmission and reception of serial data, and the serial data And a reception data storage for storing reception data received by the transmission / reception control means when transmitting and receiving, respectively. Means, a detection signal output from the transmission data detection means, and detecting that one of the transmission operation state signal and the reception operation state signal output from the transmission reception control means is output,
It may be configured to include at least a communication state detection unit that outputs a communication operation state signal.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment comprises a CPU 1, a communication device 2, and a clock control device 3 including a crystal oscillator 4 corresponding to an address / data bus 201. 2 and FIG. 3 are block diagrams showing the internal configurations of the communication device 2 and the clock control device 3, respectively, and FIG.
Shown in (b), (c) and (d) are timing charts of signals indicating the operation in this embodiment.

In FIG. 1, the main functions of the CPU 1, the communication device 2 and the clock control device 3 are basically the same as in the case of the above-mentioned conventional example, but the present invention is applied to the exchange of signals between each other. There are unique features. C
The PU 1, the communication device 2, and the clock control device 3 are initialized by the system reset signal 105 and their operations are started. Data to be transmitted to the communication device 2 is written in the transmission data buffer in advance,
In the normal operation state of the present embodiment, the communication device 2 is transmitting and receiving, and the transmission data
When the transmission data remains in the buffer, the communication status signal 103 output from the communication device 2 is output at the “1” level and input to the clock control device 3. When the communication state signal 103 is input to the clock control device 3 at "1" level, and when C
When the stop of the operation clock 101 is set from PU1 via the address / data bus 201,
The interrupt request signal 102 input from the clock controller 3 to the CPU 1 is output as a "1" level signal.

FIG. 2 is a block diagram showing the internal structure of the communication device 2. As shown in FIG.
The buffer 5 includes a transmission data detection device 6, a transmission / reception control device 7, and an OR circuit 8. The transmission data buffer 5 is input from the CPU 1 via an address / data bus 201. The transmission data to be written is written. Whether or not the transmission data is stored in the transmission data buffer 4 is detected by the transmission data detecting device 6, and when the transmission data buffer 4 has the data, the transmission data detection is performed as described above. A “1” level is output from the device 6 and input to the OR circuit 8.
Further, the transmission / reception control device 7 receives the transmission data input from the transmission data buffer 5, transmits the serial data via the Tx terminal, and
Serial data is received via the Rx terminal. The received serial data is sent to the CPU 1 via the address / data bus 201. In this case, in the state where the transmission is being performed via the transmission / reception control device 7 and the state where the reception is being performed, T
Both the xF signal 108 and the RxF signal 109 are “1”.
It is output as a level signal and input to the OR circuit 8. Therefore, when transmission / reception is being performed via the transmission / reception control device 7 and when transmission data remains in the transmission data buffer 5, the communication state signal 103 output from the OR circuit 8 is It is always output at "1" level.

FIG. 3 is a block diagram showing the internal structure of the clock control device 3. As shown in FIG. 3, an inverter 9, AND circuits 10 and 16, a NOR circuit 11, and a latch circuit 12 are provided. , The frequency divider 13 and the oscillator 14
And a crystal oscillator 4 are included. CPU1
When the stop of the operation clock 101 is set through the control action of the CPU, the CPU is connected via the address / data bus 201.
The write clock signal 104 input from 1 goes to "1" level, and the corresponding bus line in the address / data bus 201 goes to "1" level. At this point, the communication status signal 103 input from the communication device 2
Is at "0" level, the write signal output from the AND circuit 10 and input to the CK terminal of the latch circuit 12 becomes "1" level, and this "1" level is written. When the "1" level is output from the Q terminal of the latch circuit 12, the oscillation of the crystal oscillation circuit including the oscillator 14 and the crystal oscillator 4 is stopped. This oscillator 14
The clock 107 generated in 1 is sent to the frequency divider 13 and is frequency-divided to generate the operation clock 101.

In this case, transmission or reception is being performed in the communication device 2, or transmission data remains in the transmission data buffer 5 (see FIG. 2), and the OR circuit 8 is used.
When the operation of stopping the operation clock 101 is performed by the CPU 1 while the communication status signal 103 input to the clock control device 3 via the CPU 1 is at the “1” level, the AND circuit 16 outputs it to the CPU 1. The interrupt request signal 102 to be input becomes the "1" level and the C
The fact that the operation clock 101 could not be stopped is transmitted to PU1. Further, in this case, since the output of the AND circuit 10 becomes the “0” level and the “1” level is not written in the latch circuit 12, the oscillation of the oscillator 14 cannot be stopped, The operation clock 101 cannot be stopped.

4 (a), (b), (c) and (d)
As described above, it is a timing chart of signals showing the operation of the present embodiment. When the communication clock signal 103 is at "1" level and the write clock signal 104 is at "1" level, the oscillator 14 outputs The output clock 107 does not stop and the interrupt request signal 102 is generated. When the communication state signal 103 becomes "0" level and the write clock signal 104 becomes "1" level, the oscillator 14 is stopped and the interrupt request signal 102 is not generated.

Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram showing the internal configuration of the communication device according to the second embodiment of the present invention. The components other than the communication device of this embodiment are the same as those of the first embodiment described above, and are omitted in FIG. As shown in FIG. 5, the communication apparatus of the present embodiment corresponds to the address / data bus 201 and has a data buffer (for reception) 16
A data buffer (for transmission) 17, a transmission / reception control device 18, a transmission data detection device 19, and an OR circuit 20.
And is configured. The communication device in this embodiment is
As is clear from comparison with FIG. 2, the data buffer (for reception) 16 is newly added. The data buffer (for reception) 16 is a buffer for storing the data received by the transmission / reception control device 18, and the reception data stored in the data buffer (for reception) 16 is the address / data bus 201. Through C
It is read by PU1. However, even if the operation clock 101 is stopped while the received data is stored in the data buffer (for receiving) 16, the normal operation is not adversely affected, so the received data is stored in the data buffer 16. It is not necessary to detect whether it has been done. Other than this, the control operation during transmission and reception and when transmission data remains in the data buffer (for transmission) 17 is exactly the same as in the case of the first embodiment.

[0016]

As described above, the present invention comprises means for confirming the communication operation state including transmission and reception in the communication device and confirming the presence or absence of the residual transmission data in the transmission data buffer. Conventionally, it is possible to invalidate the stop setting of the operation clock by the CPU at the time of operating the communication function, and to easily notify the CPU that the stop setting of the operation clock is invalid by the interrupt request signal. Needed CP
There is an effect that a complicated program and a complicated circuit configuration in U become unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a communication device in the first embodiment.

FIG. 3 is a block diagram showing a clock control device in the first embodiment.

FIG. 4 is a timing chart showing the operation of the first embodiment.

FIG. 5 is a block diagram showing a communication device according to a second embodiment.

FIG. 6 is a block diagram showing a conventional example.

[Explanation of symbols]

 1, 21 CPU 2, 22 Communication device 3, 23 Clock control device 4, 24 Crystal oscillator 5 Transmission data buffer 6, 19 Transmission data detection device 7, 18 Transmission / reception control device 8, 11, 20 OR circuit 9 Inverter 10 , 16 AND circuit 12 Latch circuit 13 Frequency divider 14 Oscillator 16 Data buffer (for receiving) 17 Data buffer (for transmitting)

Claims (2)

[Claims] 1. A communication device for transmitting / receiving serial data, a central processing unit (referred to as a CPU), and a clock control device for generating an operation clock signal supplied to the communication device and the CPU. In a serial data communication control device configured to include a transmission data storage means for storing transmission data scheduled to be transmitted in advance, and detecting the presence or absence of the transmission data stored in the transmission data storage means. , A transmission data detection means for outputting a predetermined detection signal, and an operation including transmission and reception of serial data, and a transmission operation state indicating respective operation states at the time of transmission and reception of the serial data A signal and a reception operation status signal, and a detection signal output from the transmission data detection means. Communication state detection means for detecting that either the transmission operation state signal or the reception operation state signal output from the transmission / reception control means is output, and outputting the communication operation state signal, at least the communication device And a clock signal generating means for generating and outputting the operation clock signal, and a setting operation for stopping the operation clock signal by the CPU during the output of the communication operation state signal, the operation. An operation clock control means for invalidating the stop setting of the clock signal; and the CPU at the time when the stop setting of the operation clock signal is invalidated by the operation clock control means.
An interrupt signal generating means for outputting a predetermined interrupt request signal to the serial data communication device. 2. A transmission data storage means for storing transmission data scheduled to be transmitted in advance, and the presence or absence of the transmission data stored in the transmission data storage means is detected, and a predetermined detection signal is output. Performs operations including transmission and reception of serial data and transmission data detection means, and outputs a transmission operation state signal and a reception operation state signal indicating respective operation states during transmission and reception of the serial data. Transmission / reception control means, reception data storage means for storing reception data received by the transmission / reception control means, detection signal output from the transmission data detection means, and transmission output from the transmission / reception control means A communication state in which either the operation state signal or the reception operation state signal is detected and the communication operation state signal is output Serial data communication control device according to claim 1, further comprising a means out, the at least the communication device.