JPH06230081A - Abnormal position detector for electronic equipment board and probe used in this - Google Patents

Abstract

PURPOSE:To easily specify failure point in a circuit network of a logic signal and an AC signal. CONSTITUTION:A contact 14 of a probe 12 is brought into contact in order with respective test points in an electronic circuit network of a board, and average voltage of signals of the respective contact points is detected by an average detecting circuit 15, and peak voltage of an AC signal is detected by a peak detecting circuit 16. These detecting voltages are converted into digital values by an AD converter 37 in a main body 11, and are compared with reference data stored beforehand in a memory 38 with respective test points, and when these are different from a prescribed value or more, those are judged as abnormal, and are displayed on a display part 39. When respective input points of the circuit network are normal and the output points are abnormal, the part is specified as a failure position. When these are specified in order from a large block to a small block, a failure in a part unit can be also specified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is effectively used to identify a failure point in an electronic circuit network mounted on a board of an electronic device, and detects an abnormality in each node (test point) of the electronic circuit network. The present invention relates to a position detection device and a probe used therefor.

[0002]

2. Description of the Related Art A "signature analysis method" is known as a failure diagnosis technology for electronic circuits. This is because a pseudo random pattern is generated by using a linear feedback shift register as a test pattern generating means, and when the shift operation is repeated while sequentially inputting the test result to the input of the shift register, the final value of each shift stage of the shift register is It is determined by a specific value (signature) corresponding to the input pattern series (test result). Therefore, the value of a non-defective product is stored and the quality of the circuit network is determined by checking the value.

[0003]

In the above-mentioned conventional technique, it is necessary to incorporate a part or all of the test circuit for identifying the failure part in the device itself. In addition, for an electronic circuit network that does not have this built-in, there is no one that can easily detect an abnormal point for specifying a failure point, and a relatively expensive means that requires specialized knowledge is used. There was nothing else.

Furthermore, the above-mentioned "signature analysis method" is intended mainly for logic circuits including microprocessor circuits, and cannot be used for analog circuits. Therefore, there is a problem that it is necessary to use it in combination with other techniques in order to specify a failure point in a general network including an analog circuit. The object of the present invention is to utilize for enabling to identify the faulty part of not only the logic circuit but also the analog circuit, and moreover, it can be constructed at a very low cost, and the abnormal part detecting device for an electronic equipment board and the use thereof To provide a probe.

[0005]

According to the present invention, a probe detects an average voltage of a signal at a test point of an electronic network mounted on a board, and the probe detects the voltage. Identification information for identifying is input by the input means. The reference data is stored in the memory for each identification information of each test point, and the detection voltage from the probe and the reference data obtained by referring to the memory by the input identification information are compared and judged, and the judgment result Is notified. The input unit, the memory, the comparison unit, and the notification unit are held in the main body. According to the invention of claim 2, the probe can detect the peak voltage of the signal at the test point.

According to the invention of claim 3, the probe is electrically contacted with each test point of the electronic circuit network mounted on the board, and the average voltage of the signal of the test point inputted from the probe is detected, Further, identification information for identifying the test point with which the probe is in contact is input, reference data is stored in the memory for each identification information of each test point, and the detected average voltage is detected in the state where the probe is in contact with the test point. Is compared with the reference data obtained by referring to the memory by the input identification information, and the determination result is notified. The average detection means, the input means, the memory, the comparison means, and the notification means are held in the main body.

According to the invention of claim 4, in the invention of claim 3, peak voltage detecting means of the signal of the test point inputted from the probe is provided in the main body, and the comparison judgment of the peak voltage and the reference data is performed. . According to the invention of claim 5, in the invention of claim 2 or 4, the peak detecting means detects the positive peak voltage and the negative peak voltage after passing through the capacitor,
The mark ratio is calculated from the detected peak voltage and the detected average voltage, and the mark ratio is compared with the reference data of the mark ratio of the corresponding test point stored in the memory in advance.

According to the invention of claim 6, in the invention of claim 1 or 2, each input signal from the test point is converted into a pulse having a predetermined width and a predetermined amplitude in the probe, and an average voltage of the converted pulse. Is detected. According to the invention of claim 7, in the invention of claim 3 or 4, each signal input from the probe to the main body is converted into a pulse having a predetermined width and a predetermined amplitude, and the average voltage of the converted pulse is detected. It

According to an eighth aspect of the present invention, in any one of the first to seventh aspects of the present invention, a unique number (ID number) is stored in the memory as identification information of the test point, and the board test is performed as the input means. Means are attached to the probe to optically read the unique number attached at or near the point itself. According to the invention of claim 9, in any one of claims 1 to 7, the position coordinates are stored in a memory as identification information of the test point, and when the probe is positioned on the board, the position coordinates are used as the input means. Is detected by the position digitizer and is supplied to the main body.

According to the invention of claim 10, in any one of claims 1 to 7, the position coordinates on the board of each test point are also stored in the memory, and the probe is moved on the board to perform each test. A point is contacted and its moving contact is automatically performed by sequentially reading the position coordinates of the test point. According to the invention of claim 11, in the invention of any one of claims 1 to 7, a plurality of probes are held in the same arrangement as the arrangement of each position where a test point of the board may exist, and these probes are arranged on the board in a plurality of positions. The signal or voltage from the probe is captured in a predetermined order while being in contact with the test point of.

According to the twelfth aspect of the invention, in any one of the first to seventh aspects of the invention, a mode such as a reference data setting mode or a test data acquisition mode is designated, and the reference data setting mode is designated. The test point identification information and the reference data are input, and the reference data is stored in the memory for each identification information.

[0012]

FIG. 1 shows an embodiment of the present invention. The probe 12 is connected to the main body 11 of the abnormal point detecting device of the present invention. The probe 12 has a needle-shaped contact 14 protruding from the tip of a pen-shaped body 13, and the contact 14 can be electrically contacted with a test point of an electronic circuit network mounted on a board (not shown). In this embodiment, the probe 12 has an average detection circuit 15 and a peak detection circuit 16 housed in the body 13, and the average detection circuit 15 can detect the average voltage of the signal at the test point with which the contact 14 is in contact. In addition, the peak voltage of the signal at the test point can be detected by the peak detection circuit 16. Further, in this embodiment, the ground contact portion 17 is projected from the body 13 in parallel with the contact 14.

As shown in FIG. 2A, the average detecting circuit 15 has a resistor 18 connected to a terminal 18 connected to the contact 14.
9 is connected to one end, and the other end of the resistor 19 is connected to the capacitor 2
It is grounded through 1. The resistor 19 and the capacitor 21 form an average detection circuit 15. In this example, the output side of the average detection circuit 15, that is, the connection point of the resistor 19 and the capacitor 15 is connected to the buffer 22 having a high input impedance. In FIG. 1, the average detection circuit 15 including the buffer 22 is used.

In the peak detection circuit 16, for example, as shown in FIG. 2B, an AC coupling circuit 23 is connected to a terminal 18 connected to the contact 14. That is, one end of the DC blocking capacitor 24 is connected to the terminal 18, and the other end of the capacitor 24 is grounded through the resistor 25 and the diode 2
6 is connected to one end, and the other end of the diode 26 is grounded through the smoothing capacitor 27. Also, if necessary,
The discharge switch 30 of the capacitor 27 shown by the dotted line in FIG. 2B may be used. A buffer (not shown) may be inserted between the terminal 18 and the AC coupling circuit 23 for the purpose of increasing the input impedance. The peak detection circuit 16 is configured by the capacitors 24 and 27, the resistor 25, and the diode 26. In this example, the output side of the peak detection circuit 16, that is, the connection point of the diode 26 and the capacitor 27 is connected to the high input impedance buffer 28, and the configuration including the buffer 28 is the peak detection circuit 16 in FIG.

In FIG. 1, the output side of the average detection circuit 15
And the output side of the peak detection circuit 16 is the lead wire 2 respectively.
It is connected to the main body 11 through 8, 29. The positive side of the DC power supply 31 in the main body 11 is connected to the probe 1 through the lead wire 32.
2 is connected to the power supply terminals of the buffers 22 and 28 of the average detection circuit 15 and the peak detection circuit 16, and the ground side of the power supply 31 is connected to the ground side of the average detection circuit 15 and the peak detection circuit 16 through the lead wire 33 and the ground. It is connected to the contact part 17. The lead wires 28, 29, 32 and 33 are one cord 34.

The main body 11 controls the microprocessor 35.
In the case of being configured to mainly perform the above, the A / D converter 37, the memory 38, the display 39, the buzzer 41, the mode selection unit 42, the switch selection unit 43, the switches 45 and 46 are connected to the microprocessor 35 via the bus 36. Position drive unit 4
7 is connected. The memory 38 stores reference data for each piece of identification information that identifies each test point. Memory 38
For example, as shown in FIG. 2C, a unique number (ID number) is provided as identification information of one test point for each address.
And the position coordinates (x, y) of the test point on the board are
Also, the average voltage value and the peak voltage value under normal conditions are stored. The average voltage value and the peak voltage value are referred to as reference data.

Writing to the memory 38 is performed as follows, for example. The mode selection section 42 is operated to set the reference data setting mode, and the switches 45 and 46 are both set in the input section 48.
Set to the side. By operating the keyboard of the input unit 48, the values known in advance are set to the ID number, position coordinate (x, y),
The average voltage value and the peak voltage value are input in this order, and each input data is stored in the memory 38 by the microprocessor 35.
Write to. Alternatively, a bus is connected to an external database through the input unit 48, and the data used when the electronic circuit network of the board is designed by CAD (design device by electronic computer) is used, and the position coordinates and normal voltage (logical value, etc.) are assigned according to the ID number. Transfer the data and enter. In this case, the microprocessor 35 calculates the average voltage or the peak voltage from the input data and writes it in the memory 38. Figure 2
A ROM in which data as shown in C is previously written may be detachably attached to the main body 11 according to the board to be inspected.

Further, using a board operating normally as a model, an ID number attached near the test point of the board or attached to the test point itself is input by operating the keyboard of the input unit 48. Then, at the test point, probe 1
2 are brought into contact with each other, and the respective outputs of the average detection circuit 15 and the peak detection circuit 16 at that time are fetched and written in the memory 38. At this time, the switch selector 43 is controlled to control the switches 49, 51.
Are alternately turned on, the output voltages of the average detection circuit 15 and the peak detection circuit 16 are alternately captured, and the captured voltage is AD
It is converted into digital data by the converter 37 and written in the memory 38. This writing is performed for each test point. At this time, the position coordinates are not written. As shown in FIG. 3A, a video camera (for example, CCD camera) 52 is attached to the body 13 of the probe 12, and the video camera 52 allows
The ID number attached to the board or the test point is photographed, the video output is input to the image processing unit 53 provided in the main body 11 through the code 34, the photographed ID number is recognized, and the ID number is switched. It may be incorporated into the microprocessor 35 through 45.

It should be noted that the test point needs an area where the contact 14 of the probe is in good electrical contact, for example, as shown in FIG.
As shown in B, a part of the wiring pattern 55 on the board 54 is enlarged into a circular land shape to form a test point 56. Solder plating is preferably performed in order to avoid contact failure due to oxidation of the surface of the test point 56. ID number 5 next to test point 56
7 is written on the board 54. For an existing board, it may be connected to an original test point and, for example, as shown in FIG. 3C, a plate-like test terminal may be attached to the board 54 as a test point 56 in parallel with the test point. ID on the upper surface of this test point 56
The number 57 is attached. As shown in FIG. 3D, the central portion of the test point 56 of the terminal may be recessed toward the board 54 so that the contact 14 can be easily contacted. Video camera 5
When the ID number 57 is read by 2, the ID number 57
May be marked with a bar code.

In the case of automatic inspection, for example, as shown in FIG. 4, the probe 12 is attached to the xy movable mechanism (one type of position digitizer) 58, and the probe 12 freely moves on the board 54 to set an arbitrary test point. Will be able to contact you. Square fixing frame 59 on the periphery of the board 54
Are arranged at appropriate intervals, and both ends of the y-direction moving shaft 61 are movably attached to one of the opposing sides of the fixed frame 59 along the side, and along the y-direction moving shaft 61. An x-direction moving body 62 is movably attached, and the probe 12 is movably held on the x-direction moving body 62 in a direction perpendicular to the board 54. The movement of the y-direction moving shaft 61 and the movement of the x-direction moving body 62 are moved by, for example, a pulse motor (not shown), and the probe 12 is moved to the test point 56.
The probe 12 is moved to the board 54 side and brought into contact with the test point 56 in the state of being positioned above.

An origin mark 63 and a full scale mark 64 are provided on the board 54, and these marks are read by an optical reading means attached to the x-direction moving body 62 to know the reference of position coordinates. In FIG. 1, the position coordinate data is given from the microprocessor 35 to the position drive unit 47, and the position drive unit 47 moves the y-direction moving shaft 61 and the x-direction moving body 62 in accordance with the coordinate data, so that the probe 12 moves. It is moved to a position on the board designated by the microprocessor 35. On the other hand, when the position digitizer is used as the input means of the identification information, its mechanism may be the same as that shown in FIG. 4, and an encoder or the like may be attached instead of the pulse motor. In that case, the movement amount of the y-direction moving shaft 61 and the movement amount of the x-direction moving body 62 are input to the position coordinate conversion unit 65, and the position coordinates of the probe 12 are obtained as identification information.
6 to the microprocessor 35.

Writing of reference data in the memory 38 described above
Is controlled by the xy movable mechanism 58 as a position digitizer.
Lobe 12 is tested at each test point 56 on a normal model board 54.
May be sequentially contacted with. In this case, the ID number is
I can't remember. Mode selection unit 4
2 is set to the test data acquisition mode and the test point 56
The contact 14 of the probe 12 is brought into contact. At test point 56
If a DC signal (including power supply voltage) appears, then
The pressure directly becomes the output of the average detection circuit 15. Test point 5
The average detection circuit when a logic signal appears at 6
As shown in FIG.
Is a high level V_HIn case of high level V_HIs output,
In the case of a pulse signal of duty D, as shown in FIG. 5Ab
Average voltage V_L+ D (V_H-V_L) (V_LIs low level)
Is output, and in the case of a pulse signal with a mark ratio M, FIG.
Average voltage V_L+ M (V_H-V _L) Is output
Low level V_LIn case of low level V_LIs output
It

When an analog signal appears at the test point 56, for example, even if the output analog signal of the operational amplifier is periodic, the time constant of the average detection circuit 15 is set at a time longer than the cycle. By setting, the output of the average detection circuit 15 is obtained as a certain eigenvalue. For example by passing a double integration waveform signal average detection circuit 15 as shown in FIG. 5B, and its low level V _L, the specific average voltage V _M intermediate the high level V _H is outputted.

Therefore, in any case of the DC coupling signal, the operating condition at the test point 56 can be grasped from the output voltage of the average detecting circuit 15. In the case of an AC coupling signal, that is, a capacitor coupling signal or a zero gloss signal, the average voltage is always 0V regardless of the signal amplitude. However, in the peak detection circuit 16 (FIG. 2B), the signal at the test point 56 is blocked by the capacitor 24 and then the diode 2
6, the positive side is rectified and the capacitor 27 is charged in this example. The capacitor 27 is charged with a positive peak value V _P of the AC signal with respect to 0V. Correctly diode 2
6 forward voltage drop value smaller V _R capacitor 2
The voltage is 7. Therefore, the operation status of the AC signal at the test point can be known from the output of the peak detection circuit 16.

When the probe 12 is manually brought into contact with the test point 56, the ID number of each test point is input by the input section 48.
Input by operating the keyboard of. The microprocessor 35 fetches the ID number, and the switch selection unit 43
The output voltage of the average detection circuit 15 and the output voltage of the peak detection circuit 16 are sequentially taken in, respectively converted into digital values, and the taken-in ID from the memory 38 is controlled. The average voltage value and the peak voltage value of the reference data for the number are respectively compared with the output voltages thus taken in, and it is determined whether or not there is a deviation of a predetermined value or more. As the AD converter 37, it is conceivable to use a medium-performance converter having an accuracy of 8 to 10 bits and a response time of 1 to 10 μS.

The operating level of the logic element has a wide allowable range, for example, the low level of TTL is 0 to 0.8V and the high level thereof is 2.7 to 5.0V. Therefore, the variation of the normal value is expected every time the element changes, and the average voltage also varies accordingly. For this reason, a certain allowance is given in the failure determination, and the one whose measured value falls within the range of (reference data) ± (allowance) is regarded as normal, and the one outside of this is regarded as abnormal. In this case, when the environmental temperature changes, it is necessary to take into consideration the temperature fluctuation of the measured value, for example, ± 1%, ± 3%, ± 5%, ± 10.
It is preferable that the tolerance can be selected from%, ± 20% by operating the keyboard of the input unit 48.

Depending on the test point 56, it is sufficient to check only the output voltage of the average detection circuit 15 or only the output voltage of the peak detection circuit 16. The notification means notifies the result of comparison and determination between the measured value and the reference data. As the notification method, there are an audible notification, a visual notification, and a combination thereof.
As for the audible notification, the buzzer 41 simply sounds “beep” when normal, and the buzzer 41 sounds “blip” when abnormal. As the visual notification, for example, as the display unit 39,
As shown in FIG. 5C, light emitting diodes (LEDs) 66 are arranged in an array, and IDs are provided near the respective light emitting diodes 66.
ID number 5 of test point 56 with number 57 checked
The light emitting diode 66 at 7 is simply lit continuously (indicated by a black circle in the figure) when normal, blinks (indicated by a shaded line in the figure) when abnormal, and unlit (indicated by a white circle in the figure).

Further, the display by the display unit 39 is shown in FIG. 5C.
It is also possible to provide a numerical display section of about 5 digits of the segment light emitting diode together with the display shown in (1), and to estimate the failure point after the comparison judgment and display the result as a part number or the like on the numerical display section. Further, the display shown in FIG. 5C and the numeral display section may be realized by liquid crystal display or CRT display. Audible notification may be used together with any visual notification.
When the probe 12 is moved by the xy movable mechanism 58 and brought into contact with the test point or when another position digitizer is used, the liquid crystal display or the CRT display is usually adopted, and in the case of manual operation, any of the notification means is used. Method is adopted.

In the above description, the ID number 57 of the test point 56 with which the probe 12 is brought into contact is manually input by the keyboard, but it may be automatically input by the position digitizer. For example, FIG. 6A shows a type different from the position digitizer described above. The position digitizer 66 is provided with a rectangular fixed frame 67 on the board 54 that matches the peripheral portion of the position fixed digitizer 66. The fixed digitizer 66 has light emitting elements 68 on the inner surfaces of two adjacent sides of the fixed frame 67 at unit distance intervals along the respective sides. Are attached, and light receiving elements 71 that face the respective light emitting elements 68 and receive the emitted light 69 are attached to the opposite sides. Fixed frame 6
When the probe 12 is brought into contact with the test point 56 on the board 54 in 7, the two light receiving elements (71 _x2 , 71 _{y2 in the} illustrated example) which are blocked by the probe 12 and the light does not reach,
The contact position (2, 2) of the probe 12 is detected, and this position coordinate is taken into the microprocessor 35 from the position digitizer 66 connected to the position coordinate conversion unit 65. In this case, the reference data of the test point of the position coordinate which coincides with the fetched position coordinate is read from the memory 38.

As a method of grounding the probe 12 and the main body 11, as shown in FIG. 6B, for example, as shown in FIG.
2 is provided in the same manner as the test point 56, and the contact 14 of the probe 12 and the grounding contact portion 17 are respectively provided at the test point 5
6 and the ground point 72 are simultaneously contacted. If the signal frequency of the electronic network is low, for example, x shown in FIG.
When the y movable mechanism 58 is used, the fixed frame 59, the y direction moving shaft 61, and the x direction moving body 62 are made of a conductive material, and when the probe 12 is held by the x direction moving body 62, the peripheral surface of the probe 12 is held. The contact foil for ground that has been led out to contact the x-direction moving body 62 and is connected to the ground plane on the board 54 through the fixed frame 59. Alternatively, as shown in FIG. 4B, a ground wire 73 is led out from the probe 12 and connected to the ground plane of the board 54. The ground wire 73 is slackened so as not to hinder the movement of the probe 12.

Alternatively, the probe 12 or the x-direction moving body 62 may be manually moved to bring the probe 12 into contact with the test point 56 without driving the xy movable mechanism 58 with a motor. At this time, each moving position of the y-direction moving shaft 61 and the x-direction moving body 62 is converted into a signal by an encoder or a potentiometer and sent to the position coordinate conversion unit 65 of the main body 11.

Next, a case where the normality / abnormality of each test point is automatically determined will be described. As shown in FIG. 6C, first set N to 1.
And (S _1), reads the position coordinates (x, y) of the number N of the test points 56 (= 1) from the memory 38 (S _2). The position coordinates (x, y) are set in the position drive unit 47 in FIG. 1, the probe 12 is moved to the position coordinates (x, y) in FIG. 4, and the probe is moved to the test point 56 with the number N (= 1). 12 is brought into contact (S ₃ ). Converts average detection circuit 15, the output V _M of the peak detection circuit 16, the V _R to capture a digital value (S _4), these V _M, stores the determined result compared to V _R and the reference data (S ₅₎ . N is incremented by 1 to be N (S ₆ ), and N is P + 1 (P is the number of all test points 56)
Is checked, and if they do not match, step S ₂
Returning to (S _7), and ends with the notification of the determination result for all test points stored so far, if match (S _8). The input means in this case is the read position drive unit 4 from the memory 38.
It is also used by setting the position coordinates to 7.

Alternatively, as shown in FIG. 7A by assigning the same reference numerals to the portions corresponding to those in FIG. 1, as many probes 12 as the number of test points 56 are prepared, and these probes 12 are used for each test point 56.
7B, the holding plate 74 is inserted and held at a position corresponding to the coordinates of. The holding plate 74 is attached to the Z position drive unit 75.
Can be controlled to move to the board 54 side, and each probe 12 can be simultaneously brought into contact with each test point 56. The lead wires 28 and 29 to which the detection voltages V _M and V _R from the respective probes 12 are respectively supplied are connected to the AD converter 37 through the switches S _{1 to} S _2P .

With the ID numbers and reference data of all the test points being input to the memory 38, first, as shown in FIG. 7C, the Z position drive unit 75 is controlled to set the P test probes 12 to the corresponding test points. 56 are contacted with each other (S ₁ ). The switch selector 43 is controlled to turn on only one switch in order from the switch S _1, and the detected voltage at that time is converted into a digital value by the AD converter 37 (S ₂ ). The detected 2P voltages are compared with corresponding reference data, and the determination result is notified by the notification unit 40 (the display unit 39 and the buzzer 4 in FIG. 1).
Notify in 1) (S ₃ ). The input means in this case also serves as the sequential selection of the switch selection unit 43.

In the above description, the probe 12 has the peak detection circuit 1
In FIG. 6, only the voltage of one peak (the positive peak in the embodiment) is detected, but the other peak voltage may be detected. For example, as shown in FIG. 8A by attaching the same symbols to the portions corresponding to those in FIG. 2, in this example, the AC coupling circuit 23
The negative peak detection circuit 76 is connected to the connection point between the positive peak detection circuit 16 and the positive peak detection circuit 16. That is, the cathode of the diode 77 is connected to the anode side of the diode 26, and the anode of the diode 77 is grounded through the capacitor 78 and connected to the high input impedance buffer 79.

Average voltage V obtained from the buffer 22
_MAnd the positive peak V obtained from the buffer 28_PPAnd
Negative peak V obtained from Luffa 79_PnFrom the main body 1
In the microprocessor 35 of 1, the high level V_H=
V_M+ V_PPAnd low level V_L= V _M+ V_Pn(V_Pn<0)
And the mark ratio M (including the duty ratio D) (V_M−
V_Pn) / (V_PP-V_Pn) And
And compare with the corresponding reference data obtained in advance
To do. As described above, for example, in TTL, the low level V_L,
High level V_HThere is a large tolerance for
There are variations due to lots and among lots.
Therefore, the average voltage V_MThere is a risk of making a mistake with the judgment
It However, the mark ratio M (or duty ratio D) is also calculated.
If you compare and judge_H, V_LAre equal and mark rate
Waveforms in which M is equal are, for example, (a), (b), and
There are innumerable as shown in (c), but normal and (a) wave
The probability that the shape will become the waveform of (b) or (c) due to failure is
Very small. Therefore this V_H, V_L, M are compared and judged
To more accurately determine the test point abnormality
You can

However, in order to detect an abnormality when the frequencies are different but the mark ratio M is the same, for example, as shown in FIG. 9A, in addition to the average detection circuit 15 and the peak detection circuit 16 in the probe 12, the frequency detection section 81 is provided. Is provided. For example, each signal from the terminal 18 is converted into a pulse having a constant pulse width by the monostable multivibrator 82, and the pulse having the constant pulse width is sliced by the slicer 83 into a pulse having a constant amplitude of low level V ₁ and high level V _2. The sliced pulse is supplied to an average value circuit 84 including a resistor and a capacitor and averaged, and the average voltage V _F is supplied to the main body 11.

This average voltage V _F is proportional to the test point 56, that is, the frequency of the signal at the terminal 18. Therefore,
By preparing reference data for this average voltage V _F in advance and comparing the measured value V _F with the reference data, it is possible to reliably detect an abnormality at the test point. Although the electric circuit is provided in the probe 12 in the above description, the electric circuit may be provided in the main body 11. For example, as shown in FIG. 9B by attaching the same reference numerals to the portions corresponding to those in FIG. 1, the probe 12 has only a contact 14 and a grounding contact portion 17 (which may be the foil-like one described above) on its body. The average detection circuit 15 and the peak detection circuit 16 are provided in the main body 1
1, the probe contact 14 and the ground contact portion 17 are connected to the average detection circuit 15 and the peak detection circuit 16 through lead wires 85 and 86, respectively.
The other configuration is the same as that of FIG. 1, and the operation is also the same. Also in the configuration of FIG. 9B, the peak detection circuit 16 may detect not only one peak but also both the positive peak and the negative peak. Also in FIG.
The frequency detector 81 shown in A may be provided. Probe 1
Input of the identification information to the test point 56 contacted by 2 may be performed by a keyboard, by optical reading, by a position digitizer, or the like, as described above. Further, FIG.
It is also possible to automatically detect each test point as described in C. Similarly, as shown in FIG. 7A, it is possible to provide a plurality of probes to automatically inspect each test point. You can also Further, means for optically reading the ID number can be attached to the probe 12. When each detection circuit is provided on the main body 11 side, the average value circuit 84 can also be used as the average detection circuit 15 by switching a switch. Further, by switching the switch, the average detection circuit 1
The capacitor 21 of 5 and the capacitor 27 of the peak detection circuit 16 can be used in common.

The peak detection circuit 16 may be omitted in the above description when the electronic circuit network on the board is only a logic signal, that is, a DC coupling signal (including a power supply signal). That is, only the average detection circuit 15 or the probe 12 and the frequency detection section 81 are added to the probe 12, or these are added to the main body 1
The one provided in No. 1 is used. Further, in the above description, the main body 11 determines whether each test point is normal or abnormal, but an inspector may make this determination. That is, the average detection circuit 15 or the peak detection circuit 16 and the probe 12 provided with the frequency detection unit 81, or the average detection circuit 1
5 and the probe 12 provided with the frequency detection unit 81 are brought into contact with each test point, and the output of the probe 12 at that time, that is, the output voltage of the average detection circuit 15, the output voltage of the peak detection circuit 16, and the output of the frequency detection unit 81. The voltage may be measured by, for example, a digital voltmeter, and the inspector may use the brain to make a comparison between the measured value and the reference data for the test point in the document prepared in advance.

As a document in this case, for example, as shown in FIG. 10A, the paper 91 is similar in shape to the board 54, and a connector display 92 corresponding to the connector of the board 54 is displayed at one end of the paper 91. Blocks 93A, 93 whose shape and layout are similar to each of the blocks A, B, C, D obtained by structurally and electrically dividing the net
B, 93C and 93D are drawn on the paper 91, and the test points 56 of the input terminals and the output terminals of the paper 9 have the same arrangement as the symbol 9
4, and the ID number 57 of each test point 56 is similarly written on the paper 91. Further, in each of the test point displays 94, DC is used when measuring the output voltage of the average detection circuit 15, and AC is used when measuring the output voltage of the peak detection circuit 16, respectively. A reference data display 95 at the time of normal operation is attached. The connector display 92 also displays each corresponding contact, and the reference data display at the time of normal operation is attached to the contact display. By doing so, the probe 12 is brought into contact with the actual test point of the board or the contact portion of the connector, and the reference data for the measured voltage at that time can be easily known from the document.

In such a measurement, since the voltage measured by the digital voltmeter is only one input, the output of the average detection circuit 15 and the output of the peak detection circuit 16 are switched by the switch and supplied to the digital voltmeter. And then
The switch will be provided in the probe 12. Figure 1
As shown in 0B, the output side of the resistor 19 of the average detection circuit 15 and the output side of the diode 26 of the peak detection circuit 16 are switched by the switch 96 and connected to the capacitor 21, so that the capacitor 21 is shared. , And switch 9
It is also possible to switch 6 to detect the average voltage or the peak voltage.

In order to identify the faulty part, the following procedure is performed. It is assumed that all the necessary reference data are input to the abnormal point detecting device according to the present invention, and that the electronic device under test has only one faulty point. The latter bidirectional CPU data bus is assumed to be self-checked by the microprocessor itself incorporated in the electronic device and is normal, and the power supply is normal. (1) Identification of defective board If there are multiple boards, first identify which board has a failure. The method sequentially checks the signals coming in and out of each board, for example, at the connector part, and finds a board in which the input signal is normal but the output signal is abnormal. For this purpose, it is convenient if information such as the pin number of the connector and the type of input / output is input at the stage of inputting the reference data. (2) Identification of the faulty block When the faulty board is found, the probe 12 can be brought into contact with the test point 56 of the board by using the getter (extender) or the extraction cord, and then the board is roughly divided into blocks. It corresponds to the test point in the separated state (the instruction of this test point may be a document or may be shown on the display of the main body). Here again, a block having a normal input signal and an abnormal output signal (large failure block) is searched for. When the large failure block is found, the process proceeds to detection of the in-failure block and the small failure block. (3) Identification of faulty component If the block division of (2) is performed on the basis of 6 pieces, it means that the faulty portion can be identified with the detail of 1/6 ³ = 1/216 in ^three searches. This means that if there are 216 parts, it can be judged at the level of one part. (4) Confirmation of defective parts Even if the defective parts can be almost specified, it cannot be said that there is no error judgment. In particular, it is necessary to be cautious because it means replacing parts after finding a defective part. Further, when the other party is an LSI having a large number of pins, it is necessary to specify with certainty. Therefore, finally, for the relevant part, a signal check is performed at all pins to confirm whether the input signal is normal and the output signal is truly abnormal.

[0043]

The present invention has the following effects. A single probe is efficient because it can detect the DC voltage, the average voltage of the logic signal, and the peak voltage of the AC signal. If various data related to test points (DC voltage value, AC voltage value and ID number or position coordinate) and other data related to board connector and each component (pin number and I / O terminal distinction) are prepared, It is possible to search for a failure point by tailoring a black box block without any knowledge or knowledge, and it is possible to generalize or generalize the task of specifying a failure point that conventionally required advanced electrical technology. , Its effect is immeasurable.

Although it is basically determined that a particular network has a fault when the input signal is normal and the output signal is abnormal, the determination is quite intuitive and It is logical (There are exceptions, but if there is a cause of failure in the input of the next network, a judgment error will occur, but in this case, if the first component replacement did not recover, the next network All you have to do is doubt the parts). Therefore, it is possible to program and automate the procedure for searching for a faulty part. This leads to labor saving in the work of identifying the failure location.

Normally, a voltmeter, an ohmmeter, an oscilloscope, and sometimes a logic analyzer are indispensable for identifying a failure point in the field. However, if the failure location identifying apparatus using the present invention is used, those instruments are almost unnecessary, and it is possible to realize a large reduction in equipment cost and labor saving of instrument transportation. In a given product, there are two phases in which it is necessary to identify the location of the failure, one of which is when the board is first operated after component mounting is completed, and the other is maintenance after shipment. At present, although the two phases have a common purpose in that the fault location is identified, the coping method is not unified. In other words, board testers and special jigs are often used during production, but they are not suitable for field (field) service. They have to be polished and they can be said to generate considerable double investment as a whole.

By using the concept of specifying a failure point according to the present invention, it is possible to unify the failure point specifying device at the time of production and maintenance. This is because if all the data on test points are determined at the time of production (or at the time of design), it can be used as it is for maintenance. Resource saving is being called for as a trend in the world,
When it comes to electronic equipment, maintenance by users is one issue. However, contrary to that problem, the inside of electronic devices is becoming more and more complicated, and the problem is distant. For this situation, the fault localization concept using the present invention provides a very effective solution. There are two reasons.
One is that electronic device manufacturers will proactively release data on test points and data on fault location. This is because they do not leak any know-how in circuit design (because they are only black boxes and voltage values). The second is that no special skill is required to follow the failure point.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention of claim 2;

2A is a connection diagram showing an example of an average detection circuit 15, B is a connection diagram showing an example of a peak detection circuit 16, and C is a memory 38. FIG.
It is a figure which shows the example of a memory state inside.

FIG. 3A is an external view showing a probe having an ID number reading means, B is a plan view showing an example of test points on a board, and C is a plan view.
And D respectively show other examples, (a) is a plan view,
(B) is a sectional view.

FIG. 4 shows an example of an xy movable mechanism 58, where A is a plan view and B is a plan view.
Is a front view.

5A is a diagram showing a relationship between various states of a logic signal and an output of the average detection circuit 15, FIG. 5B is a diagram showing a relationship between a double integrated waveform signal and an output of the average detection circuit 15, and FIG. 6 is a diagram showing a display example of a display unit 39. FIG.

6A is a plan view showing another example of the position digitizer, FIG.
Is a side view showing the contact between the probe test point and the ground point,
C is a flow chart showing a processing example in the case where one probe is automatically brought into contact with each test point.

7A is a block diagram showing an embodiment of the present invention in which each test point signal is captured by a plurality of probes, B is a front view showing an example of the relationship between the probes and a board, and C is this processing example. It is a flow chart shown.

8A is a connection diagram showing another example of the internal configuration of the probe 12, and FIG. 8B is a waveform diagram showing an example in which the waveform is different at the same mark ratio.

FIG. 9 is a connection diagram showing still another example of the internal configuration of the probe 12, and B is a block diagram showing an embodiment of the invention of claim 3.

10A is a diagram showing an example of a document in which reference data is described, and B is a connection diagram showing another example of a circuit in the probe 12. FIG.

Claims (16)

[Claims] 1. A probe having an average detection means for detecting an average voltage of a signal at a test point of an electronic network mounted on a board, and inputting identification information for identifying a test point at which the probe detects a signal. Input means, a memory that stores reference data for each piece of identification information of each test point, and a detection voltage from the probe, which is compared and determined with reference data obtained by referring to the memory with the input identification information. A comparing means, an informing means for informing the result of the comparison determination, and the input means, the memory, connected to the probe,
An abnormality detecting device for an electronic device board, comprising: a main body holding the comparing means and the notifying means. 2. The abnormality detecting device for an electronic device board according to claim 1, wherein the probe is provided with peak detecting means for detecting a peak voltage of the signal at the test point. 3. A probe electrically contacting each test point of an electronic circuit network mounted on the board, a means for inputting identification information for identifying the test point with which the probe is in contact, and input from the probe. Average detection means for detecting the average voltage of the signal at the test point, a memory for storing reference data for each identification information of each test point, and a state in which the probe is in contact with the test point, from the average detection means Comparing means for judging the detected voltage of the reference data with reference data obtained by referring to the memory by the inputted identification information, notifying means for notifying the result of the comparison judgment, connected to the probe, A means for detecting an abnormality in an electronic device board, comprising: a means, the average detection means, the memory, the comparison means, and a main body holding the notification means. 4. The main body is provided with peak detecting means for detecting a peak voltage of a signal at the test point input from the probe, and the comparing means detects the peak with the probe in contact with the test point. 4. The apparatus for detecting an abnormal portion of an electronic device board according to claim 3, wherein the detection voltage from the means is also compared and judged with the reference data. 5. The peak detecting means is means for detecting a positive direction peak voltage and a negative direction peak voltage after AC coupling, and the positive direction peak voltage and the negative direction peak voltage detected by the main body, 3. A means for calculating a mark ratio from the average voltage, and a means for comparing and judging the calculated mark ratio with reference data of the mark ratio of a corresponding test point stored in advance in the memory. 4. An electronic device board abnormal point detecting device according to 4. 6. The probe includes means for converting each signal from the test point into a pulse having a predetermined width and a predetermined amplitude, and means for detecting an average voltage of the converted pulse. Item 1. An electronic device board abnormal point detection device according to item 1 or 2. 7. The main body includes means for converting each signal from the test point input from the probe into a pulse having a predetermined width and a predetermined amplitude, and means for detecting an average voltage of the converted pulse. 5. An abnormal position detecting device for an electronic device board according to claim 3 or 4. 8. A unique number is stored in the memory as identification information of each test point, and the input means is attached to the probe and attached to or near the test point itself of the board. 8. An abnormality detecting device for an electronic device board according to claim 1, which is means for optically reading the unique number. 9. The memory stores the position coordinates as identification information of each test point, and the input means is a position digitizer that detects the position coordinates when the probe is positioned on the board. The abnormal part detecting device for an electronic device board according to any one of claims 1 to 7, wherein: 10. The position coordinates on the board of each test point are also stored in the memory, movable holding means for moving the probe on the board to contact the test point, and each test point. 8. The electronic device according to claim 1, further comprising means for sequentially reading the position coordinates of the probe from the memory, setting the coordinates in the movable holding means, and sequentially bringing the probe into contact with the test point. Board abnormality detection device. 11. A plurality of the probes are provided, and the plurality of probes are held in the same arrangement as the positions of the test points on the board, and the probes are brought into contact with the plurality of test points on the board. 8. An abnormal part detection of the electronic device board according to claim 1, further comprising means for taking in a signal or voltage from the probe into the main body in a predetermined order in a state where the electronic device board is abnormal. apparatus. 12. A mode designation means for designating a mode such as a reference data setting mode and a test data acquisition mode, and identification information of a test point and its reference data in a state where the reference data setting mode is designated by the mode designating means. 8. An abnormality detecting device for an electronic device board according to any one of claims 1 to 7, further comprising: a means for inputting the input reference data and a means for storing the input reference data for each identification information in the memory. . 13. A body that can be held and moved, a contact that projects from the body and can make electrical contact with a test point, and an average voltage of an input signal received from the contact that is housed in the body. A probe for detecting an abnormal part of an electronic device board, comprising: an average detecting means for detecting. 14. The probe for detecting an abnormal portion of an electronic device board according to claim 13, wherein peak detection means for detecting a peak voltage of an input signal from said contact is housed in said body. 15. The probe for detecting an abnormal portion of an electronic device board according to claim 14, wherein said peak detecting means detects a positive side peak voltage and a negative side peak voltage after AC coupling. 16. A means, which is housed in the body, includes means for converting an input signal from the contact into a pulse having a predetermined width and a predetermined amplitude, and means for detecting an average voltage of the converted pulse. The probe for detecting an abnormal portion of an electronic device board according to claim 13.