JPH06195977A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the area of a semiconductor memory chip. CONSTITUTION:A write driver in an I/O circuit 23 is constituted of the series circuit of an FET 27 and an FET 30 and the series circuit of an FET 33 and an FET 35. The B and the inverse of B of a bit wire pair are set to voltage responding to input data with the write driver in the timming of a write-in. Besides, a precharge voltage is impressed to the bit wire pair B and the inverse of B by the write driver in the timming of a precharge.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a function of precharging bit lines when reading data.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory of this type, for example, there is a static random access memory (SRAM) shown in FIG. In such an SRAM, memory cells 1 for storing information are arranged in a matrix in the row and column directions. Each memory cell 1
Are connected in the row direction by word lines, and are connected in the column direction by bit line pairs B and B. This bit line pair is generally called a column. A P-channel MOSFET 2 is connected in series to each column, and when a low level signal is input to the precharge (Pr) terminal during reading, each FET 2 is turned on. Each FE
When T2 is turned on, the voltage of each bit line pair B and bar B is set to the power supply voltage level and precharge is performed.

A word line and a bit line are selected according to an input address, and the memory cell 1 connected to the selected word line and bit line includes a sense amplifier 3 and an I / O.
Connected to the circuit 4. At the time of writing, the P-channel MOSFETs 5 and 6 in the I / O circuit 4 are driven by the NAND circuits 9 and 10 according to the input data D _in when the write enable (Wr.En) signal is active. The N-channel MOSFETs 7 and 8 are controlled by the NOR circuits 11 and 12 and the NOT circuit 13 into a switching state opposite to that of the P-channel MOSFETs 5 and 6. Therefore, the bit line pair B and the bar B are FETs 5 to 8 respectively.
Is set to a voltage according to the input data D _in , and information is stored in the memory cell 1. On the other hand, when reading
The potential of the precharged bit line pair changes according to the information stored in the memory cell 1, and this change is amplified by the sense amplifier 3. Amplified read data D
_out is output via the buffer 14 in the I / O circuit 4.

[0004]

However, in the above conventional semiconductor memory, since it is necessary to precharge the bit lines before reading, the bit line pair B,
In particular, the bar B is provided with the P-channel MOSFET 2.
Therefore, in the conventional semiconductor memory, a region for forming the precharge transistor element is required in the semiconductor chip, and the chip area has not been reduced.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and includes a plurality of memory cells for storing information, and a word line connecting these memory cells in the row direction. In a semiconductor device provided with a bit line connecting each memory cell in the column direction and a write circuit for writing data to the memory cell via the bit line, the write circuit is provided with write input data and a precharge signal. And a signal selection circuit that outputs write input data at the write timing and outputs a precharge signal at the precharge timing, and a bit line drive that sets the bit line to a predetermined voltage according to the output of the signal selection circuit. And a circuit.

Further, a column decoder for decoding an input column address, a column selection circuit for selecting a bit line according to the decode value of this column decoder, and a decode value given from the column decoder to the column selection circuit as a selection signal input. A decode value selection circuit for switching to a value for selecting a predetermined number of bit lines in accordance therewith.

[0007]

The bit line drive circuit is used both for writing data to the bit line and for precharging the bit line.
The conventional transistor for exclusive use of precharge becomes unnecessary.

When the column selection circuit selects a predetermined number of bit lines under the control of the decode value selection circuit, the bit line drive circuit precharges the predetermined number of bit lines at once.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a schematic structure of an SRAM according to an embodiment of the present invention.

The memory cells 21 are composed of CMOSFETs and are arranged in a matrix in the row and column directions. And each line is connected by word line,
Each column is connected by a bit line pair B and a bar B. Each word line is connected to a row decoder via a word driver, and the row decoder sets the voltage level of any one word line to a high level according to an input address. The memory cell 21 connected to the word line driven to the high level is connected to the bit line pair B and bar B. In this embodiment, 1-bit information is associated with 1 column. Therefore, 1 word is 8
When the bit configuration is used, an 8-unit circuit configuration in which the illustrated circuit configuration is 1 unit is formed as one word.

The I / O circuit 23 is connected to the pair of bit lines B and B, and has a precharge enable (Pr.En) signal that determines the precharge timing and a write enable (Wr. En) signal and write input data D _in are input. Further, the I / O circuit 23 outputs read data D _out .

The input data D _in is input to one terminal of the AND circuit 24. The write enable signal is inverted by the NOT circuit 25 and input to the other terminal of the AND circuit 24. The precharge enable signal is the NOR circuit 2
6 is input to one terminal, and the output of the AND circuit 24 is input to the other terminal. The output of the NOR circuit 26 is a P-channel MO whose source is set to the power supply voltage V _DD.
It is given to the SFET 27. The input data D _in is N
The write enable signal, which is also input to one terminal of the OR circuit 28 and is returned to the original by the NOT circuit 29, is applied to the other input terminal of the NOR circuit 28. The output of the NOR circuit 28 is given to the N-channel MOSFET 30 whose source is grounded. These FET27
And FET30 are connected in series, and each FET2
The connection point of 7 and 30 is connected to the bit line B.

The output of the NOR circuit 28 is also input to one terminal of the AND circuit 31, and the write enable signal inverted by the NOT circuit 25 is input to the other terminal of the AND circuit 31. The output of the AND circuit 31 is input to one terminal of the NOR circuit 32, and the precharge enable signal is input to the other terminal. The output of the NOR circuit 32 is given to the P-channel MOSFET 33 whose source is set to the power supply voltage V _DD . Also,
The output of the NOR circuit 26 is input to one terminal of the NOR circuit 34, and the write enable signal returned to the original value when inverted by the NOT circuit 29 is input to the other terminal.
The output of the NOR circuit 34 is given to the N-channel MOSFET 35 whose source is grounded. These FET33
And FET35 are connected in series, and each FET3
The connection points of 3, 35 are connected to the bit line bar B.

In such a structure, a specific word line and bit line pair B and bar B are selected according to an input address. Further, one memory cell 21 is specified by the selected word line and bit line pair B and bar B, and this memory cell 21 is connected to the sense amplifier 22 and I / I.
It is connected to the O circuit 23. Writing to and reading from the specified memory cell 21 are performed by the I / 0 circuit 23.
Is used as an interface.

The write enable signal input to the I / O circuit 23 is shown in FIG. 2B and becomes low level in response to the fall of the clock signal shown in FIG. 2A, and the rise of this clock signal. According to the high level. Further, the precharge enable signal that determines the precharge timing is shown in (d) of the figure. As with the write enable signal, the precharge enable signal goes low at the falling edge of the clock signal and goes high at the rising edge of the clock signal. Become a level. The high level of the write enable signal corresponds to the inactive negated state, and the low level corresponds to the active asserted state. On the contrary, in the precharge enable signal, the high level corresponds to the asserted state, and the low level corresponds to the negated state.

The write operation of the SRAM in this embodiment is performed as follows.

The input data D _in is input to the AND circuit 2 when the write enable signal is at the low level, that is, at the write timing.
4 to the NOR circuit 26. Since the precharge enable signal is inactive when the write enable signal is active, the NOR circuit 26 receives the input data D _in from the AND circuit 24 when the write enable signal is active.
Is output. Also, when the precharge signal is active,
The NOR circuit 26 outputs a precharge signal. Therefore, the P-channel MOSFET 27 is ON / OFF controlled according to the input data D _in when the write enable signal is active. Further, the N-channel MOSFET 30 is NO
The R circuit 28 controls the switching state opposite to that of the P-channel MOSFET 27.

For example, when the input data D _in is at high level, the AND circuit 24 outputs a high level signal at the write timing, and the NOR circuit 26 outputs a low level signal which is the inverted high level signal to the FET 27. To do.
The P-channel MOSFET 27 receives this low level signal and is turned on. Further, the NOR circuit 28 receives the high level input data D _in and outputs a low level signal to the FET 30 at the write timing. N-channel MOSF
The ET 30 receives this low level signal and is turned off.
Therefore, the power supply voltage V is applied to the bit line B via the FET 27.
_DD is supplied.

Further, the AND circuit 31 is a NOR circuit 28.
From the data, that is, the inverted signal of the input data D _in is output at the write timing. The NOR circuit 32 receives this signal output and directly outputs the inverted signal of the input data D _in to the FET.
Output to 33. Therefore, the P-channel MOSFET 33
Is controlled to be turned on / off according to the input data D _in when the write enable signal is active. In addition, N-channel MOS
The FET 35 is controlled to the switching state opposite to that of the P-channel MOSFET 33 by the NOR circuit 34 receiving the inverted signal of the input data D _in output from the NOR circuit 26.

For example, when the input data D _in is at a high level, the AND circuit 31 outputs a low level signal at the write timing, and the NOR circuit 32 outputs a high level signal obtained by inverting the low level signal to the FET 33. To do.
The P-channel MOSFET 33 receives this high level signal and is turned off. Further, the NOR circuit 34 receives the low level signal obtained by inverting the high level input data D _in from the NOR circuit 26, and outputs the high level signal to the FET 35 at the write timing. N-channel MOSFET 35
Receives this high level signal and is turned on. Therefore, the ground voltage is supplied to the bit line bar B through the FET 35.

Therefore, the bit line pair B and the bar B are shown in FIG.
As shown in (c), when the write enable signal is asserted, the voltage corresponding to the input data D _in is set after a certain time delay from the fall of the write enable signal. As a result, information according to the set potential of the bit line pair B and the bar B is written in the specific memory cell 11 selected by the word line and the bit line pair.

On the other hand, the SRAM precharge operation in this embodiment is performed as follows.

First, prior to the read operation, precharge for resetting the bit line pair B and bar B to a predetermined voltage is performed on each bit line pair. This precharge is performed when the precharge enable signal shown in FIG. 2D is at high level. Therefore, at the precharge timing, a high level signal is applied to one input of each of the NOR circuit 26 and the NOR circuit 32 in the I / O circuit 23 shown in FIG. Therefore, at the precharge timing, a low level signal is output from each of the NOR circuits 26 and 32 regardless of the signal input to the other terminal, and this low level signal is output to each P channel M.
It is given to the OSFETs 27 and 33. Therefore, each FET
27 and 33 are turned on.

When the precharge signal is at high level, the write enable signal is also at high level as shown in FIG. Therefore, the output of the NOR circuit 28 which inputs this write enable signal to one terminal becomes low level regardless of the signal input to the other terminal at the precharge timing. Therefore, the N-channel MOSFET 30 which inputs this low level signal is turned off at the precharge timing. Also, NO
Since the write enable signal is also applied to one terminal of the R circuit 34, the NOR circuit 34 outputs a low level signal regardless of the signal input to the other terminal at the precharge timing. Therefore, the N-channel MOSFET 35 that inputs this low level signal is also turned off at the precharge timing.

As a result, at the precharge timing, the power supply voltage V _DD is supplied to the bit line pair B and the bar B through the FETs 27 and 33, and precharge is performed by the I / O circuit 23. After precharging the bit line pair, a read operation is performed, and the specific memory cell 2 selected by the word line and the bit line pair B and B is selected.
1 changes the bit line pair B and bar B set to the precharge potential to a potential according to the stored information. This potential change is amplified by the sense amplifier 22 and output via the buffer 36 in the I / O circuit 23.

As described above, in this embodiment, the series circuit of the FET 27 and the FET 30 and the series circuit of the FET 33 and the FET 35, which constitute the write driver, both write data to each bit line pair and precharge the bit line pair. Is done. That is, the P channel MOSFETs 27 and 33 in the I / O circuit 23 are also used for precharging instead of the conventional P channel MOSFETs dedicated to precharging that are connected in series to the bit line pair, and the conventional P channel MOSFETs dedicated to precharging
Becomes unnecessary. A considerable number of the conventional P-channel MOSFETs are provided for each bit line and occupy a large area on the semiconductor memory chip. On the other hand, the P-channel MOSFET used for precharging in this embodiment
Is also used as the P-channel MOSFETs 27 and 33 used as the write driver as described above, the P-channel MOSFET conventionally provided only for precharge.
The element formation region of is deleted from the semiconductor memory chip.
As a result, the memory chip area is reduced.

FIG. 3 shows an SRAM according to another embodiment of the present invention.
It is a figure which shows schematic structure of. In the above embodiment, the case where one bit information is associated with one column to store information has been described, but in this embodiment, the case where one bit information is associated with four columns and information is stored will be described. .

The memory cells 41 are arranged in a matrix in the row direction and the column direction, and each row is connected by a word line, and each column is connected by a bit line pair B and a bar B. Each word line is connected to the row decoder 43 via the word driver 42, and the row decoder 4
3 sets the voltage level of any one of the word lines to the high level according to the input address. The memory cell 41 connected to the word line driven to the high level is connected to the bit line pair B and bar B. In addition, each bit line pair B,
The bar B is connected to a column selector 44 composed of an N-channel MOSFET, and this column selector 44 is connected to a column decoder 46 via a decode value selection circuit 45.

The column decoder 46 outputs a decode value for selecting any one column from the input address.
This decode value is O that constitutes the decode value selection circuit 45.
It is input to one terminal of the R circuit 47. This OR circuit 4
The sel terminal is connected to the other terminal of 7
When the selection signal input to the l terminal is low level, the decode value selection circuit 45 outputs the decode value output from the column decoder 46 to the column selector 44 as it is.
Therefore, the column selector 44 selects any one column according to the decoded value, and the bit line pair B and bar B of the selected column is connected to the sense amplifier 4 via the data line.
7 and I / O circuit 48. When the selection signal input to the sel terminal becomes high level, each NO
All outputs of the R circuit 47 become high level regardless of other inputs. Therefore, all the N-channel MOSFETs that form the column selector 44 by this selection signal input
Is turned on, and the column selector 44 selects all columns.
Therefore, all the bit line pairs B and B are connected to the sense amplifier 47 and the I / O circuit 48 via the data lines.

The I / O circuit 48 is the I / O circuit in the above embodiment.
It is configured similarly to the O circuit 23. Therefore, the write and read operations are performed in the same manner as in the above embodiment, but the precharge is performed as follows. That is, when the precharge signal is asserted, the high-level selection signal is input to the sel terminal. Therefore, the column selector 44 is set to the all column selection state by the control of the decode value selection circuit 45 at the precharge timing. Therefore, the precharge voltage output from the I / O circuit 48 as described above is applied to the bit line pairs B and B of all columns via the data lines. Therefore, in the case of the present embodiment in which one bit information is associated with a plurality of columns to store information, the bit line pairs of all columns are precharged at one time.

As described above, also in this embodiment, the P-channel MOSFET of the write driver in the I / O circuit 48 is used.
Are used both for writing data to the bit line pair B and bar B and for precharging each bit line pair B and bar B. Therefore, P, which is conventionally provided only for precharge
The channel MOSFET becomes unnecessary, and the area of the memory chip is reduced in this embodiment as well, and the same effect as that of the above embodiment can be obtained.

[0032]

As described above, according to the present invention, the bit line drive circuit is used for both the data writing to the bit line and the precharge for the bit line, and the conventional transistor dedicated to the precharge is unnecessary. Become. When the column selection circuit selects a predetermined number of bit lines under the control of the decode value selection circuit, the bit line drive circuit precharges the predetermined number of bit lines at once. Therefore, the element forming region of the precharge-dedicated transistor is removed from the semiconductor memory chip forming the semiconductor memory device, and the area of the memory chip is reduced.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a schematic configuration of an SRAM according to an embodiment of the present invention.

FIG. 2 is a timing chart showing signals of various parts of SRAM in one embodiment.

FIG. 3 is a circuit block diagram showing a schematic configuration of an SRAM according to another embodiment of the present invention.

FIG. 4 is a circuit block diagram showing a schematic configuration of a conventional SRAM.

[Explanation of symbols]

21 ... Memory cell, 22 ... Sense amplifier, 23 ... I / O
AND circuit, 25, 29 ... NOT circuit, 26, 28, 32, 34 ... NOR circuit, 27, 33
... P-channel MOSFET, 30, 35 ... N-channel M
OSFET, 36 ... Buffer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 6866-5L G11C 11/34 353 F

Claims (4)

[Claims] 1. A plurality of memory cells for storing information, a word line connecting each of these memory cells in a row direction, a bit line connecting each of the memory cells in a column direction, and said bit line via said bit line. In a semiconductor memory device including a write circuit for writing data to a memory cell, the write circuit inputs write input data and a precharge signal and outputs the write input data at a write timing to output a precharge timing. 2. A semiconductor memory device, comprising: a signal selection circuit for outputting a precharge signal; and a bit line drive circuit for setting the bit line to a predetermined voltage according to the output of the signal selection circuit. 2. The signal selection circuit is a logical sum of a first gate circuit that outputs write input data at a write timing, a precharge signal, and write input data output from the first gate circuit. And a second gate circuit that outputs a signal, the bit line drive circuit includes a transistor that switches between two reference voltages, and when the signal output from the second gate circuit is write input data, The bit line is set to a voltage according to write input data, and when the signal output from the second gate circuit is a precharge signal, the bit line is set to one of the two reference voltages. 2. Precharging to
The semiconductor memory device described. 3. The signal selection circuit is a logical sum of a first gate circuit that outputs write input data at a write timing, a precharge signal, and write input data output from the first gate circuit. And a third gate circuit that outputs an inverted signal of write input data at a write timing. The bit line drive circuit has a drain set to one reference voltage. A first transistor having a first conductivity type channel whose gate is connected to the output of the second gate circuit, a drain connected to the source of the first transistor and a bit line, and a gate connected to the third gate 2. The semiconductor memory device according to claim 1, further comprising a second transistor connected to the output of the circuit and having a second conductivity type channel whose source is set to another reference voltage. 4. A column decoder which decodes an input column address, a column selection circuit which selects the bit line according to a decode value of the column decoder, and a decode value which is given from the column decoder to the column selection circuit. 4. The semiconductor memory device according to claim 1, further comprising a decode value selection circuit that switches to a value that selects a predetermined number of the bit lines according to a signal input.