JPH06187065A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To provide the clock switching circuit for switching the clock of a CPU with interruption and reducing power by selecting a clock generating circuit for which the more the number of times of interruption is increased, the higher the frequency is increased. CONSTITUTION:When an interruption request is permitted and the interruption is generated, an interruption counter is incremented. A comparator circuit 4 respectively compares the number of times of interruption at an interruption time counter 2 with an interruption time comparative value for selecting clocks at frequencies n1-n3, and the comparator circuit with coincidence generates select data. The clocks are outputted from clock generation circuits 51-53, to which the signal is inputted, to a multiplexer 6. The multiplexer 6 selects the clock at much higher speed from any one of clock generation circuits 5 and supplies the high-speed clock signal to a CPU 1. When interruption processing request signals are inputted while being overlapped during the interruption processing, the number of times of interruption counted by the interruption time counter 2 is increased, and the clock is switched to the clock at much higher speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching device for a central processing unit.

[0002]

2. Description of the Related Art A central processing unit (CPU) is usually
A single clock generation circuit is provided. If this CPU handles multiple events simultaneously, its single clock must be fast. The CPU terminates the processing of one event at high speed and executes the processing of another event. in this case,
Since a high-speed clock is used, it consumes a large amount of power and is unsuitable for a battery-driven system. However, if a low-speed clock is used for the purpose of low power, when a plurality of events are processed at the same time, the processing cannot be performed in time, which makes control impossible. Therefore, a plurality of clocks having different speeds are provided, a low-speed clock is used in the processing of a single event, and when a plurality of events occur, it is possible to switch to a clock having a speed as necessary.

[0003]

However, in a switching circuit that switches a clock by connecting a plurality of clock generation circuits to a CPU, a comparison circuit is provided between the CPU and each clock circuit, and a signal from the CPU is used. The clock generation circuit activated by the comparison circuit is switched. Here, in the clock switching, the CPU determines the switching timing and outputs a signal for the clock to be switched to the comparison circuit to perform the switching processing. Therefore, the clock switching requires processing by the CPU, and there is a problem that the switching timing is delayed.

An object of the present invention is to provide a clock switching circuit which switches the clock of the CPU by an interrupt and has a small power.

[0005]

In order to solve this problem, a clock switching device according to the present invention comprises a plurality of clock generation circuits for generating clock signals of different frequencies,
Correspond the number of interrupts that counts the number of times that the interrupt processing by an external interrupt signal overlaps, and the number of interrupts counted by the number of interrupts counters to the above multiple clock generation circuits. It is characterized in that it has a selection circuit for selecting a higher frequency clock generation circuit as it is larger, and a switching circuit for sending a clock signal generated by the clock generation circuit selected by the selection circuit to the central processing unit. Preferably, the selection circuit corresponds to each of the clock generation circuits and sets a plurality of comparison value registers for setting an interrupt count comparison value, and the interrupt count comparison values set in the respective comparison value registers and the interrupt count comparison value. And a comparison circuit for comparing the interrupt count of the interrupt count counter of 1) with the interrupt count counter, and selects the clock generation circuit corresponding to the comparison value register in which the interrupt count comparison value equal to the interrupt count is set. Further, preferably, in the above comparison value register, a comparison value of the number of interrupts can be set by the central processing unit.

[0006]

[Function] Since the clock selection / switching is automatically performed according to the number of interrupts counted by the interrupt counter,
The switching timing is fast and the load on the CPU is small.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a multiple interrupt CPU clock switching circuit. In this circuit, the CPU 1 includes three clock generation circuits 51, 52, 53, and a multiplexer 6
Thus, the clock is switched to a clock corresponding to the number of times the interrupt processing by the interrupt signal is duplicated. Interrupts from external events are made to be multiplexed so that a high-speed clock is required.

An interrupt request signal from the outside is sent to the CPU 1 N
It is input to the IPQ interrupt request terminal and the UP input terminal of the interrupt number counter 2, and the interrupt number is counted each time an interrupt occurs. Also, CPU1
Sends a signal from port 1 to the DOWN input terminal of the interrupt counter 2. This signal is generated when the interrupt process is completed. Before permitting an interrupt, the CPU 1 has a comparison value register 3 including three registers 31, 32 and 33.
, The number of times any clock is selected (interrupt count comparison value)
Is set from port 2. The three interrupt count comparison values correspond to the three clock generation circuits. Three comparators 41, 4
The comparator circuit 4 composed of 2 and 43 respectively compares the interrupt count counted by the interrupt counter 2 with the interrupt count comparison value of the comparison value register 3 to select a clock signal. Generate A, B, C. The select signals A, B, C are respectively supplied to the clock generation circuits 5
1, 52, and 53, and the selected clock circuit is activated and input to the selection terminal of the multiplexer 6. Each of the clock generation circuits 51, 52, 53 has a clock enable signal D1, D2, D of frequencies n1, n2, n3.
3 is sent to the multiplexer 6. The multiplexer 6 selects the clock signal indicated by the select data at the timing of the strobe signal STB from the clock circuit 5 and sends the clock signal to the CPU 1. Table 1 shows the clock switching situation.

[0009]

[Table 1]

The frequencies n1, n2, n3 generated by the clock generation circuits 51, 52, 53 are higher in this order. The interrupt count comparison values set in the registers 31, 32, and 33 are, for example, 0, 1, and 2. In the initial setting before the interrupt request is issued, the interrupt counter 2 is set to 0, and the register 31, the comparator 41, and the clock generation circuit 51 corresponding to the lowest speed clock are activated. When an event that requires a faster clock occurs, multiple interrupt requests are generated. Before permitting the interrupt, the CPU 1 uses the port 2 to register the registers 31 to 33.
Then, an interrupt count comparison value for selecting clocks of frequencies n1, n2, and n3 is set.

When an interrupt request is permitted and an interrupt occurs,
The interrupt counter 2 is incremented by +1. In the comparison circuits 41 to 43, the interrupt count of the interrupt counter 2 and
The interrupt count comparison values for selecting clocks of frequencies n1, n2, and n3 are compared with each other, and the coincident comparison circuits generate select data ('H'), while the other comparison circuits generate '
Output the L'signal. The signal is the clock generation circuit 5
The clock of the clock generating circuit to which the “H” signal is input is output to the multiplexer 6. The multiplexer 6 selects the higher speed clock from the clock generation circuit 5 according to the select data and supplies the high speed clock signal to the CPU 1. When the interrupt processing is completed, the value of the interrupt number counter 2 is decremented by 1 by the CPU 1 and returned to the original low speed clock. If the interrupt request signals are input in duplicate during the interrupt processing, the number of interrupts counted by the interrupt processing number counter 2 increases and the clock is switched to a higher speed clock.

As shown in FIG. 2, each clock generation circuit 5
1, 52, and 53 each include a clock oscillation circuit 56 having a different clock, and a delay circuit 97 that delays until the clock becomes stable. When the select data is input from the comparison circuit 4 and the corresponding clock oscillation circuit 56 is activated, the select data is also input to the delay circuit 57 at the same time. The delay circuit 57 generates the timing signal G after a predetermined time. This opens the AND gate 58, and then the output of the clock oscillation circuit 56 is output as a clock signal.

FIG. 3 shows a processing flow of the CPU 1.
When the CPU 1 is activated, the interrupt counter 2 is first reset (S1), and then the interrupt count comparison value (clock switching value) is set in the comparison value register 3 from the port 2 (S2). (Note that the comparison value does not necessarily have to be set from the CPU 1.) Then, system processing is performed (S
3). Here, the interrupt is permitted. FIG. 4 shows a flow of interrupt processing. When an interrupt request signal NIPQ is generated from the outside (S11), first, an interrupt process is performed (S11).
12). Here, the interrupt counter is incremented by one, compared with the interrupt count comparison value of the comparison value register 3, and select data corresponding to the matched interrupt count comparison value is output.
The clock generation circuit 5 is switched and the clock is output to the CPU 1. When the interrupt process is completed, the interrupt counter 2 is decremented by 1 from the port 1 (S12). Then, the interrupt count is compared with the interrupt count comparison value of the comparison value register 3, select data corresponding to the matched interrupt count comparison value is output, and the selected clock is output to the CPU 1.

In the embodiment described above, the clock is switched according to the number of interrupts of the interrupt counter 2.
This clock switching is automatically performed according to the interrupt after the interrupt is permitted. On the other hand, even after the interruption permission, CPU1
It is also possible to arbitrarily change the interrupt count comparison value in the comparison value register 3 from the port 2. This makes CP
U1 can also freely change the clock switching timing. It is also possible to stop the clock.

[0015]

The clock of the CPU can be automatically switched by an external interrupt. The clock circuit has low power.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock switching circuit.

FIG. 2 is a block diagram of a clock generation circuit.

FIG. 3 is a flowchart of processing of a CPU.

FIG. 4 is a flowchart of interrupt processing.

[Explanation of symbols]

1 ... CPU, 2 ... Interrupt number counter, 3 ... Comparison value register, 4 ... Comparison circuit, 5 ... Clock generation circuit, 6 ... Multiplexer.

Claims (3)

[Claims] 1. A plurality of clock generation circuits that generate clock signals of different frequencies, an interrupt number counter that counts the number of times that interrupt processing by an external interrupt signal overlaps, and an interrupt number counter. The number of interrupts generated is made to correspond to the plurality of clock generation circuits described above, and the larger the number of interrupts, the more the frequency of the clock generation circuit is selected by the selection circuit and the frequency of the clock generation circuit selected by the selection circuit. And a switching circuit for sending a clock signal to the central processing unit. 2. The selection circuit corresponds to each of the clock generation circuits, and a plurality of comparison value registers for setting interrupt count comparison values, and interrupt count comparison values set in each comparison value register. And a comparator circuit that compares the interrupt count of the above-mentioned interrupt count counter, and the comparator circuit selects the clock generation circuit corresponding to the comparison value register in which the interrupt count comparison value equal to the interrupt count is set. The clock switching circuit according to claim 1, wherein: 3. The clock switching circuit according to claim 2, wherein the comparison value register is capable of setting an interrupt count comparison value by a central processing unit.