JPH06140391A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for facilitating formation of a connection port and a metal wiring layer due to miniaturization by patterning and for manufacturing a semiconductor device with a high electrical reliability efficiently by reducing the surface step of an interlayer insulation film. CONSTITUTION:A polycrystalline silicon film 4 is formed on the surface of a semiconductor substrate 1 and further silicon nitride film 50 is formed on it. Silicon oxide film 8 with a lower hardness than the silicon nitride film 50 is formed so that the polycrystalline silicon film 4 and the silicon nitride film 50 are covered. The silicon oxide film 8 is flattened so that the surface of the silicon nitride film 50 is exposed. A silicon oxide film 39 is formed on the flattened silicon oxide film 8. Further, a first wiring layer 12 is formed on silicon oxide film 39.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an insulating layer with a highly flat surface.

[0002]

2. Description of the Related Art First, the structure of a conventional semiconductor device will be described.

FIG. 22 is a sectional view showing an example of a conventional semiconductor device. 22, isolation oxide film 2 having a film thickness of about 300 to 800 nm is formed on the surface of semiconductor substrate 1 made of silicon. Elements such as MOSFETs are formed in the regions separated by the isolation oxide film 2.

This MOSFET is composed of an impurity diffusion layer 6 forming a source / drain, a gate oxide film 3 and a polycrystalline silicon film 4 forming a gate. The impurity diffusion layer 6 forming the source / drain is formed on the surface of the semiconductor substrate 1. So as to straddle the impurity diffusion layer 6,
A gate oxide film 3 is formed on the surface of the semiconductor substrate 1. A polycrystalline silicon film 4 forming a gate is formed on the surface of the gate oxide film 3. A silicon oxide film 5 is formed on the surface of the polycrystalline silicon film 4. Sidewalls 7 are formed on the side walls of the polycrystalline silicon film 4 and the silicon oxide film 5.

A first interlayer insulating film 38 made of a silicon oxide film containing boron and phosphorus (hereinafter abbreviated as "BPSG film") is formed on the entire surface of the semiconductor substrate 1 on which the MOSFET is formed as described above. ing. A connection port is formed in the first interlayer insulating film 38, and the tungsten plug 1
1 is embedded.

A first wiring layer 12 is formed on the first interlayer insulating film 38. The first wiring layer 12 is connected to the impurity diffusion layer 6 and the polycrystalline silicon film 4 by the tungsten plug 11.

A second interlayer insulating film 40 is formed on the entire surface of the first interlayer insulating film 38 on which the first wiring layer 12 is formed so as to cover the first wiring layer 12. . A connection port is formed in the second interlayer insulating film 40, and the tungsten plug 21 is embedded therein.

A second wiring layer 22 is formed on the second interlayer insulating film 40. The second wiring layer 22 is connected to the first wiring layer 12 by the tungsten plug 21.

A passivation film 13 is formed on the entire surface of the second interlayer insulating film 40 on which the second wiring layer 22 is formed so as to cover the second wiring layer 22.

Next, a method of manufacturing the semiconductor device configured as described above will be described. 9 to 22 are cross-sectional views showing a conventional method for manufacturing a semiconductor device.

Referring to FIG. 9, a film thickness of 300 to 8 is formed on the surface of semiconductor substrate 1 made of silicon by a local oxidation method.
An isolation oxide film 2 having a thickness of about 00 nm is formed.

Referring to FIG. 10, a portion of semiconductor substrate 1 exposed from isolation oxide film 2 has a film thickness of 5 by a thermal oxidation method.
A gate oxide film 3 of about 30 nm is formed. Next, a polycrystalline silicon film 4 and a silicon oxide film 5 containing phosphorus and arsenic are deposited on the surface of the semiconductor substrate 1 by vapor phase epitaxy. These gate oxide film 3, polycrystalline silicon film 4 and silicon oxide film 5 are patterned by photolithography and RIE.

Referring to FIG. 11, polycrystalline silicon film 4,
Using the silicon oxide film 5 and the isolation oxide film 2 as a mask,
Impurity ions are implanted in the semiconductor substrate 1. By this ion implantation, the impurity diffusion layer 6 is formed on the exposed surface of the semiconductor substrate 1.

Referring to FIG. 12, a silicon oxide film 15 having a thickness of 50 to 300 nm is formed on the surface of semiconductor substrate 1 by the vapor phase epitaxy method.

Referring to FIG. 13, this silicon oxide film 1
5 is etched by the RIE method. By this etching, sidewalls 7 are formed on the sidewalls of the polycrystalline silicon film 4 and the silicon oxide film 5. The side wall 7, the silicon oxide film 5, and the isolation oxide film 2 are formed on the semiconductor substrate 1.
Impurity ions are implanted using the mask as a mask. By this ion implantation, the impurity diffusion layer 6 having a two-layer structure having a high impurity concentration portion and a low impurity concentration portion is formed. Further, by forming the impurity diffusion layer, a MOS transistor including the impurity diffusion layer 6, the gate oxide film 3 and the polycrystalline silicon film 4 is formed.

Referring to FIG. 14, a first interlayer insulating film 38 made of a BPSG film is deposited so as to cover elements such as MOS transistors formed on the surface of semiconductor substrate 1.

Referring to FIG. 15, the deposited first interlayer insulating film is heat-treated at a temperature of 800 ° C. to 1000 ° C. By this heat treatment, the first interlayer insulating film 38 having a smooth surface shape is obtained.

Referring to FIG. 16, the connection port 14 is formed in the first interlayer insulating film 38 having a smooth surface shape by the photolithography method and the RIE method. The impurity diffusion layer 6 or a part of the surface of the polycrystalline silicon film 4 is exposed from the connection port 14. The silicon oxide film 5 is also etched when the polycrystalline silicon film 4 is exposed.

Referring to FIG. 17, first interlayer insulating film 38
A tungsten thin film 11a is deposited on the entire surface of the substrate by vapor phase epitaxy.

Referring to FIG. 18, tungsten thin film 11
a is etched by the RIE method. By this etching, the tungsten thin film 11a other than in the connection port 14 is removed, and the tungsten plug 11 is formed in the connection port 14.

Referring to FIG. 19, first interlayer insulating film 38
An aluminum-copper alloy film, for example, is deposited on the surface of the substrate by the sputtering method, and then patterned by the photolithography method and the RIE method. By this patterning, the first wiring layer 12 is formed. At this stage, the first wiring layer 12 is electrically connected to the impurity diffusion layer 6 and the polycrystalline silicon film 4.

Referring to FIG. 20, first interlayer insulating film 38 is formed.
So as to cover the first wiring layer 12 formed on the surface of
The second interlayer insulating film 40 is formed. Here, since the second interlayer insulating film 40 is formed on the first wiring layer 12 made of a low melting point aluminum-copper alloy, it is similar to that used when forming the first interlayer insulating film 38. Planarization by high temperature heat treatment is impossible. Therefore, the second interlayer insulating film 4
A method different from the method for flattening the first interlayer insulating film 38 is used for flattening 0, but the detailed description thereof will be described later.

21, a connection port is formed in the planarized second interlayer insulating film 40 by the photolithography method and the RIE method, and the tungsten plug 1 described above is formed.
The tungsten plug 21 is formed by the same method as that of forming 1.

Referring to FIG. 22, second interlayer insulating film 40
A second wiring layer 22 is formed on the surface of the same as the first wiring layer 12. At this stage, the second wiring layer 22 is
It is electrically connected to the first wiring layer 12. Furthermore, the second
Second wiring layer 2 formed on the surface of the inter-layer insulating film 40 of
A passivation film 13 made of a silicon nitride film is formed so as to cover 2 by plasma vapor deposition.

Through the above steps, M on the silicon wafer
A semiconductor device in which OSFETs are integrated is manufactured.

Here, a method of forming the second insulating film 40 will be described.
It will be described with reference to the drawings. 23 to 27 are cross-sectional views showing a conventional method of forming the second insulating film 40.

Referring to FIG. 23, first interlayer insulating film 38
The first wiring layer 12 is formed on the above.

Referring to FIG. 24, the first wiring layer 12 is formed on the surface of the first interlayer insulating film 38 by plasma vapor deposition at a forming temperature of 300 to 450.degree.
A silicon oxide film 30 of about 0 to 800 nm is deposited.

Referring to FIG. 25, a spin-on-glass (SOG) method is performed on the silicon oxide film 30 by 2 to 3.
By repeating 20 times, the silicon oxide film 31 is formed by the SOG method. The silicon oxide film 31 formed by the SOG method has a smooth surface shape.

Referring to FIG. 26, silicon oxide film 30 and silicon oxide film 31 are etched back by the RIE method. By this etch back, the silicon oxide film 32 having the optimum film thickness is obtained.

Referring to FIG. 27, silicon oxide film 3 is formed on silicon oxide film 32 by plasma vapor deposition.
3 are deposited.

As described above, the second interlayer insulating film having a smooth plane shape is obtained. When forming the second interlayer insulating film, the silicon oxide film 33 is formed on the silicon oxide film 32 by plasma vapor deposition as described above for the following reason. That is, the insulating film in contact with the wiring layer made of an aluminum-copper alloy is required to have pressing stress and low hygroscopicity in order to ensure its reliability. However, the silicon oxide film formed by the SOG method usually has tensile stress and has higher hygroscopicity than the silicon oxide film formed by the plasma vapor deposition method. Therefore, it is necessary to cover the region that is in wide contact with the wiring layer with the silicon oxide film formed by the plasma vapor deposition method.

[0033]

In the conventional semiconductor device manufactured as described above, if the surfaces of the first and second interlayer insulating films 38 and 40 are poor in flatness, the following adverse effects occur.

First, FIG. 34 is a sectional view schematically showing a state in which the resist is exposed. Referring to FIG. 34, a resist 202 is applied on the surface of lower layer 201. The resist 202 is patterned into a desired shape using the mask 203. At this time, the exposure light is incident on the area 202a to be exposed by the mask 203 from the direction of the arrow A only. However, when there is a step in the lower layer 201, the exposure light is reflected in the arrow B direction by the step. Due to the reflection in the direction of the arrow B, the area 202b that is not originally exposed is exposed. That is, when the lower layer 201 has a step, the resist 202 is formed into a desired shape.
Is difficult to expose. Therefore, the resist 202
It is difficult to accurately pattern the pattern into a desired shape.

In particular, when the lower layer 201 is a reflective substrate such as Al, the reflection in the arrow B direction becomes even more intense. In order to prevent this reflection, for example, when the exposure light is i-line (365 nm), a TiN thin film is formed on the surface of Al by a sputtering method to prevent reflection (Anti).
Reflection (hereinafter, abbreviated as “ARC”) is used as a film to suppress reflection in the arrow B direction.

FIG. 35 is a sectional view schematically showing the optimum focus position when exposing the resist. Referring to FIG. 35, resist 202 is applied on the surface of lower layer 201. If there is a step on the surface of the lower layer 201, the thickness of the resist 202 varies depending on the part. If the thickness is different, the optimum focus position of the exposure light for exposing the resist 202 is different. That is, the optimum focus positions of the exposure light at the positions C and D are c and d, respectively. Therefore, when the exposure is performed by focusing on the position of C, the pattern at the position of D becomes defective in shape, as shown in FIG. Also,
When the exposure is performed by focusing on the position D, see FIG.
As shown in, the pattern at the position C has a defective shape.
Therefore, it is difficult to accurately pattern the resist 202 into a desired shape.

If there is a step in the lower layer 201 as described above,
The resist 202 cannot be accurately patterned into a desired shape. When etching is carried out using such a resist having a defective shape as a mask, the finished dimension may be distorted. There is a problem in that it is difficult to miniaturize the finished product due to the deviation of the finished dimensions, and it is difficult to form a connection port or a pattern of the metal wiring layer when the miniaturization is attempted.

Furthermore, if the surface of the interlayer insulating film is poor in flatness, the following problems will occur when the connection port is filled with a plug.

38 and 39 are a cross-sectional view and a plan view schematically showing a state in which an adverse effect is caused by embedding the connection port with a plug. Referring to these drawings, a plug 202 is formed at the connection port 201. With this plug 202, the upper conductive layer 203 and the lower conductive layer 20
4 is electrically connected. This plug 202
It is formed by etching the conductive layer deposited on the entire surface of the insulating layer 205. However, the insulating layer 2
When the surface of 05 is poor in flatness, residues 202a and 202b at the time of forming the plugs remain on the stepped portion of the surface of the insulating layer 205. The residue 202a may short-circuit the other wiring layers 206a and 206b. As described above, when the surface of the interlayer insulating film is poor in flatness, there is a problem in that a residue is generated on the surface residue portion and the electrical reliability such as a short circuit of the wiring layer is deteriorated.

In order to prevent the above-mentioned harmful effects, as a method of improving the surface flatness of the first interlayer insulating film 38, a method of raising the heat treatment temperature or a BP forming the first interlayer insulating film is used.
A method of increasing the concentration of impurities such as boron and phosphorus in the SG film can be considered. However, if the heat treatment temperature is increased, the depth of the impurity diffusion layer 6 becomes deeper than necessary, and in recent highly miniaturized semiconductor devices, MOSFE
The performance as T will be impaired. Further, if the impurity concentration is increased, the moisture resistance is deteriorated, so that the impurity concentration in the BPSG film forming the first interlayer insulating film 38 has an upper limit.

On the other hand, in order to form the second interlayer insulating film 40 flat, many steps are required as described above.

As a method for solving such a problem and flattening the interlayer insulating film at a low temperature, for example, a chemical mechanical polishing method (hereinafter, abbreviated as "CMP method") is a Journal.
ofElectrochemical Societ
y. Vol. 138, p. 1778. Hereinafter, a method for planarizing the interlayer insulating film by the CMP method will be described with reference to the drawings.

28 to 33 are cross-sectional views showing a method of manufacturing a semiconductor device using the planarizing method of the interlayer insulating film by the CMP method.

Referring to FIG. 28, through the steps similar to those described with reference to FIGS. 9 to 14, BP is formed so as to cover elements such as MOS transistors formed on the surface of semiconductor substrate 1.
A first interlayer insulating film 38 made of an SG film is deposited.

Referring to FIG. 29, the first interlayer insulating film 38 is flowed while flowing an abrasive containing colloidal silica as a main component.
Is mechanically polished. When the surface has irregularities, the first interlayer insulating film 38 is polished because the convex portions are polished.
Is flattened.

Referring to FIG. 30, the tungsten plug 11 and the first wiring layer 12 are formed on the planarized first interlayer insulating film 38 through the same steps as those described with reference to FIGS. 16 to 19. It is formed.

Referring to FIG. 31, first interlayer insulating film 38 is formed.
So as to cover the first wiring layer 12 formed on the surface of
The second interlayer insulating film 40 is formed thicker by the plasma vapor deposition method.

Referring to FIG. 32, second interlayer insulating film 40
Are planarized by the CMP method similar to the planarization of the first interlayer insulating film 38. Further, similarly, the tungsten plug 21 and the second wiring layer 22 are formed on the planarized second interlayer insulating film 40.

The flattening of the interlayer insulating film by the CMP method has an excellent feature that the flattening process can be performed at a low temperature in addition to the interlayer insulating film having extremely good flatness. ing. However, since the polishing rate in the CMP method strongly depends on the temperature of the polishing agent and the surface shape of the object to be polished, there is a problem that it is difficult to control the polishing amount. Therefore, when the polishing amount is insufficient, the unevenness of the base remains, which adversely affects the photolithography and the formation of the tungsten plug. On the other hand, if the polishing amount is too large, the structures located under the interlayer insulating film, such as the polycrystalline silicon film 4 and the first wiring layer 12, are damaged. Further, the CMP method may include an alkali metal such as potassium or sodium as a component of the polishing agent. Such an alkali metal becomes a movable ion in the gate oxide film 3 and causes a problem that the performance of the MOSFET is deteriorated.

In the above-mentioned conventional technique, it is difficult to give the interlayer insulating film sufficient flatness, so that the degree of integration of the semiconductor device is limited and the non-defective rate is lowered. On the other hand, C
Although the MP method can obtain an interlayer insulating film having excellent flatness, the controllability is poor and there is a problem of alkali metal contamination, so that the productivity of semiconductor devices cannot be increased.

The object of the present invention is to solve the above-mentioned problems,
To provide a method for efficiently manufacturing a semiconductor device having high electrical reliability by facilitating formation of a connection port and a metal wiring layer by patterning accompanying miniaturization by reducing the surface step of an interlayer insulating film. It is in.

[0052]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first conductive layer on a surface of a semiconductor substrate, and a step of forming a first hardness on the first conductive layer. Forming a first insulating layer, patterning the first conductive layer and the first insulating layer, and covering the semiconductor substrate and the patterned first conductive layer and the first insulating layer all. Forming a second insulating layer having a second hardness lower than the first hardness, and planarizing the second insulating layer so that the surface of the first insulating layer is exposed. The method includes the steps of forming a third insulating layer on the planarized surface and forming a second conductive layer on the third insulating layer.

Preferably, the step of planarizing the second insulating layer may be performed using a chemical mechanical polishing method.

As another preferred example, a silicon oxide film is used as the second insulating layer, and one antireflection film selected from an organic film, a TiN film and a silicon nitride film is used as the first insulating layer. It may be used.

[0055]

In the method of manufacturing a semiconductor device according to the present invention, the first insulating layer having the first hardness and the second insulating layer having the second hardness lower than the first hardness are formed, The second insulating layer is planarized so that the surface of the first insulating layer is exposed. Further, the planarization is performed using a chemical mechanical polishing method. Therefore, when the second insulating layer is polished by the chemical mechanical polishing method, the polishing rate becomes slower when the first insulating layer is exposed. Therefore, the polishing can be finished with good controllability.

The polishing rate of one antireflection film selected from the organic film, the TiN film and the silicon nitride film is about 25% or less of the polishing rate of the silicon oxide film. Therefore, one antireflection film selected from an organic film, a TiN film, and a silicon nitride film is formed as the first insulating layer, a silicon oxide film is formed as the second insulating layer, and chemical mechanical polishing is performed. When the silicon oxide film is polished by the method, the polishing rate becomes slow when the antireflection film is exposed. Therefore, the polishing can be finished with good controllability.

[0057]

1 is a sectional view showing the structure of a semiconductor device manufactured according to an embodiment of the present invention.

Referring to FIG. 1, this semiconductor device is shown in FIG.
Similar to the conventional semiconductor device shown in FIG. 2, the isolation oxide film 2 is formed on the surface of the semiconductor substrate 1 made of silicon,
In the region isolated by the isolation oxide film 2, a MOS
Elements such as FETs are formed.

This MOSFET is composed of an impurity diffusion layer 6, a gate oxide film 3 and a polycrystalline silicon film 4. On the surface of the polycrystalline silicon film 4 forming the gate,
The silicon oxide film 5 is formed in the conventional example shown in FIG. 22, but the silicon nitride film 50 is formed in this embodiment.

A silicon oxide film 8 is formed on the entire surface of the semiconductor substrate 1 on which the MOSFET is formed in such a manner that the surface of the silicon nitride film 50 is exposed. A silicon oxide film 39 is further formed on the silicon oxide film 8. The surface of the first interlayer insulating film composed of the silicon oxide film 8 and the silicon oxide film 39 has extremely high flatness.

The first wiring layer 12 is formed on the silicon oxide film 39, and the first wiring layer 12 is connected to the impurity diffusion layer 6 and the polycrystalline silicon film 4 by the tungsten plug 11. .

On the surface of the first wiring layer 12, a silicon nitride film 51, which was not formed in the conventional example, is formed.

A silicon oxide film 9 is formed on the entire surface of the silicon oxide film 39 on which the first wiring layer 12 is formed so that the surface of the silicon nitride film 51 is exposed. A silicon oxide film 41 is further formed on the silicon oxide film 9. The surface of the second interlayer insulating film composed of the silicon oxide film 9 and the silicon oxide film 41 has the first
Like the inter-layer insulating film of, the flatness is extremely high.

A second wiring layer 22 is formed on the silicon oxide film 41, and the second wiring layer 22 is connected to the first wiring layer 12 by a tungsten plug 21.

A passivation film 13 is formed on the entire surface of the silicon oxide film 41 having the second wiring layer 22 formed thereon so as to cover the second wiring layer 22.

Next, a method of manufacturing the semiconductor device configured as described above will be described. 2 to 8 and FIG.
[FIG. 7A] is a cross-sectional view showing the method of manufacturing the semiconductor device of the above-mentioned embodiment.

Referring to FIG. 2, a film thickness of 300 to 8 is formed on the surface of semiconductor substrate 1 made of silicon by a local oxidation method.
An isolation oxide film 2 having a thickness of about 00 nm is formed. A gate oxide film having a film thickness of 5 to 30 nm is formed on the portion of the semiconductor substrate 1 exposed from the isolation oxide film 2 by a thermal oxidation method. Next, a polycrystalline silicon film 4 containing phosphorus and arsenic and a silicon nitride film 50 are deposited on the surface of the semiconductor substrate 1 by a vapor phase growth method. These gate oxide film 3, polycrystalline silicon film 4 and silicon nitride film 50 are patterned by photolithography and RIE. When this polycrystalline silicon film 4 is patterned,
The silicon nitride film 50 acts as an ARC film. Then, impurity ions are implanted into semiconductor substrate 1 using polycrystalline silicon film 4, silicon nitride film 50 and isolation oxide film 2 as a mask. By this ion implantation, the semiconductor substrate 1
The impurity diffusion layer 6 is formed on the exposed surface of the.
Further, a silicon oxide film having a thickness of 50 to 300 nm is formed by the vapor phase epitaxy method, and the sidewall 7 is formed by the etching by the RIE method so that the side wall 7 is formed of the polycrystalline silicon film 4 and the silicon nitride film 50.
Is formed on the side wall of the. Also, the impurity diffusion layer 6 having a two-layer structure of a portion having a high impurity concentration and a portion having a low impurity concentration is formed by the implantation of the impurity ions. In this way, MO
The SFET is formed.

Referring to FIG. 3, PH ₃ is formed so as to cover elements such as MOSFET formed on the surface of semiconductor substrate 1.
A silicon oxide film 8 containing about 7% by weight of P ₂ O ₅ is deposited to a thickness of about 100 nm by a low pressure vapor deposition method using TEOS (Si (OC ₂ H ₅ ) ₄ ) and the like as raw materials.

Referring to FIG. 4, mechanical polishing is performed on the surface of the deposited silicon oxide film 8 for about 5 minutes while flowing a polishing liquid containing a polishing agent such as colloidal silica. . The surface of the deposited silicon oxide film 8 is flattened by polishing until a part of the silicon nitride film 50 is exposed. At this time, when the polished surface reaches the silicon nitride film 50, the polishing rate sharply decreases, so that the polishing amount can be easily controlled.

Referring to FIG. 5, a silicon oxide film having a thickness of about 50 nm is formed on the planarized silicon oxide film 8 by a low pressure vapor phase epitaxy method using TEOS (Si (OC ₂ H ₅ ) ₄ ) or the like as a raw material. A film 39 is formed. This silicon oxide film 8
A connection port is formed in the first interlayer insulating film made of and the silicon oxide film 39 by the photolithography method and the RIE method. Furthermore, a tungsten thin film is formed by a vapor phase growth method using WF ₆ or the like as a raw material, and a tungsten plug 11 is formed by etching by the RIE method. Next, the aluminum-copper alloy film 12a is deposited on the silicon oxide film 39 by the sputtering method, and a 50 nm-thick silicon nitride film 51 is further formed thereon by the vapor phase growth method using SiH ₄ and NH ₃ as raw materials. It is formed.

Referring to FIG. 6, aluminum-copper alloy film 1
The 2a and the silicon nitride film 51 are patterned by the photolithography method and the RIE method to form the first wiring layer 12. This aluminum copper alloy film 12a
When the silicon is patterned, the silicon nitride film 51 is
Acts as a C film.

Referring to FIG. 7, TE is formed so as to cover first wiring layer 12 formed on the surface of silicon oxide film 39.
A silicon oxide film 9 is deposited to a thickness of about 200 to 500 nm by plasma vapor deposition using OS as a raw material.

Referring to FIG. 8, a CM for the surface of the deposited silicon oxide film 9 is described in the same manner as described with reference to FIG.
Polishing is performed by the P method to flatten the surface. Also at this time,
When the polished surface reaches the silicon nitride film 51, the polishing rate sharply decreases, so that the polishing amount can be easily controlled.

Referring to FIG. 9, 200 n is formed on the planarized silicon oxide film 9 by plasma vapor deposition.
A silicon oxide film 41 of about m is formed. A tungsten plug 21 is formed on the second interlayer insulating film formed of the silicon oxide film 9 and the silicon oxide film 41 as in the conventional example.
Is formed. Further, after the second wiring layer 22 is formed, the passivation film 13 made of a silicon nitride film or the like is formed so as to cover the second wiring layer 22.

The wafer process for this semiconductor device is completed through the above steps. The film thickness and phosphorus concentration described in the above embodiments are not limited to the values shown above. Needless to say, the polishing time by the CMP method is not limited to the values described in the above examples because it strongly depends on the type of polishing agent and the type of polishing pad. Further, the silicon oxide film 8 containing phosphorus may be a BPSG film containing boron at the same time as phosphorus. The method for forming the silicon oxide film, the silicon nitride film, the wiring layer and the plug may be other than the method described in the above embodiment. Further, although the example of tungsten has been described in the present embodiment as the material of the plug,
It may be polycrystalline silicon or aluminum. Although the silicon nitride film was used as the ARC film in the patterning in the embodiment, any other film such as TiN, amorphous silicon, or an organic film having an optical property of absorbing the exposure light may be used. The device described in the above embodiments has two layers of wiring, but a semiconductor device having three or more wiring layers may be applied to the structure of the interlayer insulating film used between those wiring layers. In addition to the polishing of the silicon oxide film, the CMP method may be used for etching the tungsten film instead of the RIE method.

[0076]

As described above, according to the present invention, a semiconductor device having an interlayer insulating film having an extremely flat surface can be obtained with a smaller number of steps than the conventional method.

Further, according to the present invention, since it becomes easy to control the polishing amount, it becomes possible to flatten the interlayer insulating film by the CMP method.

Further, by forming the interlayer insulating film having high flatness, it becomes easy to pattern the conductive layer by the photolithography method and remove the conductive layer by etching, thereby improving the productivity and reliability of the semiconductor device. it can.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a first step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional view showing a second step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a sectional view showing a third step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a sectional view showing a fourth step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a sectional view showing a fifth step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a sectional view showing a sixth step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a sectional view showing a seventh step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a first step of a method for manufacturing an example of a conventional semiconductor device.

FIG. 10 is a cross-sectional view showing a second step of the manufacturing method of the conventional semiconductor device.

FIG. 11 is a cross-sectional view showing a third step of the manufacturing method of the conventional semiconductor device.

FIG. 12 is a cross-sectional view showing a fourth step of the method for manufacturing the conventional semiconductor device.

FIG. 13 is a sectional view showing a fifth step of the method for manufacturing the conventional semiconductor device.

FIG. 14 is a cross-sectional view showing a sixth step of the manufacturing method of the conventional semiconductor device.

FIG. 15 is a cross-sectional view showing a seventh step of the method for manufacturing the conventional semiconductor device.

FIG. 16 is a cross-sectional view showing an eighth step of the manufacturing method of the conventional semiconductor device.

FIG. 17 is a cross-sectional view showing a ninth step of the method for manufacturing the conventional semiconductor device.

FIG. 18 is a tenth manufacturing method of an example of a conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 19 is an eleventh manufacturing method of an example of a conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 20 is a twelfth example of the manufacturing method of the conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 21 is a thirteenth manufacturing method of an example of a conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 22 is a fourteenth manufacturing method of a conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 23 is a sectional view showing a first step of a conventional method for forming an interlayer insulating film.

FIG. 24 is a sectional view showing a second step of the conventional method for forming an interlayer insulating film.

FIG. 25 is a sectional view showing a third step of the conventional method for forming an interlayer insulating film.

FIG. 26 is a sectional view showing a fourth step of the conventional method for forming an interlayer insulating film.

FIG. 27 is a cross-sectional view showing a fifth step of the conventional method for forming an interlayer insulating film.

FIG. 28 is a first manufacturing method of another example of the conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 29 is a second manufacturing method of another example of the conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 30 is a third manufacturing method of another example of the conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 31 is a fourth manufacturing method of another example of the conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 32 is a fifth manufacturing method of another example of the conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 33 is a sixth manufacturing method of another example of the conventional semiconductor device.
It is sectional drawing which shows a process.

FIG. 34 is a cross-sectional view schematically showing a state in which the resist is exposed.

FIG. 35 is a cross-sectional view schematically showing an optimum focus position when exposing a resist.

FIG. 36 is a cross-sectional view schematically showing a state in which an adverse effect is caused by the focal position when exposing the resist.

FIG. 37 is a cross-sectional view schematically showing a state in which an adverse effect is caused by the focal position when exposing the resist.

FIG. 38 is a cross-sectional view schematically showing a state in which an adverse effect is caused by embedding the connection port with a plug.

[Fig. 39] Fig. 39 is a plan view schematically showing a state in which an adverse effect is caused by embedding the connection port with a plug.

[Explanation of symbols]

 1 semiconductor substrate 4 polycrystalline silicon film 8 silicon oxide film 9 silicon oxide film 12 first wiring layer 22 made of aluminum copper alloy 22 second wiring layer 39 silicon oxide film 41 silicon oxide film 50 silicon nitride film 51 silicon nitride film In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 27/108

Claims (3)

[Claims] 1. A step of forming a first conductive layer on a surface of a semiconductor substrate; a step of forming a first insulating layer having a first hardness on the first conductive layer; Patterning a first conductive layer and the first insulating layer, and the first hardness so as to cover all of the semiconductor substrate and the patterned first conductive layer and the first insulating layer. A second having a lower second hardness
Forming an insulating layer, planarizing the second insulating layer so that the surface of the first insulating layer is exposed, and forming a third insulating layer on the planarized surface. A method of manufacturing a semiconductor device, comprising: a forming step; and a step of forming a second conductive layer on the third insulating layer. 2. The step of planarizing the second insulating layer is performed using a chemical mechanical polishing method.
A method for manufacturing a semiconductor device as described above. 3. The second insulating layer is a silicon oxide film, and the first insulating layer is one antireflection film selected from an organic film, a TiN film and a silicon nitride film.
A method of manufacturing a semiconductor device according to claim 1 or 2.