JPH0548881A - Picture varying power processing system and device - Google Patents

Abstract

PURPOSE:To make it possible to perform picture reduction (enlarge) for multilevel picture data forming one picture element by plural bits with excellent reproducibility without being complicated by a hardware constitution and without the occurrence of character break, character transform, etc., even when the picture reduction (enlarge) of more than 1/2 is performed. CONSTITUTION:A reduction processing is divided into two stages. For instance, after picture data is reduced to 1/2<n> (n: integral number including 0) at a first stages A1, B1, a reduced picture of (1/2<n>) alpha is obtained by performing a picture reduction with an arbitrary set magnification alpha within the range of 1 to 1/2 for the reduced picture data. In this case, the picture reduction in a main scanning direction B and a sub-scanning direction A is not performed at a time and the constitution is much simplified by performing the picture reduction in each scanning direction A, B, successively. The reduction magnification is not always limited to 1/2<n>. If the range of magnification of the second reduction processing means A2, B2 is set to 1 to 1/P, the reduction of 1/P<n> (P: integral number) is enough. An enlarging processing in a similar system is possible by setting this P as a fraction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image scaling processing system comprising image data read by a facsimile, an image scanner or the like and a device therefor.
The present invention relates to a scaling method for multi-valued image data that generates pixels and an apparatus for the same.

[0002]

2. Description of the Related Art Conventionally, in a facsimile or image scanner, for example, a CCD functioning as an image reading unit is used.
It is configured to digitize the analog signal corresponding to the original image read by and transmit the digitized image data to the receiver side. Especially in recent years, the intermediate colors of photographs etc. are reproduced with good gradation. In order to enable the conversion, the analog signal corresponding to the original image is converted into multi-valued image data which forms one pixel with a plurality of bits, and then the image data is binary when output to a page printer or other printer side. The binarization processing (slicing at a predetermined binarization level (slice value)) is performed and the binarized signal is used to perform video expansion in the main scanning direction and the sub-scanning direction.

When an image is reduced in such an apparatus, generally, the image is reduced by performing a thinning control on the binarized signal (dot pattern) before output to the print engine side in correspondence with a predetermined magnification. However, when such a configuration is adopted, the characters are likely to be distorted even when the image is reduced by 1/2 or less, and the above-mentioned drawbacks are caused when the image is reduced by 1/2 or more. Not only increase further, but also cause a garbled phenomenon.

For this reason, it is preferable to reduce the image in the multi-valued stage before performing the binarization process. However, when the image is reduced in such a multi-valued stage, the area corresponding to a predetermined magnification is generally used. A method of obtaining the desired reduction pattern by multiplying and summing the reference pixels extracted corresponding to the ratio or the length ratio is adopted, but with such a configuration, it is reduced to 1/2 to 1/3. Requires 4 pixels when performing the above, and 5 pixels when reducing to ⅓ to 1/4. If the above-described product-sum operation processing method is adopted, a multiplier and an adder are provided for each reference pixel. Is required, resulting in a complicated hardware configuration.

In view of the above-mentioned drawbacks of the prior art, the present invention is reproducible without causing misshapen characters or garbled characters even if the image is reduced (enlarged) to 1/2 or more without complicating the hardware configuration. It is an object of the present invention to provide an image scaling processing method and an apparatus therefor that can reduce (enlarge) an image well.

[0006]

In order to achieve the above technical object, the present invention adopts an image reduction processing method of multi-valued image data in which one pixel is formed by a plurality of bits, but it is possible to obtain a desired image in one step. The reduction process is divided into two steps without reducing the magnification, and for example, in the first step, the image data is reduced to 1/2 ⁿ (n:
After being reduced to an integer including 0), the image data reduced to 1/2 ⁿ in the second step is reduced by an arbitrary set magnification α in the range of 1 to 1/2 (1/2 We propose an image reduction processing method characterized by obtaining a reduced image of ⁿ ) × α.

In this case, the structure is further simplified by sequentially performing the image reduction in each of the main scanning directions and the sub-scanning directions, not in one time, but in each scanning direction.

The reduction scale is not necessarily limited to 1/2 ^n, and the scale range of the second reduction processing means is 1 to 1
If it is set to / P, it may be reduced to 1 / P ⁿ (P: integer), and if P is set to a fraction, enlargement processing can be performed in the same manner as described above.

[0009]

In order to make it easier to understand the operation of the present invention, the case of using 2 for P will be described. According to the present technical means, the image data previously reduced to 1/2 ⁿ is reduced to the desired magnification α. Because it does, it looks like 1
Despite the limited reduction ratio of 1/2,
Set 0 to 0 to 1 to 0.5 times reduction ratio, set n to 1 to set 0.5 to 0.25 times reduction ratio, and set n to 2. By 0.25
A reduction ratio of 0.125 is obtained for each, and as a result, reduction processing in a wide range is possible.

Further, the scaling means for scaling to 1/2 ⁿ can be simply constructed by simply using a shift register.
Even in the second scaling means that scales an image at an arbitrary set scaling factor in the range of 1/2, the scaling process is performed because the scaling factor is limited and three reference pixels are sufficient. The circuit configuration is simplified without complicating the processing circuit or the coefficient generation circuit for performing the coefficient calculation corresponding to the magnification.

Further, according to the present invention, it is possible to carry out the scaling processing in the main scanning direction and the sub-scanning direction at the same time, but it is preferable to carry out the image scaling in the one side scanning direction (main / sub) individually. For example, even when setting a top margin or a left margin, one of the magnifications can be changed and the magnification can be easily changed (the magnifications in the main scanning direction and the sub scanning direction are different) without complicating the circuit configuration. ..

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described in detail below as an example with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, relative positions, etc. of the components described in this embodiment are not intended to limit the scope of the present invention thereto, but are merely illustrative examples. Not too much.

FIG. 1 is an overall block diagram showing an image reduction processing means according to an embodiment of the present invention. The structure will be described according to the flow of multi-valued image data.
B is a main scanning processing means, both of which are 1/2 ⁿ multipliers A1 and B.
1 and sum-of-products arithmetic circuits A2 and B2. First, multi-valued data forming one pixel with a plurality of bits is reduced in the sub-scanning direction, and then the reduced multi-valued data is subjected to main scanning processing means. It is configured to input to B and perform reduction processing in the main scanning direction.

Next, the internal structure of each processing means will be described. 1 is a sub-scanning coefficient generator and 1/2 ⁿ multiplier A1
When the target magnification T is 1 to 1/2, n is 0 and α is T.
If the magnification T is 1/2 to 1/4, n is 1,
α is set to T / 2, and when the magnification T is 1/4 to 1/8, n is set to 2 and α is set to T / 4. As a result, α can always be kept in the range of 0.5 to 1.0.

The 1/2 ⁿ multiplier A1 is composed of a shift circuit 2, a 16 KB SRAM 3 also serving as an adder, a scanning line delay device 4, a changeover switch 5 and a changeover control circuit 6, the operation procedure of which n is 0, In the case of 1 and 2, respectively, when n is 0, the multi-valued image data corresponding to the original image is obtained without performing the reduction process in advance with the 1/2 ⁿ multipliers A1 and B1. After delaying by one line and repeating, image data for three lines is written to the SRAM 3.

When n is 1 (2), the input pixel data is right-shifted by 1 bit in the shift circuit 2 and converted to 1/2 times (1/4 times), and then the SRAM 3 and the delay unit are provided. The corresponding image data (1,
The corresponding image data before two or three scanning lines are sequentially added) to generate one line of image data from 2 (4) lines and write it to the SRAM3, and the same is applied to the next and next lines. By repeating such addition operation, the image data for three lines is written in the SRAM3.

The product-sum operation circuit A2 includes a coefficient generator 12 and a register 11 for storing corresponding pixel data in the sub-scanning direction.
a, a 1-line delay circuit 13a interposed between the registers 11a, a multiplier 14a for multiplying the coefficient corresponding to the pixel data, and an adder for adding the data calculated by the multiplier 14a. It consists of 15.

Before describing the circuit operation, the coefficient generation algorithm in the coefficient generator 12 in this circuit will be briefly described. For example, in the case of 1 to 1/2 reduction, for example, 10 pixels are replaced with 5 to 10 pixels. Since it may be re-expressed by an arbitrary new pixel between them, if this is redistributed by the length ratio as shown in FIG. 2, the new pixel may be weighted by referring to three adjacent old pixels. Can understand. Therefore, three types of coefficients for weighting each corresponding pixel are sufficient,
The calculation formula is as follows. K _an = α + K _an− 1−1 (K _an−1 > 0) = α + K _an−1 (K _an−1 ≦ 0) K _bn = 1−K _an (K _an ≧ 1−α) = α (K _an <1−α) K _cn = 0, (K _an ≧ 1−α) = 1−α−K _an (K _an <1−α), and when α is 70%, the coefficient is shown in FIG. It becomes a value.

[0019] To briefly described next operation procedure of the product-sum operation circuit A2, 3 single pixel data adjacent in the sub-scanning direction, the 1/2 ⁿ while one scan line at a time delayed by the delay circuit 13a ... By calling from the multiplier A1, the pixel data corresponding to the sub-scanning direction is accurately stored in each register 11a.

The pixel data P _a , P _b , P _c stored in each register 11 a ... And the coefficients K _a , K _b , K _c generated by the coefficient generator 12 are integrated by the respective multipliers 14 a. Then, the weighted data is added, and the weighted data is added by the adder 15, and the data subjected to the scaling processing in the sub-scanning direction is input to the main scanning processing means, and the reduction processing is performed in the main scanning direction.

The main scanning processing means A is also composed of a 1/2 ⁿ multiplier B1 and a product-sum operation circuit B2, except that neither circuit has a one-line delay circuit 13a. Since it is the same as the data on the means A side, the description thereof is omitted. Incidentally, in the present embodiment, the reduction in the sub-scanning direction and the reduction in the main-scanning direction are sequentially performed individually, so that it is possible to make the reduction ratios different from each other.

In each of the processing means, in order to perform weighting, the number of multipliers 14a ... Corresponding to the number of reference pixels is required, and since the multipliers 14a ... Have a heavy load on hardware. The circuit configuration easily becomes complicated.

The invention described in FIG. 3 is intended to solve such a drawback, and limits the number of multipliers 14 incorporated in the product-sum operation circuits A2 and B2 to one, and corresponds to the sub (main) scanning direction. The selectors 16a are interposed between the registers 11a in which pixel data are stored and the multiplier 14 and between the coefficient generator 12 and the multiplier 14, respectively, and based on the timing signal from the timing control circuit 17, first, Pa · K _a
After being added by the multipliers 14a ..., The weighting data is latched in the latch circuit 18 via the adder 15.

Then, with the next and next higher timing signals, P
While adding b · K _b and Pc · K _c sequentially, each weighting data is sequentially added to the latch data by the adder 15. According to this embodiment, one multiplier 14 can achieve the same effect as the above embodiment.

[0025]

[Effect] As described above, according to the present invention, even if the image is reduced (enlarged) to 1/2 or more without complicating the hardware configuration, the image is reduced with good reproducibility without causing misalignment or garbled characters. (Enlargement) is possible. And so on.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an image reduction processing apparatus according to an embodiment of the present invention,

FIG. 2 is an operation diagram showing a coefficient generation algorithm in the product-sum calculation circuit shown in FIG.

FIG. 3 is an overall block diagram of an image reduction processing apparatus according to an embodiment of the present invention,

[Explanation of symbols]

A sub-scanning processing means, B main-scanning processing means A1, B1 1/2 ⁿ multiplier A2, B2 product-sum operation circuit

Claims (3)

[Claims] 1. In an image scaling processing method of multi-valued image data in which one pixel is formed by a plurality of bits, the image data is converted into 1 / P ⁿ (n: integer including 0, P: integer or fraction). After scaling, the image data scaled to 1 / P ⁿ is subjected to image scaling at an arbitrary set scaling factor α in the range of 1 to 1 / P, and thereby a scaled image of (1 / P ⁿ ) α is obtained. Image scaling method characterized by obtaining 2. An image scaling processing method, characterized in that the image scaling according to claim 1 is sequentially and individually performed for each one-side scanning direction (main / sub). 3. An image scaling processing device for multi-valued image data which forms one pixel with a plurality of bits, wherein the image data is converted into 1 / P ⁿ (n: integer including 0, P: integer or fraction). From the first scaling means for scaling and the second scaling means for scaling the image data scaled by the first scaling means at any set scaling factor in the range of 1 to 1 / P. Image scaling processor characterized in that