JPH05343399A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form contact holes which are smaller than the limit of lithography while preventing that yield of interlayer dielectric strength of an insulation film covering wirings is lowered. CONSTITUTION:A polycide film 13, an interlayer insulation film 24 and a polycrystalline Si film 25 are processed into the patterns of gate electrode and the interlayer insulation film 26 and polycrystalline Si film 27 are sequentially deposited on the entire part. The entire part of the polycrystalline Si film 27 is etched back, leaving polycrystalline Si film 27 in the form of a side wall. The interlayer insulation film 26 is etched using the polycrystalline Si film 27 as the mask and contact holes 17 are opened. In this case, the interlayer insulation film 26 is masked with the polycrystalline Si film 27 and the interlayer insulation film 24 is also masked by the Si film 25. Therefore, quality of interlayer insulation films 26, 24 is not deteriorated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having wiring and contact holes.

[0002]

2. Description of the Related Art FIG. 3A shows a semiconductor device having a gate electrode as a wiring and a contact hole, which is manufactured by a first conventional example of the present invention called a self-aligned contact method. Shows. In this first conventional example, Si
After forming the SiO ₂ film 12 as a gate oxide film on the surface of the element active region of the substrate 11, and a SiO ₂ film 14 for the polycide film 13 or polycrystalline Si film and the offset are sequentially stacked, these SiO ₂ Membrane 14 and polycide membrane 1
3 and the like are processed into a pattern of a gate electrode.

After that, a SiO ₂ film 15 is deposited on the entire surface, and the entire surface of the SiO ₂ film 15 is etched back to obtain S
The side wall made of the iO ₂ film 15 is covered with the polycide film 13 and Si.
At the same time as being formed on the side surface of the O ₂ film 14, a contact hole 17 reaching the diffusion layer 16 in the Si substrate 11 is opened. Then, an upper wiring that contacts the diffusion layer 16 through the contact hole 17 is formed of the polycrystalline Si film 18.

In the first conventional example as described above, the contact hole 1
No mask is required for opening 7 and contact hole 1
7 can be formed in self-alignment with the polycide film 13. Therefore, if the distance between the polycide films 13 is set to the limit of lithography, the contact hole 17 smaller than the limit of lithography can be formed, so that a highly integrated semiconductor device can be manufactured.

FIG. 4 shows a semiconductor device having a gate electrode as a wiring and a contact hole, which is manufactured by a second conventional example of the present invention called a matching contact system. In the second conventional example, the polycide film 13 is used.
After forming the gate electrode with, the interlayer insulating film 21 and the reduced pressure CV
The SiN film 22 by the D method is sequentially laminated. Then, a contact hole 17 is formed in the SiN film 22 and the interlayer insulating film 21 by etching using a resist (not shown) as a mask, and an upper wiring layer is formed by the polycrystalline Si film 18.

[0006]

However, as shown in FIG.
In the first conventional example shown in, the polycide film 13 and the polycrystalline S
Most of the interlayer isolation film between the i layer 18, a SiO ₂ film 15 sidewall-shaped film quality is inferior to that formed by etching back polycrystalline polycide film 13 via the SiO ₂ film 15 The area where the Si film 18 faces is large.
Therefore, in the first conventional example, the yield of the interlayer breakdown voltage between the polycide film 13 and the polycrystalline Si film 18 was low, and the semiconductor device could not be manufactured with a high yield.

Moreover, as shown in FIG. 3B, when the polycide film 13 has a protrusion 13a or a pattern abnormality, the film thickness of the side wall-shaped SiO ₂ film 15 formed by etching back becomes thin at this portion, Polycide film 13 and polycrystalline Si film 18
The yield of the interlayer withstand voltage between and is particularly low in this portion.

On the other hand, in the second conventional example shown in FIG.
The film quality of the N film 22 is dense, and pinholes are unlikely to occur in the portion where the SiN film 22 and the interlayer insulating film 21 are laminated. For this reason, the portion of the interlayer insulating film 21 having poor film quality has contact holes 17 opened by etching.
It is only the part facing. However, since the area of this portion is small, the yield of the interlayer breakdown voltage between the polycide film 13 and the polycrystalline Si film 18 is high.

However, in the second conventional example, since the contact hole 17 is opened by etching using a resist as a mask, the contact hole 17 cannot be made smaller than the limit of lithography, and moreover, the polycide film 13 is used.
A margin for alignment is required between the contact hole 17 and the contact hole 17. Therefore, in the second conventional example, it was not possible to manufacture a semiconductor device having a high degree of integration.

[0010]

In the method of manufacturing a semiconductor device according to the present invention, the conductive film 13, the first insulating film 24 and the first coating film 25, which are sequentially stacked, are processed into a wiring pattern. A step of forming a second insulating film 26 having a different etching characteristic from that of the first coating film 25 on the entire surface after this processing, and a step of forming the second insulating film 26 covering the pattern. A step of forming a side wall of a second coating film 27 having a different etching characteristic from that of the second insulating film 26 on the side portion, and using the first and second coating films 25 and 27 as a mask By etching the second insulating film 26,
And the step of forming the contact hole 17 in the insulating film 26.

[0011]

In the method of manufacturing a semiconductor device according to the present invention, when the second insulating film 26 for forming the contact hole 17 is etched, the second insulating film 26 on the side of the wiring is covered with the second coating film 27. Masked with, and the first insulating film 24 on the wiring
Is also masked by the first coating film 25. Therefore, when forming the contact hole 17, the first and second insulating films 2 are formed.
The portions of the wirings 4 and 26 that cover the wirings are not etched, and the film quality of the first and second insulating films 24 and 26 can be maintained to prevent the yield of interlayer breakdown voltage from decreasing. ..

Moreover, the side wall-shaped second coating film 27 can be formed in a self-aligned manner with respect to the wiring by etching back the entire surface after deposition, and the contact hole 17 is formed in the side wall-shaped second coating film 27. Since the contact hole 17 is formed by etching using the coating film 27 and the like as a mask, the contact hole 17 can also be formed in self-alignment with the wiring. Therefore,
If the distance between the wirings is set to the limit of lithography, the contact hole 17 smaller than the limit of lithography can be formed.
Can be formed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to the manufacture of DRAM will be described below with reference to FIGS. The components corresponding to those of the first and second conventional examples shown in FIGS. 3 and 4 are designated by the same reference numerals.

In this embodiment, as shown in FIG.
Si for element isolation is formed on the surface of the Si substrate 11 by the OCOS method or the like.
The O ₂ film 23 is formed, and the SiO ₂ film 1 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 23.
Form 2. Then, the polycide film 13 or the polycrystalline Si film, the interlayer insulating film 24 which is a SiO ₂ film having a film thickness of about 1000 Å and containing no impurities, and a film thickness of 1000 to
A polycrystalline Si film 25 of about 3000 Å is sequentially deposited.

After that, the polycrystalline Si film 25 and the interlayer insulating film 2
4 and the polycide film 13 are continuously subjected to RIE using a resist (not shown) having the same gate electrode pattern as a mask. Then, using the polycide film 13 having the pattern of the gate electrode, the interlayer insulating film 24, and the polycrystalline Si film 25 as a mask, for example, phosphorus is applied at an energy of about 20 to 40 keV to about 1 × 10 ^{13 to} 5 × 10 ¹³ cm ^−2. To the Si substrate 11 by implanting ions at a dose of
Is formed in the element active region.

Next, a PSG film or a SiO ₂ film containing no impurities is deposited by the CVD method to a film thickness of several hundred to several thousand Å, and a SiN film is further deposited by the low pressure CVD method to a film thickness of several hundred Å. Then, the interlayer insulating film 26 is formed of these two layers as shown in FIG. Then, the polycrystalline Si film 27 is deposited by the low pressure CVD method to a film thickness of several hundred to several thousand Å. However,
In order to increase the degree of integration, the film thickness of the polycrystalline Si film 27 is preferably thin.

Next, RI is applied until the interlayer insulating film 26 is exposed.
The polycrystal Si film 27 is anisotropically etched by E to form a side wall of the polycrystal Si film 27 on the side portion of the interlayer insulating film 26 covering the polycide film 13 and the like as shown in FIG. 1C. Leave on.

Then, RIE is performed on the interlayer insulating film 26 by using the polycrystalline Si film 27 as a mask to open the contact hole 17 reaching the diffusion layer 16 in a self-aligned manner with respect to the polycide film 13 and the like. At this time, even if the interlayer insulating film 26 on the polycrystalline Si film 25 is etched, the polycrystalline Si film 2
The interlayer insulating film 24 is not etched because 5 serves as a stopper. That is, the polycrystalline Si film 25 serves as a mask for the interlayer insulating film 24.

After that, the diffusion layer 16 and the polycrystalline Si film 27,
25 so that the polycrystalline Si film 28 is CV
Deposit a thickness of several hundred Å by method D. Then, the polycrystalline Si films 28, 27, 2 are formed by ion implantation or predeposition.
After doping 5 or 5 with phosphorus or arsenic, a resist 29 is processed on the polycrystalline Si film 28 into a pattern of an extraction electrode.

Next, using the resist 29 as a mask, the polycrystal Si films 28, 27 and 25 are sufficiently anisotropically etched to store the capacitors constituting the memory cells as shown in FIG. 1D. A lead electrode for the node electrode and a lead electrode for the bit line are formed. After that, the DRAM is completed through conventionally known steps.

In this embodiment as described above, the contact hole 1
When RIE is performed on the inter-layer insulation film 26 for opening the holes 7, the poly-Si films 27, 25 are used as the inter-layer insulation films 26, 24.
Are masked. Therefore, the interlayer insulating films 26 and 24 in the portion covering the polycide film 13 are not etched, and the film quality of the interlayer insulating films 26 and 24 in this portion does not deteriorate.

Further, since the interlayer insulating films 26 and 24 covering the polycide film 13 are not etched, as shown in FIG. 2, even if the polycide film 13 has a protrusion 13a or a pattern abnormality, the interlayer insulating film 26 is not etched. The thickness of the film does not become thin at this portion. Therefore, the yield of the interlayer breakdown voltage between the polycide film 13 and the polycrystalline Si films 28, 27, 25 is high.

[0023]

In the method of manufacturing a semiconductor device according to the present invention, when the contact hole is formed, the yield of the interlayer withstand voltage of the insulating film covering the wiring is prevented from being lowered, and it is smaller than the limit of lithography. Since the contact hole can be formed, a semiconductor device having a high degree of integration can be manufactured with a high yield.

[Brief description of drawings]

FIG. 1 is a side sectional view sequentially showing an embodiment of the present invention.

FIG. 2 is a side sectional view for explaining one embodiment.

FIG. 3 shows a first conventional example of the present invention, (a) is a side sectional view of a DRAM manufactured in the first conventional example, and (b) is a side sectional view for explaining the first conventional example. Is.

FIG. 4 is a side sectional view of a DRAM manufactured in a second conventional example of the present invention.

[Explanation of Codes] 13 Polycide Film 17 Contact Hole 24 Interlayer Insulating Film 25 Polycrystalline Si Film 26 Interlayer Insulating Film 27 Polycrystalline Si Film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/90 D 7735-4M 27/108

Claims (1)

[Claims] 1. A step of processing a conductive film, a first insulating film, and a first coating film, which are sequentially laminated, into a wiring pattern, and, after this processing, the first coating film is A step of forming a second insulating film having different etching characteristics on the entire surface, and a step of forming a second insulating film on the side surface of the second insulating film covering the pattern,
A step of forming a second coating film having a different etching characteristic from that of the second insulating film in a sidewall shape; and etching the second insulating film using the first and second coating films as a mask. And a step of forming a contact hole in the second insulating film.