JPH05308274A - Cmos level shift circuit - Google Patents

Abstract

PURPOSE:To obtain a signal output of a high voltage level with a constant current in the circuit configuration employing a MOS transistor(TR) with a small gate-source breakdown voltage. CONSTITUTION:Each source and each drain of 1st and 2nd P-channel MOS TRs 10, 13 are connected between each drain of 3rd and 4th P-channel MOS transistors(TRs) 9, 12 whose sources are connected to a power supply voltage source and each drain of 1st and 2nd N-channel MOS TRs 11, 14 whose sources connect to ground, and a voltage not in excess of a voltage difference between a power supply voltage VDD and a source-gate breakdown voltage BVGS of the 1st and 2nd P-channel MOS TRs is applied to gates of the 1st and 2nd P-channel MOS TRs 10,13 as a prescribed bias voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal having a small voltage level difference with respect to a reference voltage level (hereinafter referred to as a "low voltage level signal") to a signal having a large voltage level difference with respect to a reference voltage level (hereinafter referred to as "high voltage level"). Of the CMOS level shift circuit for obtaining the signal ".

[0002]

2. Description of the Related Art In recent years, C has been used as a driver for large current output.
With the increasing use of MOS, higher breakdown voltage and higher voltage output of CMOS are becoming indispensable. The conventional CMOS level shift circuit will be described below. Figure 2
FIG. 6 is a circuit diagram showing a configuration of a conventional CMOS level shift circuit.

As shown in FIG. 2, a conventional CMOS level shift circuit uses p-type MOS transistors 22 and 25 as drivers, and p-type MOS transistors 22 and 25 and n-type MOS transistor 2 connected in series.
The n-type MOS transistors 23 and 26 are respectively inserted between the 4 and 27, and the n-type MOS transistors 23 and 26 are inserted.
The respective gates are commonly connected to the bias terminal BIAS, and an output is obtained from the output terminal OUT which is a connection point of the drains of the p-type MOS transistors 22 and 25 and the drains of the n-type MOS transistors 23 and 26.

By applying the bias voltage V _B shown in [Equation 1] to the bias terminal BIAS, the source potential V _S of the n-type MOS transistors 23 and 26 becomes as shown in [Equation 2].

[0005]

[Formula 1] V _B = (V _DD + V _EE ) / 2

[0006]

## EQU2 ## V _S = (V _DD + V _EE ) / 2-V _th n-type MOS transistors 24 and 27 have n-type MO gates.
The through current is reduced by connecting to the drains of the S transistors 25 and 22. In such a CMOS level shift circuit, by inputting a low voltage level signal to the input terminal IN of the inverter 21, a high voltage level signal can be obtained from the output terminal OUT.

[0007]

However, in the conventional CMOS level shift circuit configured as described above,
Since the p-type and n-type MOS transistors 22 to 27 have a circuit configuration in which a high voltage is applied between the gate and the source, each of the MOS transistors 22 to 27 has a gate.
It is necessary to use one with a large source breakdown voltage BV _GS .

Normally, the MOS transistor has a structure that the source-drain breakdown voltage BV _SD can be easily secured, but it is difficult to secure the gate-source breakdown voltage BV _GS . An object of the present invention is to solve the above-mentioned problems of the related art and to achieve a small gate-source breakdown voltage M.
It is an object of the present invention to provide a CMOS level shift circuit capable of obtaining a signal output at a high voltage level with a constant current by a circuit configuration using OS transistors.

[0009]

A CMOS level shift circuit according to the present invention has a first inverter in which a low voltage level signal is input to an input terminal, a gate connected to the output terminal of the inverter, and a source grounded. The first conductivity type MOS transistor, the gate is connected to the input terminal of the inverter, the source is grounded to the second first conductivity type MOS transistor, the gate is connected to the output terminal of the inverter, and the drain is connected to the output terminal. , A third first-conductivity-type MOS whose source is grounded
A transistor, a first second conductivity type MOS transistor in which a predetermined bias voltage is applied to the gate, and a drain is connected to the drain of the first first conductivity type MOS transistor; and a gate is a first second conductivity type MOS transistor. A second second conductivity type MO connected to the gate of the transistor and having a drain connected to the drain of the second first conductivity type MOS transistor.
An S-transistor, a third second-conductivity-type MOS transistor whose drain is connected to the source of the first second-conductivity-type MOS transistor and whose source is connected to a power supply voltage source, and its gate is the third second-conductivity Type MOS transistor drain connected to the drain of the second second conductivity type M
Source of OS transistor and third second conductivity type MO
A fourth second-conductivity-type MOS transistor connected to the gate of the S-transistor and having a source connected to the power supply voltage source, a gate connected to the drain of the fourth second-conductivity-type MOS transistor, and a drain connected to the third It is provided with a fifth second-conductivity-type MOS transistor connected to the drain and output terminal of the first-conductivity-type MOS transistor and having a source connected to a power supply voltage source.

[0010]

According to the structure of the present invention, the drains of the third and fourth second conductivity type MOS transistors having their sources connected to the power supply voltage source and the first and second drains having their sources grounded.
Source and drain of the first and second second-conductivity-type MOS transistors are connected to the respective drains of the first-conductivity-type-MOS-transistors, and the first and second second-conductivity-type MOS transistors are connected. A predetermined bias voltage is applied to the gate of the. The power supply voltage and the first and second second conductivity type MOSs are used as the predetermined bias voltage.
By applying a voltage that does not exceed the voltage difference between the source-gate withstand voltage of the transistor, the voltage applied between the source-gate of the first and second second conductivity type MOS transistors is increased. It will be less than the voltage.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A CMOS level shift circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a CMOS level shift circuit according to an embodiment of the present invention.

In FIG. 1, IN is an input terminal for a signal having a small voltage level difference with respect to a reference voltage level (hereinafter referred to as "low voltage level signal"), 8 is an inverter operated by a low voltage level signal, and 11 is a first inverter. 1 n-type MOS transistor, 14 a second n-type MOS transistor, 16
Is a third n-type MOS transistor, 10 is a first p-type M
An OS transistor, 13 is a second p-type MOS transistor, 9 is a third p-type MOS transistor, 12 is a fourth p-type MOS transistor, and 15 is a fifth p-type MOS transistor.

As shown in FIG. 1, a low voltage level signal is input to the input terminal IN of the inverter 8. The gate of the second n-type MOS transistor 14 is connected to the input terminal IN of the inverter 8, and the first and third n-type MOS transistors 11 and 11 are connected to the output terminal of the inverter 8.
16 gates are connected. The sources of the first, second and third n-type MOS transistors 11, 14 and 16 are connected to the ground terminal V _SS .

Further, the first n-type MOS transistor 11
The drain of the first p-type MOS transistor 10 is connected to the drain of the second n-type MOS transistor 14
The drain of the second p-type MOS transistor 13 is connected to the drain of the
The gates of the transistors 10 and 13 are commonly connected to the bias terminal BIAS, and a predetermined bias voltage V
_{As B} , the voltage shown in [Equation 3] is applied.

[0015]

Equation 3] V _B ≦ V _DD -BV _GS However, V _DD is the supply voltage, BV _GS shows the source-gate breakdown voltage of the p-type MOS transistor 10 and 13. The source of the first p-type MOS transistor 10 is connected to the drain of the third p-type MOS transistor 9 and the gate of the fourth p-type MOS transistor 12, and the source of the second p-type MOS transistor 13 is connected. The third and fifth
Of the p-type MOS transistors 9 and 15 and the fourth
The drain of the p-type MOS transistor 12 is connected. The sources of the third, fourth and fourth p-type MOS transistors 9, 12 and 15 are connected to the power supply voltage source.

Further, the third n-type MOS transistor 16
And the fifth p-type MOS transistor 15 are connected to the output terminal OUT. C configured in this way
In the MOS level shift circuit, the first and second p-type MOS transistors 1 connected to the bias terminal BIAS
By applying the voltage shown in [Equation 3] as the bias voltage V _B to the gates of 0 and 13 and inputting the signal of the low voltage level to the input terminal IN of the inverter 8, the voltage level with respect to the reference voltage level is output from the output terminal OUT. A signal with a large difference (hereinafter referred to as a "high voltage level signal") is obtained. For example,
By inputting a low voltage level signal having a logical value "1" to the input terminal IN of the inverter 8, the first and third n-type MOS transistors 11 and 16 are turned off, and the second n-type MOS transistors 11 and 16 are turned off.
The n-type MOS transistor 14 is turned on. Accordingly, the first p-type MOS transistor 10 to which the bias voltage is applied is turned on, the second p-type MOS transistor 13 is turned off, and the third p-type MO transistor 10 is turned on.
The S transistor 9 is turned on, and the fourth p-type MOS
The transistor 12 is turned off, and the fifth p-type MOS transistor 15 is turned on. As a result, a high voltage level signal having a logical value "1" can be obtained at the output terminal OUT. In addition, by inputting a low voltage level signal having a logical value “0” to the input terminal IN of the inverter 8, the first n-type MOS transistors 11 and 16 are input.
Is turned on, and the second n-type MOS transistor 14 is turned on.
Is turned off. Along with this, the first p-type MOS transistor 10 to which the bias voltage is applied is turned off, the second p-type MOS transistor 13 is turned on, and the third p-type MOS transistor 9 is turned off. The fourth p-type MOS transistor 12 is turned on, and the fifth p-type MOS transistor 15 is turned off. As a result, a high voltage level signal having a logical value "0" can be obtained at the output terminal OUT.
As a result, the power supply voltage V _DD or the ground voltage V _SS is output to the output terminal OUT.

In the CMOS level shift circuit thus constructed, the transistor sizes of the first, second and third n-type MOS transistors 11, 14, 16 are set to the first, second, third, fourth and fifth. By making it larger than the p-type MOS transistors 9, 10, 12, 13, 15 of
First, second and third n-type MOS transistors 11,
The threshold voltage of 14 and 16 is lowered below 1/2 V _DD , so that even if the signal is at a low voltage level, the first, second and third n-type MOS transistors 11, 14 and 16 are surely turned on and turned on. It can be in a non-conducting state.

Further, the first and second p-type MOS transistors 10 and 13 commonly connected to the bias terminal BIAS.
By applying the bias voltage V _B shown in [Equation 3] to the gate of, the voltage applied between the source and gate of the first and second p-type MOS transistors becomes equal to or lower than the source-gate withstand voltage. Further, the gate of the third p-type MOS transistor 9 and the drain of the fourth MOS transistor 12 are connected, and the gate of the fourth p-type MOS transistor 12 and the drain of the third p-type MOS transistor 9 are connected. Further, by connecting the gate of the fifth p-type MOS transistor 15 to the drain of the fourth p-type MOS transistor 12, the through current can be reduced and a low quiescent current can be realized.

As described above, according to the embodiment, the drains of the third and fourth p-type MOS transistors 9 and 12 whose sources are connected to the power supply voltage source and the first and second n-types whose sources are grounded. The sources and drains of the first and second p-type MOS transistors 10 and 13 are connected to the drains of the MOS transistors 11 and 14, respectively, and the first and second p-type MOS transistors 10 and 13 are connected.
As a predetermined bias voltage, a voltage which does not exceed the difference voltage between the power supply voltage V _DD and the source-gate withstand voltage BV _{GS of} the first and second p-type MOS transistors is applied to the gate of The voltage applied between the source and gate of the second p-type MOS transistor is not more than the source-gate withstand voltage BV _GS .

Therefore, the source-gate withstand voltage BV
Each M has a circuit configuration with a small _GS MOS transistor.
By operating the OS transistor, a high voltage level signal can be obtained with a constant current from a low voltage level signal. In this embodiment, the power supply voltage V _DD is set higher than the ground potential V _SS , and the first to third n-type MOS transistors 11 and 1 are used as the first to third first conductivity type MOS transistors.
4, 16 are n-channel type, and the first to fifth second conductivity type MOS transistors are p-channel type using the first to fifth n-type MOS transistors 10, 13, 9, 12, and 15. However, the power supply voltage V _{DD is set} to the ground potential V
_If it is smaller than _SS , the first to third first conductivity type MOS transistors are p-channel type, and the first to fifth second conductivity type MOS transistors are n-channel type, the circuit configuration similar to the embodiment is obtained. It is possible to realize a CMOS level shift circuit with which the same effect can be obtained.

[0021]

According to the CMOS level shift circuit of the present invention, the third and fourth sources whose sources are connected to the power supply voltage source are provided.
Between the drains of the second conductivity type MOS transistors and the drains of the first and second first conductivity type MOS transistors whose sources are grounded, the first and second second conductivity type MOS transistors The source and each drain are connected, and a predetermined bias voltage is applied to the gates of the first and second MOS transistors of the second conductivity type. By applying, as the predetermined bias voltage, a voltage that does not exceed the difference voltage between the power supply voltage and the source-gate withstand voltage of the first and second second conductivity type MOS transistors, the first and second second The voltage applied between the source and the gate of the conductivity type MOS transistor is less than the withstand voltage between the source and the gate.

As a result, with a circuit configuration of MOS transistors having a small withstand voltage between the source and gate, each MOS transistor can be operated to obtain a high voltage level signal at a constant current from a low voltage level signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a CMOS level shift circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a conventional CMOS level shift circuit.

[Explanation of symbols]

8 Inverter 11 1st n-type MOS transistor (1st 1st conductivity type MOS transistor) 14 2nd n-type MOS transistor (2nd 1st conductivity type MOS transistor) 16 3rd n-type MOS transistor (1st Third first-conductivity-type MOS transistor) 10 First p-type MOS transistor (first second-conductivity-type MOS transistor) 13 Second p-type MOS transistor (second-second-conductivity-type MOS transistor) 9 Third P-type MOS transistor (third second conductivity type MOS transistor) 12 Fourth p-type MOS transistor (fourth second conductivity type MOS transistor) 15 Fifth p-type MOS transistor (fifth second conductivity type) Type MOS transistor) OUT output terminal

Claims (1)

[Claims] 1. An inverter having a low voltage level signal input to an input terminal; a first first-conductivity-type MOS transistor having a gate connected to the output terminal of the inverter and a source grounded; and a gate having the inverter. A second first-conductivity-type MOS transistor that is connected to the input end of the inverter and whose source is grounded; and a third first grounded transistor whose gate is connected to the output terminal of the inverter, whose drain is connected to the output terminal, and whose source is grounded. A conductive type MOS transistor, a first second conductive type MOS transistor having a gate connected to a drain of the first first conductive type MOS transistor with a predetermined bias voltage applied thereto, and a gate having the first conductive type MOS transistor. It is connected to the gate of a second conductivity type MOS transistor, and the drain is the second first conductivity type MOS transistor.
Second second conductivity type M connected to the drain of the transistor
A transistor of an OS transistor, a third second conductivity type MOS transistor having a drain connected to the source of the first second conductivity type MOS transistor and a source connected to a power supply voltage source, and a gate of the third third conductivity type MOS transistor. The drain of the second conductivity type MOS transistor is connected to the drain of the second conductivity type MOS transistor.
The source of the S-transistor and the third second conductivity type M
A fourth second conductivity type MOS transistor connected to the gate of the OS transistor and having a source connected to the power supply voltage source; a gate connected to the drain of the fourth second conductivity type MOS transistor; Third conductivity type MO
A CMOS level shift circuit comprising: a drain of an S transistor and a fifth second conductivity type MOS transistor connected to the output terminal and having a source connected to the power supply voltage source.