JPH05211242A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH05211242A JPH05211242A JP434792A JP434792A JPH05211242A JP H05211242 A JPH05211242 A JP H05211242A JP 434792 A JP434792 A JP 434792A JP 434792 A JP434792 A JP 434792A JP H05211242 A JPH05211242 A JP H05211242A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- insulating film
- interlayer insulating
- titanium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置およびその
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.
【0002】[0002]
【従来の技術】従来の半導体装置の製造方法は、まず、
図4(a)に示すように、P型(又はN型)のシリコン
基板1の一主面に、N型(又はP型)の拡散層2及び酸
化シリコン膜あるいは酸化シリコン膜にリンやホウ素が
添加されているPSG膜やBSPG膜より構成される厚
さ0.5〜1.0μmの層間絶縁膜3を形成する。2. Description of the Related Art A conventional semiconductor device manufacturing method is as follows.
As shown in FIG. 4A, an N-type (or P-type) diffusion layer 2 and a silicon oxide film or a silicon oxide film are formed on one main surface of a P-type (or N-type) silicon substrate 1 with phosphorus or boron. An interlayer insulating film 3 having a thickness of 0.5 to 1.0 μm and formed of a PSG film or a BSPG film to which is added is formed.
【0003】次に、所望の位置にバイアホール(図示せ
ず)を形成した後、バイアホールを含む表面にタングス
テンにチタンが5〜10%添加されたチタンタングステ
ン合金膜あるいはチタン膜と窒化チタン膜の2層より構
成される厚さ0.05〜0.2μmの第1の金属膜4及
び金、白金、パラジウム等より構成される厚さ0.01
〜0.1μmの第2の金属膜5を順次堆積して形成す
る。Next, after forming a via hole (not shown) at a desired position, a titanium tungsten alloy film or a titanium film and a titanium nitride film in which 5 to 10% of titanium is added to tungsten on the surface including the via hole. A first metal film 4 having a thickness of 0.05 to 0.2 μm and a thickness of 0.01 made of gold, platinum, palladium or the like.
A second metal film 5 having a thickness of .about.0.1 .mu.m is sequentially deposited and formed.
【0004】次に、図4(b)に示すように、フォトリ
ソグラフィー技術を用いてポジタイプのフォトレジスト
膜10を1.0〜2.0μmの厚さに第2の金属膜5の
上に選択的に形成し、フォトレジスト膜10をマスクと
して第2の金属膜5の上に電解金めっきを行い、金膜6
を0.5〜2.0μmの厚さに形成する。Next, as shown in FIG. 4B, a positive type photoresist film 10 having a thickness of 1.0 to 2.0 μm is selected on the second metal film 5 by using a photolithography technique. And then electrolytically gold-plating the second metal film 5 using the photoresist film 10 as a mask.
To a thickness of 0.5 to 2.0 μm.
【0005】次に、図4(c)に示すように、有機溶剤
を用いフォトレジスト膜10を除去し、続いてアルゴン
ガスをソースとするミリング法やCF4 ,SF6 をエッ
チングガスとした反応性イオンエッチング法により、金
膜6をエッチングマスクとして下層の第1の金属膜4お
よび第2の金属膜5の不要部分のみを除去して、第1の
金属膜4,第2の金属膜5,金膜6の積層構造により構
成される金属配線を形成する。Next, as shown in FIG. 4 (c), the photoresist film 10 is removed using an organic solvent, followed by a milling method using argon gas as a source or a reaction using CF 4 or SF 6 as an etching gas. The unnecessary portions of the lower first metal film 4 and the second metal film 5 are removed by a positive ion etching method using the gold film 6 as an etching mask, and the first metal film 4 and the second metal film 5 are removed. , A metal wiring composed of a laminated structure of the gold film 6 is formed.
【0006】次に、図4(d)に示すように、Si
H4 ,N2 O,NH4 ,N2 等を原料ガスとするプラズ
マCVD法により金膜6の上に酸化シリコン膜9又は窒
化シリコン膜を形成していた。Next, as shown in FIG.
The silicon oxide film 9 or the silicon nitride film is formed on the gold film 6 by the plasma CVD method using H 4 , N 2 O, NH 4 , N 2 etc. as the source gas.
【0007】[0007]
【発明が解決しようとする課題】上述した従来の半導体
装置は、配線を構成する金膜の上に設ける層間絶縁膜と
して酸化シリコン膜あるいは酸化シリコン膜を用いるの
が通例となっているが、金は化学的に安定な元素であり
酸化シリコン膜あるいは窒化シリコン膜との密着性に乏
しいため、層間絶縁膜の機械的な強度が得にくい。した
がって、高い長期信頼性と安定した特性を有する半導体
装置を得にくくなり、さらにその製造過程での高い歩留
は実現できない。In the conventional semiconductor device described above, it is customary to use a silicon oxide film or a silicon oxide film as an interlayer insulating film provided on the gold film forming the wiring. Is an element that is chemically stable and has poor adhesion to a silicon oxide film or a silicon nitride film, so that it is difficult to obtain mechanical strength of the interlayer insulating film. Therefore, it becomes difficult to obtain a semiconductor device having high long-term reliability and stable characteristics, and a high yield in the manufacturing process cannot be realized.
【0008】[0008]
【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に設けた絶縁膜の上に形成した金属配線
と、前記金属配線を含む表面に設けた金属酸化物膜もし
くは金属窒化物膜からなる第1の層間絶縁膜と、前記第
1の層間絶縁膜上に設けた酸化シリコン又は窒化シリコ
ン膜からなる第2の層間絶縁膜とを有する。The semiconductor device of the present invention comprises:
A metal wiring formed on an insulating film provided on a semiconductor substrate, a first interlayer insulating film made of a metal oxide film or a metal nitride film provided on the surface including the metal wiring, and the first interlayer A second interlayer insulating film made of a silicon oxide film or a silicon nitride film provided on the insulating film.
【0009】本発明の半導体装置の製造方法は、半導体
基板上に設けた絶縁膜の上に金属配線を選択的に設ける
工程と、前記金属配線を含む表面にアルミニウム膜又は
チタン膜を形成して酸化処理又は窒化処理を行い酸化ア
ルミニウム膜,酸化チタン膜又は窒化チタン膜のいずれ
かよりなる第1の層間絶縁膜を形成する工程と、前記第
1の層間絶縁膜の上に酸化シリコン膜又は窒化シリコン
膜からなる第2の層間絶縁膜を形成する工程とを含んで
構成される。A method of manufacturing a semiconductor device according to the present invention comprises a step of selectively providing a metal wiring on an insulating film provided on a semiconductor substrate, and an aluminum film or a titanium film formed on a surface including the metal wiring. A step of forming a first interlayer insulating film of an aluminum oxide film, a titanium oxide film or a titanium nitride film by performing an oxidation treatment or a nitriding treatment; and a silicon oxide film or a nitride film on the first interlayer insulating film. And a step of forming a second interlayer insulating film made of a silicon film.
【0010】[0010]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0011】図1(a)〜(c)及び図2(a)〜
(c)は本発明の第1の実施例を説明するための工程順
に示した半導体チップの断面図である。1 (a) to 1 (c) and 2 (a) to
(C) is sectional drawing of the semiconductor chip shown in order of process for demonstrating the 1st Example of this invention.
【0012】まず、図1(a)に示すように、P型(又
はN型)のシリコン基板1の一主面にN型(又はP型)
の拡散層2を選択的に設け、拡散層2を含むシリコン基
板1の上に酸化シリコン膜あるいは酸化シリコンにリン
やホウ素が添加されているPSG膜やBPSG膜より構
成される厚さ0.5〜1.0μmの層間絶縁膜3を形成
する。次に、所望の位置にバイアホール(図示せず)を
形成したのち、バイアホールを含む層間絶縁膜3の表面
に拡散層2と上層に形成される金属配線の間の原子拡散
の抑制による耐熱性の向上およびめっき時のめっき電流
供給を目的として、タングステンにチタンが5〜10%
添加されたチタンタングステン合金膜あるいはチタン膜
と窒化チタン膜の2層より構成される第1の金属膜4を
D.C.マグネトロンスパッタ法による成膜パワー1.
0〜5.0kW、成膜圧力2〜10mTorrの条件
で、0.05〜0.2μmの厚さに形成する。次に、第
1の金属膜4の上に、めっき法により金属配線を形成す
る際の第1の金属膜4の表面のめっき液からの保護、密
着性の改善、めっき電流の供給を目的として、金、白
金、パラジウム等より構成される第2の金属膜5を、
D.C.マグネトロンスパッタ法による成膜パワー0.
5〜1.0kW、成膜圧力2〜10mTorrの条件
で、0.01〜0.1μmの厚さに形成する。First, as shown in FIG. 1A, an N type (or P type) is formed on one main surface of a P type (or N type) silicon substrate 1.
And a PSG film or a BPSG film in which phosphorus or boron is added to silicon oxide is formed on the silicon substrate 1 including the diffusion layer 2. An interlayer insulating film 3 having a thickness of 1.0 μm is formed. Next, after forming a via hole (not shown) at a desired position, heat resistance is obtained by suppressing atomic diffusion between the diffusion layer 2 and the metal wiring formed in the upper layer on the surface of the interlayer insulating film 3 including the via hole. Titanium is added to tungsten in an amount of 5 to 10% for the purpose of improving the property and supplying the plating current during plating.
The first metal film 4 composed of the added titanium-tungsten alloy film or two layers of a titanium film and a titanium nitride film was used as a D.I. C. Deposition power by magnetron sputtering method 1.
It is formed to a thickness of 0.05 to 0.2 μm under the conditions of 0 to 5.0 kW and a film forming pressure of 2 to 10 mTorr. Next, for the purpose of protecting the surface of the first metal film 4 from the plating solution when forming metal wiring on the first metal film 4 by a plating method, improving adhesion, and supplying a plating current. A second metal film 5 made of gold, platinum, palladium, etc.,
D. C. Deposition power by magnetron sputtering method 0.
It is formed to a thickness of 0.01 to 0.1 μm under the conditions of 5 to 1.0 kW and a film forming pressure of 2 to 10 mTorr.
【0013】次に、図1(b)に示すように、第2の金
属膜5の上にフォトレジスト膜10を0.5〜2.0μ
mの厚さに塗布してパターニングし配線形成用マスクを
形成する。次に、フォトレジスト膜10をマスクとし、
第2の金属膜5を陰極とし、メッシュ状のチタン板の表
面部に白金を被覆した金属電極板を陽極として、30〜
60℃程度に恒温保持された例えば亜硫酸金塩溶液など
で構成される電解金めっき液中で陰陽両極間に電圧を印
加し、通電することにより、金膜6を第2の金属膜5の
上に0.5〜1.0μmの厚さに形成する。Next, as shown in FIG. 1B, a photoresist film 10 having a thickness of 0.5 to 2.0 μm is formed on the second metal film 5.
A coating mask having a thickness of m is formed and patterned to form a wiring forming mask. Next, using the photoresist film 10 as a mask,
The second metal film 5 is used as a cathode, and the metal electrode plate obtained by coating the surface of a mesh-shaped titanium plate with platinum is used as an anode.
A gold film 6 is formed on the second metal film 5 by applying a voltage between the positive and negative electrodes in an electrolytic gold plating solution composed of, for example, a gold sulfite solution which is kept at a constant temperature of about 60 ° C. To a thickness of 0.5 to 1.0 μm.
【0014】次に図1(c)に示すように、有機溶剤を
用いた剥離法あるいは酸素プラズマを用いたアッシング
法等によりフォトレジスト膜10を除去した後、金膜6
をマスクとしてSF6 ,CF4 ,CC14 ,BC13 等
をエッチングガスとするドライエッチングによりエッチ
バックし、第1の金属膜4および第2の金属膜5を除去
して、第1の金属膜4,第2の金属膜5及び金膜6より
構成される金属配線を形成する。Next, as shown in FIG. 1C, the photoresist film 10 is removed by a stripping method using an organic solvent or an ashing method using oxygen plasma, and then the gold film 6 is removed.
Is used as a mask to etch back by dry etching using SF 6 , CF 4 , CC1 4 , BC1 3, etc. as an etching gas to remove the first metal film 4 and the second metal film 5, thereby removing the first metal film. 4, a metal wiring composed of the second metal film 5 and the gold film 6 is formed.
【0015】次に、図2(a)に示すように、金属配線
を含む表面にアルミニウム膜7をD.C.マグネトロン
スパッタ法を用い成膜パワー0.5〜1.0kW、成膜
圧力2〜10mTorrの条件で0.01〜0.05μ
mの厚さに形成する。Next, as shown in FIG. 2A, an aluminum film 7 is formed on the surface including the metal wiring by D.P. C. Using a magnetron sputtering method, the film forming power is 0.5 to 1.0 kW, and the film forming pressure is 2 to 10 mTorr.
It is formed to a thickness of m.
【0016】次に、図2(b)に示すように、NH4 ,
N2 等を原料ガスとするプラズマ窒化法によるRFパワ
ー0.5〜1.0kW、成膜圧力0.1〜10Torr
の条件で、アルミニウム膜7にプラズマ窒化処理を施し
窒化アルミニウム膜8を形成する。Next, as shown in FIG. 2 (b), NH 4 ,
RF power by plasma nitriding method using N 2 or the like as a source gas 0.5 to 1.0 kW, film forming pressure 0.1 to 10 Torr
Under these conditions, the aluminum film 7 is plasma-nitrided to form the aluminum nitride film 8.
【0017】次に、図2(c)に示すように、Si
H4 ,N2 O,NH4 ,N2 等を原料ガスとするプラズ
マCVD法を用い、RFパワー0.5〜1.0kW、成
膜圧力0.1〜10Torrの条件で、窒化アルミニウ
ム膜8の上に酸化シリコン膜9を0.1〜0.5μmの
厚さに形成する。Next, as shown in FIG.
The aluminum nitride film 8 is formed under the conditions of RF power of 0.5 to 1.0 kW and film forming pressure of 0.1 to 10 Torr using a plasma CVD method using H 4 , N 2 O, NH 4 , N 2 etc. as a source gas. A silicon oxide film 9 is formed thereon to a thickness of 0.1 to 0.5 μm.
【0018】このようにして得られた配線構造は、配線
金属膜である金膜6と層間絶縁膜である酸化シリコン膜
9との間に窒化アルミニウム膜8が存在しており、両者
の密着性を向上させている。In the wiring structure thus obtained, the aluminum nitride film 8 is present between the gold film 6 which is the wiring metal film and the silicon oxide film 9 which is the interlayer insulating film, and the adhesion between the two is high. Is improving.
【0019】また、このような層間絶縁膜の形成方法に
おいては、アルミニウム膜7をスパッタ法により形成し
たのち窒化処理を施しているので、金膜6の金原子がス
パッタ法により形成されたアルミニウム原子と密着して
おり、窒化アルミニウム膜8を直接スパッタ法により形
成した場合にくらべてさらに密着性を向上させることが
可能となる。Further, in such a method of forming an interlayer insulating film, since the aluminum film 7 is formed by the sputtering method and then subjected to the nitriding treatment, the gold atoms of the gold film 6 are formed by the sputtering method. And the aluminum nitride film 8 can be further improved in adhesion as compared with the case where the aluminum nitride film 8 is directly formed by the sputtering method.
【0020】図3(a)〜(d)は本発明の第2の実施
例を説明するための工程順に示した半導体チップの断面
図である。FIGS. 3A to 3D are sectional views of the semiconductor chip in the order of steps for explaining the second embodiment of the present invention.
【0021】図3(a)に示すように、第1の実施例と
同様の工程によりP型シリコン基板1の一主面に、選択
的に設けたP型拡散層の上に層間絶縁膜3を設け、層間
絶縁膜3の上に第1の金属膜4および第2の金属膜5を
順次堆積する。次に、第2の金属膜5の上に設けたフォ
トレジスト膜をマスクとして第2の金属膜5の上に電解
めっきにより0.5〜1.0μmの厚さの銅膜11を選
択的に形成し、有機溶剤を用いた剥離法あるいは酸素プ
ラズマを用いたアッシング法等によりフォトレジスト膜
を除去した後、Arをミリングソースとしたイオンミリ
ンダ法やCF4,SF6 等をエッチングガスとするドラ
イエッチング法により銅膜11をマスクとして第1の金
属膜4および第2の金属膜5の不要部分を除去し、第1
の金属膜4,第2の金属膜5及び金膜6の積層構造によ
り構成される金属配線を形成する。As shown in FIG. 3A, the interlayer insulating film 3 is formed on the P type diffusion layer selectively provided on one main surface of the P type silicon substrate 1 by the same process as in the first embodiment. And the first metal film 4 and the second metal film 5 are sequentially deposited on the interlayer insulating film 3. Next, using the photoresist film provided on the second metal film 5 as a mask, a copper film 11 having a thickness of 0.5 to 1.0 μm is selectively formed on the second metal film 5 by electrolytic plating. After forming and removing the photoresist film by a peeling method using an organic solvent or an ashing method using oxygen plasma, an ion millinda method using Ar as a milling source or a dry method using CF 4 , SF 6 or the like as an etching gas is used. Unnecessary portions of the first metal film 4 and the second metal film 5 are removed by the etching method using the copper film 11 as a mask,
A metal wiring having a laminated structure of the metal film 4, the second metal film 5 and the gold film 6 is formed.
【0022】次に、図3(b)に示すように、金膜6を
含む表面にチタン膜12をD.C.マグネトロンスパッ
タ法を用い成膜パワー0.5〜1.0kW、成膜圧力2
〜10mTorrの条件で、0.01〜0.05μmの
厚さに形成する。Next, as shown in FIG. 3B, a titanium film 12 is formed on the surface including the gold film 6 by D.P. C. Film formation power of 0.5 to 1.0 kW and film formation pressure of 2 using the magnetron sputtering method
It is formed to a thickness of 0.01 to 0.05 μm under the condition of 10 mTorr.
【0023】次に、図3(c)に示すように、O2 を原
料ガスとするプラズマ酸化法を用い、RFパワー0.5
〜1.0kW、成膜圧力0.1〜10Torrの条件
で、チタン膜12にプラズマ酸化処理を施し酸化チタン
膜13を形成する。Next, as shown in FIG. 3C, RF power of 0.5 is used by the plasma oxidation method using O 2 as a source gas.
The titanium film 12 is subjected to plasma oxidation treatment under the conditions of .about.1.0 kW and film forming pressure of 0.1 to 10 Torr to form the titanium oxide film 13.
【0024】次に、図3(d)に示すように、酸化チタ
ン膜12の上にSiH4 ,N2 O,NH4 ,N2 等を原
料ガスとするプラズマCVD法を用いRFパワー0.5
〜1.0kW、成膜圧力0.1〜10Torrの条件
で、酸化シリコン膜9を0.1〜0.5μmの厚さに形
成する。Next, as shown in FIG. 3D, an RF power of 0.1 V is applied on the titanium oxide film 12 by a plasma CVD method using SiH 4 , N 2 O, NH 4 , N 2 etc. as a source gas. 5
The silicon oxide film 9 is formed to a thickness of 0.1 to 0.5 μm under the conditions of ˜1.0 kW and film forming pressure of 0.1 to 10 Torr.
【0025】このようにして得られた配線構造は、配線
金属膜である銅膜11と層間絶縁膜である酸化シリコン
膜9との間に酸化チタン膜13が存在しており、両者の
密着性を向上させている。In the wiring structure thus obtained, the titanium oxide film 13 exists between the copper film 11 which is a wiring metal film and the silicon oxide film 9 which is an interlayer insulating film, and the adhesion between the two is high. Is improving.
【0026】また、このような層間絶縁膜の形成方法に
おいては、チタン膜12をスパッタ法により形成したの
ち酸化処理を施しているので、めっき銅の銅原子がスパ
ッタ法により形成されたチタン原子と密着しており、酸
化チタン膜を直接スパッタ法により形成した場合にくら
べてさらに密着性を向上させることが可能となる。Further, in such a method for forming an interlayer insulating film, since the titanium film 12 is formed by the sputtering method and then subjected to the oxidation treatment, the copper atoms of the plated copper are different from the titanium atoms formed by the sputtering method. Since they are in close contact, the adhesion can be further improved as compared with the case where the titanium oxide film is directly formed by the sputtering method.
【0027】[0027]
【発明の効果】以上説明したように本発明は、配線金属
膜と層間絶縁膜の密着性を向上させることができるの
で、層間絶縁膜の安定した良好な電気特性や高い長期信
頼性を有する多層配線構造を形成できるという効果を有
する。As described above, according to the present invention, since the adhesion between the wiring metal film and the interlayer insulating film can be improved, the multilayer insulating film having stable and good electric characteristics and high long-term reliability can be obtained. It has an effect that a wiring structure can be formed.
【図1】本発明の第1の実施例を説明するための工程順
に示した半導体チップの断面図。1A to 1C are cross-sectional views of a semiconductor chip showing the order of steps for explaining a first embodiment of the present invention.
【図2】本発明の第1の実施例を説明するための工程順
に示した半導体チップの断面図。FIG. 2 is a sectional view of a semiconductor chip showing the order of steps for explaining the first embodiment of the present invention.
【図3】本発明の第2の実施例を説明するための工程順
に示した半導体チップの断面図。FIG. 3 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a second embodiment of the present invention.
【図4】従来の半導体装置の製造方法を説明するための
工程順に示した半導体チップの断面図。FIG. 4 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.
1 シリコン基板 2 拡散層 3 層間絶縁膜 4 第1の金属膜 5 第2の金属膜 6 金膜 7 アルミニウム膜 8 窒化アルミニウム膜 9 酸化シリコン膜 10 フォトレジスト膜 11 銅膜 12 チタン膜 13 酸化チタン膜 1 Silicon Substrate 2 Diffusion Layer 3 Interlayer Insulation Film 4 First Metal Film 5 Second Metal Film 6 Gold Film 7 Aluminum Film 8 Aluminum Nitride Film 9 Silicon Oxide Film 10 Photoresist Film 11 Copper Film 12 Titanium Film 13 Titanium Oxide Film
Claims (4)
した金属配線と、前記金属配線を含む表面に設けた金属
酸化物膜もしくは金属窒化物膜からなる第1の層間絶縁
膜と、前記第1の層間絶縁膜上に設けた酸化シリコン又
は窒化シリコン膜からなる第2の層間絶縁膜とを有する
ことを特徴とする半導体装置。1. A metal wiring formed on an insulating film provided on a semiconductor substrate, and a first interlayer insulating film made of a metal oxide film or a metal nitride film provided on a surface including the metal wiring, A second interlayer insulating film made of a silicon oxide film or a silicon nitride film provided on the first interlayer insulating film, and a semiconductor device.
複数の導電層からなる請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the metal wiring comprises a plurality of conductive layers containing at least a gold film or a copper film.
酸化チタン膜又は窒化アルミニウム膜のいずれかである
請求項1又は請求項2記載の半導体装置。3. The first interlayer insulating film is aluminum oxide,
The semiconductor device according to claim 1 or 2, which is either a titanium oxide film or an aluminum nitride film.
配線を選択的に設ける工程と、前記金属配線を含む表面
にアルミニウム膜又はチタン膜を形成して酸化処理又は
窒化処理を行い酸化アルミニウム膜,酸化チタン膜又は
窒化チタン膜のいずれかよりなる第1の層間絶縁膜を形
成する工程と、前記第1の層間絶縁膜の上に酸化シリコ
ン膜又は窒化シリコン膜からなる第2の層間絶縁膜を形
成する工程とを含むことを特徴とする半導体装置の製造
方法。4. A step of selectively providing a metal wiring on an insulating film provided on a semiconductor substrate, and an oxidation treatment or a nitriding treatment to form an aluminum film or a titanium film on a surface including the metal wiring and to perform oxidation. A step of forming a first interlayer insulating film made of an aluminum film, a titanium oxide film or a titanium nitride film, and a second interlayer made of a silicon oxide film or a silicon nitride film on the first interlayer insulating film. And a step of forming an insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP434792A JPH05211242A (en) | 1992-01-14 | 1992-01-14 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP434792A JPH05211242A (en) | 1992-01-14 | 1992-01-14 | Semiconductor device and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05211242A true JPH05211242A (en) | 1993-08-20 |
Family
ID=11581896
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP434792A Withdrawn JPH05211242A (en) | 1992-01-14 | 1992-01-14 | Semiconductor device and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05211242A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013111533A1 (en) * | 2012-01-23 | 2013-08-01 | シャープ株式会社 | Thin film transistor substrate manufacturing method, and thin film transistor substrate manufactured by same |
JP2016103646A (en) * | 2015-12-14 | 2016-06-02 | 富士通株式会社 | Semiconductor device and method of manufacturing semiconductor device |
US9379229B2 (en) | 2011-02-24 | 2016-06-28 | Fujitsu Limited | Semiconductor apparatus including protective film on gate electrode and method for manufacturing the semiconductor apparatus |
-
1992
- 1992-01-14 JP JP434792A patent/JPH05211242A/en not_active Withdrawn
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9379229B2 (en) | 2011-02-24 | 2016-06-28 | Fujitsu Limited | Semiconductor apparatus including protective film on gate electrode and method for manufacturing the semiconductor apparatus |
US9685547B2 (en) | 2011-02-24 | 2017-06-20 | Fujitsu Limited | Semiconductor apparatus including barrier film provided between electrode and protection film |
WO2013111533A1 (en) * | 2012-01-23 | 2013-08-01 | シャープ株式会社 | Thin film transistor substrate manufacturing method, and thin film transistor substrate manufactured by same |
US9209282B2 (en) | 2012-01-23 | 2015-12-08 | Sharp Kabushiki Kaisha | Method of manufacturing thin film transistor substrate and thin film transistor substrate manufactured by the method |
JP2016103646A (en) * | 2015-12-14 | 2016-06-02 | 富士通株式会社 | Semiconductor device and method of manufacturing semiconductor device |
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