JPH0519293A - Thin film field effect transistor element array - Google Patents

Abstract

PURPOSE:To apply a driving voltage to a liquid crystal so as to be symmetrical vertically and to prevent the deterioration of a picture quality such as a flicker, etc., caused by non-symmetricalness of a driving waveform by providing a shield electrode on the intersecting part of a gate bus line and a drain bus line, and connecting the shield electrode to an electrode whose potential is constant such as a common electrode, etc. CONSTITUTION:On a transparency insulating substrate, plural, parallel gate bus lines 1, and plural parallel drain bus lines 2 are formed like a matrix, and in picture element parts surrounded and formed by the gate bus line 1 and the drain bus line 2, a thin film field effect transistor is formed, respectively. To these thin film field effect transistors, a picture element electrode 3 is connected, respectively, and in a transistor element array in which a storage capacity electrode 5 is connected to a common bus line 4, a shield electrode 6 is inserted into an intersecting part of the gate bus line 1 and the drain bus line 2, and this shield electrode 6 is connected to the common bus line 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film field effect transistor element array for use in an active matrix type liquid crystal display.

[0002]

2. Description of the Related Art FIG. 5 is a plan view showing one pixel of a conventional thin film field effect transistor element array, and FIG.
It is an A'sectional view. FIG. 7 is an equivalent circuit diagram for one pixel in FIG. 5, in which the capacitance at the intersection of the bus lines is taken into consideration. FIG. 8 shows voltage waveforms input to the gate bus line, drain bus line, and common bus line, and FIGS. 9 and 10 show the gate electrode and the gate electrode when signals of the Nth frame and the N + 1th frame of FIG. 8 are input, respectively. It is a figure which shows the signal waveform in a drain electrode. In FIG. 5, reference numerals 1, 2 and 4 denote a chrome gate bus line, a chrome drain bus line and a chrome common bus line of the thin film field effect transistor element array, respectively. These are formed on the glass substrate 10. Reference numerals 28a, 28b and 28c respectively denote a chromium source electrode, a chromium gate electrode and a chromium drain electrode of the thin film field effect transistor element, and these and the channel portion 29 of amorphous silicon form the thin film field effect transistor element 14. As shown in FIG. 6, the intersection of the chromium gate bus line 1 and the chromium drain bus line 2 is insulated via the first insulating film 8. As a result, a capacitance C _CRS as shown in FIG. 7 occurs at the intersection of the gate bus line and the drain bus line.

[0003]

When a coupling capacitance such as C _CRS in FIG. 7 occurs between the bus lines, the gate and drain signals influence each other via C _CRS .

When a signal as shown in FIG. 8 is input to each bus line, the waveform of each electrode at this time is as shown in FIGS. 9 and 10.
As shown in. FIG. 9 shows an electrode waveform in the case of the Nth frame in FIG. At this time, the gate electrode signal 20 is C
_It is affected by the drain signal 26 via the _CRS and exhibits steep rising and falling characteristics. Further, the drain electrode signal 21 is also influenced by the gate electrode signal 20 and exhibits a steep rise and fall characteristic, and phenomena such as overshoot and increase in field through voltage appear in the waveform.

FIG. 10 shows an electrode waveform in the (N + 1) th frame of FIG. In this case, the gate electrode signal 20 is affected by the drain signal 26 and has a blunt rising and falling waveform. At this time, under the influence of the gate signal 25, the drain electrode signal 22 also has a blunt waveform.

According to the present invention, the asymmetry of the applied voltage to the liquid crystal caused by the coupling capacitance C _{CRS at} the intersection of the gate bus line and the drain bus line is maintained without changing the conventional input signal and without lowering the aperture ratio. It is an object of the present invention to provide a thin film field effect transistor device array having a reduced number.

[0007]

Means for Solving the Problems A plurality of parallel gate bus lines and a plurality of parallel drain bus lines are formed in a matrix on a transparent insulating substrate, and the gate bus lines and the drain bus lines are formed. The thin film field effect transistors are formed in the pixel portions formed in the past, the pixel electrodes are connected to the thin film field effect transistors, and the storage capacitor electrodes are connected to the common bus line. In the thin film field effect transistor element array, a shield electrode is inserted at the intersection of the gate bus line and the drain bus line,
The structure is characterized in that the shield electrode is connected to the common bus line.

[0008]

According to the thin film field effect transistor element array of the present invention, a shield electrode is provided at the intersection of the gate bus line and the drain bus line, and the shield electrode is connected to an electrode having a constant potential such as a common electrode. Since the fluctuation of the signal waveform caused by the coupling capacitance between the bus lines is eliminated, the rising and falling waveforms of the drain signal are vertically symmetrical. For this reason, the driving voltage applied to the liquid crystal becomes vertically symmetrical, so that the deterioration of the image quality such as flicker due to the asymmetry of the liquid crystal driving waveform does not occur.

[0009]

1 is a plan view showing the structure of a thin film field effect transistor element array having a structure according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA 'in FIG. FIG. 3 is an equivalent circuit diagram for one pixel in FIG. 1, in which the capacitance at the intersection of the bus lines is taken into consideration. FIG. 4 is a signal waveform diagram at each electrode.

In FIG. 1, 1 is a chromium gate bus line using chromium as a metal, and 2 is a chromium drain bus line. Reference numeral 3 is a pixel electrode using ITO.
4 is a chrome common bus line formed at the same time as the chrome gate bus line, and 5 is an I formed on the storage capacitance line.
It is a storage capacitor electrode using TO. 28a, 28b, 2
8c is a chromium source electrode, a chromium gate electrode, and a chromium drain electrode of the thin film field effect transistor,
These and the channel portion 29 form a thin film field effect transistor. Reference numeral 6 is a shield electrode using chromium as a metal, and 7 is a contact hole for connecting the shield electrode and the storage capacitance line. In FIG. 2, 8 is a first insulating film using silicon oxide (SiO ₂ ), and 9 is a second insulating film using silicon nitride (SiN _x ). Reference numeral 10 is a glass substrate, and 11 is a surface protective film.

FIG. 3 shows an equivalent circuit for one pixel in FIG.
7 is different from FIG. 7 in that the coupling capacitance formed between the bus lines is divided into C _CRS1 and C _CRS2 , the middle point of which is the common electrode 1.
It is connected to the common bus line 4 via 9. As a result, the potential on the common electrode side is fixed to the common potential even if there is a coupling capacitance between the bus lines,
It does not affect other signals via the coupling capacitance.
Therefore, as shown in FIG. 4, the gate signal is the Nth frame,
The gate electrode signal waveforms 20 are the same in the (N + 1) th frame and the waveforms of the drain electrode signals 21 and 22 are not deformed due to the influence of the gate signals, so that vertically symmetrical waveforms are obtained.

When a thin film field effect transistor element array was actually manufactured with the structure as shown in FIG. 1, the interference due to the coupling capacitance at the intersection of the bus lines of the gate and the drain was negligible. As a result, since the influence of the fluctuation of the gate signal due to the drain signal is eliminated, the voltage applied to the liquid crystal becomes a vertically symmetrical alternating current, and the factors that deteriorate the image quality such as flicker are reduced, and high quality display can be obtained.

In this embodiment, ITO is used for the pixel electrode and the storage capacitor electrode, but In ₂ O ₃ and SnO ₂ are used.
Can also be used. Further, as the gate insulating film, SiO ₂ may be used instead of SiN _x . Further, it is possible to use other metals such as Ta, Al, Mo, and Ti instead of chromium for the gate bus line, the drain bus line and the storage capacitor electrode.

[0014]

As described above, according to the thin film field effect transistor element array of the present invention, it is possible to reduce the interference between the gate signal and the drain signal due to the capacitance at the intersection of the bus lines. When a panel was manufactured using this structure, it was possible to suppress the vertical asymmetry of the drain signal waveform due to the mutual influence of the bus lines while maintaining the same aperture ratio as the conventional panel by using the same signal as the conventional one. It was possible to realize a display without deterioration of image quality such as flicker as a result.

[Brief description of drawings]

FIG. 1 is a plan view of one pixel of a thin film field effect transistor element array of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ in FIG.

FIG. 3 is an equivalent circuit diagram of one pixel of the present invention.

FIG. 4 is a signal waveform diagram of each electrode according to the present invention.

FIG. 5 is a plan view of one pixel of a conventional thin film field effect transistor element array.

6 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 7 is a conventional equivalent circuit diagram for one pixel.

FIG. 8 is a waveform diagram of an input signal to each bus line.

FIG. 9 is a signal waveform diagram of a conventional N-th frame electrode.

FIG. 10 is a signal waveform diagram of electrodes of the (N + 1) th frame.

[Explanation of symbols]

 1 Chrome Gate Bus Line 2 Chrome Drain Bus Line 3 Pixel Electrode 4 Chrome Common Bus Line 5 Storage Capacitance ITO Electrode 6 Shield Electrode 7 Contact Hole 8 First Insulating Film 9 Second Insulating Film 10 Glass Substrate 11 Surface Protecting Film 14 Thin Film Field effect transistor element (TFT) 19 Common electrode 20 Gate electrode signal 21 Nth frame drain electrode signal 22 N + 1 frame drain electrode signal 25 Gate signal 26 Drain signal 28a Chrome source electrode 28b Chrome gate electrode 28c Chrome drain electrode 29 Channel part

Claims (1)

Claim: What is claimed is: 1. A plurality of parallel gate bus lines and a plurality of parallel drain bus lines are formed orthogonal to each other on a translucent insulating substrate, and the intersections are formed in a matrix. A thin film field effect transistor is formed in each pixel portion surrounded by the gate bus line and the drain bus line, and a pixel electrode is connected to each thin film field effect transistor, and a storage capacitor electrode is formed. Is a thin film field effect transistor element array connected to a common bus line, a shield electrode is inserted at an intersection of the gate bus line and the drain bus line, and the shield electrode is connected to the common bus line. Thin film field-effect transistor element array of structure.