JPH05167932A - Solid state image pickup device - Google Patents

Abstract

PURPOSE:To surely output an image pickup signal having high field frequency appropriate for industrial or image processing. CONSTITUTION:Respective image information data read out from a two-line simultaneous reading type CCD image sensor 1 through respective horizontal transfer registers are written in the 1st and 2nd field memories 5A, 5B, read out twice the writing speed and then alternately outputted through a demultiplexer 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to photoelectric conversion of light information on a pixel-by-pixel basis, and a plurality of pieces of pixel information obtained by the photoelectric conversion are accumulated and output for a predetermined period of time. The present invention relates to a solid-state imaging device using a 2-line simultaneous readout type solid-state image sensor that reads out every 1 field, and more particularly to a solid-state imaging device that outputs an imaging signal having a field frequency twice the field frequency of a standard television system. ..

[0002]

2. Description of the Related Art CCD (Charge Coupled)
A solid-state image sensor such as a device (charge-coupled device) image sensor has excellent features such as no image sticking or afterimage, high impact resistance, and easy miniaturization of a camera, compared with an imaging tube. There is. Generally, in a video camera conforming to a standard television system such as the NTSC system in which interlaced scanning is adopted, an image pickup signal from each pixel of an odd field image and an image pickup signal from each pixel of an even field image are recorded for one field period ( CC that is read alternately every 1/60 seconds in the NTSC system
A D image sensor is used. In addition, a two-line simultaneous readout type in which a horizontal transfer register for two lines is provided so that the image pickup signal from each pixel of the odd field image and the image pickup signal from each pixel of the even field image are all read out within one field period The so-called "Progress"
ing Scan CCD (hereinafter simply referred to as P.S.CCD
Image sensors are provided for high resolution video cameras.

[0003]

By the way, the conventional NT
A video camera conforming to a standard television system such as the SC system has a field frequency of 60 fields / second, that is, a field frequency of 60 Hz. High speed processing is required when inspecting an object. Since the solid-state image sensor such as the CCD image sensor is a capacitive load, the load doubles when the driving frequency doubles. Therefore, if the field frequency is increased in order to perform high-speed processing, there is a risk that the drive circuit will lack capacity, and it will be necessary to review the entire drive system. In particular, P.3 for high resolution video cameras. S. In the CCD, since it is difficult to read all the image pickup signals from all pixels with one horizontal transfer register within one field period, two horizontal transfer registers are provided, so that the speed is doubled. It is extremely difficult to drive with.

In view of the problems in the solid-state image pickup device using the conventional solid-state image sensor as described above, the present invention can reliably output an image pickup signal having a high field frequency, which is optimum for industrial use or image processing. The present invention provides a solid-state imaging device capable of performing

[0005]

In order to solve the above-mentioned problems, a solid-state image pickup device according to the present invention photoelectrically converts optical information in pixel units, and outputs a plurality of pixel information obtained by the photoelectric conversion for a predetermined time. A two-line simultaneous read-out type solid-state image sensor in which image information of all pixels is read out for each field from two photoelectric transfer units that accumulate and output over the entire range, and one of the solid-state image sensor is used. A first memory for storing at least one line of imaging information read out via a horizontal transfer register, and a second memory for storing at least one line of image information read out from the image sensor via the other horizontal transfer register. And information switching means for alternately switching and outputting each image information read from the first and second memories, and the solid-state image Image information read simultaneously from two lines from the image sensor is written in the first and second memories, read at a read speed twice as fast as the write speed, and the image information is alternately output via the information switching means. It has a control means for controlling.

[0006]

In the solid-state image pickup device according to the present invention, each image information read from the two-line simultaneous read-out type solid-state image sensor through each horizontal transfer register is written in the first and second memories, and the writing speed is doubled. The image information is read at the reading speed of 1 and the image information is alternately output via the information switching means.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a solid-state image pickup device according to the present invention will be described in detail below with reference to the drawings. The solid-state imaging device according to the present invention is configured, for example, as shown in the block diagram of FIG.

The solid-state image pickup device shown in FIG. 1 includes a CCD image sensor 1 of a two-line simultaneous read-out type, and this CCD.
The image pickup signals read simultaneously from two lines from the image sensor 1 are respectively correlated double sampling circuits 2A and 2B.
Via the process processing circuits 3A and 3B, and the image pickup signals processed by these process processing circuits 3A and 3B are A / D converters 4A and 4A, respectively.
Each field memory 5A, 5B supplied via B,
A demultiplexer 6 to which the image pickup signals read from the field memories 5A and 5B are supplied, an encoder 8 to which the image pickup signals output from the demultiplexer 6 are supplied via a D / A converter 7, Encoder 8
An output buffer 9 for outputting a video signal obtained as an encoded output from the output terminal 10, a CCD drive circuit 11 for driving the CCD image sensor 1, and a CC for this CC.
The D drive circuit 11 and the like are provided with a control unit 12 that gives various clock signals and the like to control the operation.

In the CCD image sensor 1, as shown in FIG. 2, photosensitive elements SO and SE such as photodiodes corresponding to respective pixels of an odd field image and an even field image are arranged in a matrix on the image pickup surface. The image pickup section IM and the photosensitive elements SO of the image pickup section IM,
A so-called frame interline transfer (FIT) type CCD image sensor having an accumulating portion ST in which accumulated charges obtained by SE are transferred through a vertical transfer register, and is obtained by each of the photosensitive elements SO and SE. The accumulated charges thus read are simultaneously read out from the accumulating section ST for two lines via two horizontal transfer registers HO _REG and HE _REG to image the accumulated charges of all pixels, that is, one frame (2 fields) for each field. A two-line simultaneous read-out type P.I. S.
A CCD image sensor is used.

This CCD image sensor 1 has the above-mentioned CC
It is driven by the D drive circuit 11 as follows.

That is, the accumulated charges transferred to the storage section ST are first transferred from the vertical transfer registers VO _REG and VE _REG to the first horizontal transfer register HO _REG .
At that time, as shown in A of FIG. 3, the charges of the odd vertical transfer register VO _REG are _{equal to those} of the first horizontal transfer register HO _REG.
To of an H ₁ phase, also the charge of the even vertical transfer register VO _REG enters into H ₂ phase of the first horizontal transfer register HO _REG. Here, “O ₁ ”, “O ₂ ” ... In the figure indicate the charges transferred from the odd vertical transfer register VO _REG , and “E ₁ ”, “E ₂ ” ... , The even-numbered vertical transfer register VE _REG is shown.

The first horizontal transfer register HO
_{The REG} and the second horizontal transfer register HO _REG operate in the H ₁ and H ₂ phases with the same drive pulses φH ₁ and φH ₂ . When the drive pulses φH ₁ and φH ₂ are both “H”, H ₁ and H ₂
Charges are accumulated in the phases. Further, the transfer gate between the first horizontal transfer register HO _REG and the second horizontal transfer register HO _REG has a drive pulse φHHG.
Has been opened because it is "H".

Then, by changing the driving pulse φH ₂ from "H" to "L" in this state, the charge "E ₁ " from the even vertical transfer register VO _REG , as shown in FIG. 3B, “E ₂ ” ... Is transferred from the φH ₂ phase of the first horizontal transfer register HO _REG to the H ₁ phase of the second horizontal transfer register HE _REG via φHHG. As a result, the first horizontal transfer register HO _REG
H ₁ phase of the odd vertical transfer register VO _REG charge "O
₁ ”,“ O ₂ ”, etc., and the charges“ E ₁ ”,“ E ₂ ”, ... Of the even vertical transfer register VO _REG are _{added to} the H ₁ phase of the second horizontal transfer register HE _REG. Goes in.

Next, by setting the drive pulse φHHG to "L", the transfer gate is closed to close the first horizontal transfer register HO _REG and the second horizontal transfer register H.
By prohibiting the transfer to and from E _REG , changing the drive pulse φH ₁ from “H” to “L” and changing the drive pulse φH ₂ from “L” to “H” in this state, As shown in C of FIG. 3, each horizontal transfer register HO
The charges in _REG , HE _REG , are transferred from the H ₁ phase to the H ₂ phase.

Then, the drive pulse φHHG is set to "L".
Then, while the transfer gate is opened, the drive pulse φH ₁ is changed from “L” to “H”, and the drive pulse φH ₂ is changed from “H” to “L”. As shown in D, the charges “O ₂ ”, “O ₃ ” ... Of the H ₂ phase of the first horizontal transfer register HO _REG are transferred to the H ₁ phase of the second horizontal transfer register HE _REG. Together with H _{2 of the second} horizontal transfer register HE _REG
The phase charges “E ₂ ”, “E ₃ ” ... Are transferred to the H ₁ phase. As a result, the first horizontal transfer register HO _REG
There is no electric charge in the second horizontal transfer register HE _REG and all the electric charges are transferred to the second horizontal transfer register HE _REG , and the odd vertical transfer register VO _{REG is added to} the H ₁ phase of the second horizontal transfer register HE _REG.
, "O ₁ ", "O ₂ " ... And the charges "E ₁ ", "E ₂ " ... Of the even vertical transfer register VO _REG are added. By the above operation, the imaging charge for one scanning line is transferred to the second horizontal transfer register HE _REG .

Further, the drive pulse φHHG is set to "L".
Then, with the transfer gate opened, both the drive pulses φH ₁ and φH ₂ are set to “H”, the charge is transferred from the vertical transfer registers VO _REG and VE _REG , and as shown in E of FIG. the odd charges of the vertical transfer register VO _REG to H ₁ phase of the first horizontal transfer register HO _REG, also the even vertical transfer register VO _REG H ₂ phases of the first horizontal transfer register HO _REG charge of Put in.

Then, the drive pulse φH ₁ is kept at “H”, and the drive pulse φH ₂ is changed from “H” to “L”, so that the first horizontal transfer register as shown in F of FIG. HO _REG H ₂ phase charge “O ₂ ”, “O ₃ ” ・
... the transfer to H ₁ phase. Thus, the charge "O _1" of the first horizontal transfer register HO _REG of an H ₁ phase to the odd vertical transfer register VO _REG, "O _2", ... and the charge of the even vertical transfer register VO _REG "E ₁ , "E ₂ " ...
・ You will enter with added. In addition, the second
In the horizontal transfer register HE _REG , the idle transfer is performed from the H ₂ phase to the H ₁ phase without any change.

As a result of the above operation, the image-capturing charges for one scanning line enter the respective horizontal transfer registers HO _REG and HE _REG .

Then, by changing the drive pulse φH ₁ from “H” to “L” and changing the drive pulse φH ₂ from “L” to “H”, the H ₁ phase is changed to H.
Transfer to the _2- phase, then again drive pulse φH ₁ to "L"
H from as well as to the "H" by changing the driving pulse .phi.H ₂ from "H" to "L", the H ₂ phase
Two lines are simultaneously read by repeating the operation of transferring to _one phase. The CCD image sensor 1
As shown in G of FIG. 3, the respective image pickup signals read out simultaneously from two lines from the second horizontal transfer register HE _REG
The image pickup signal read via the first horizontal transfer register HO _REG is 1 than the image pickup signal read via the first horizontal transfer register HO _REG.
It's a pixel behind.

The image pickup signals read out simultaneously from the CCD image sensor 1 for two lines are subjected to noise reduction processing by the correlated double sampling circuits 2A and 2B, respectively, and then supplied to the process processing circuits 3A and 3B. ..
The process processing circuits 3A and 3B perform process processing such as gamma correction, clamp, and white clip necessary for a video camera on each image pickup signal supplied via the correlated double sampling circuits 2A and 2B.

Here, the second horizontal transfer register HE
The correlated double sampling circuit 2B and the process processing circuit 3 to which the image pickup signal read out via the _REG is supplied.
A delay circuit 13 is provided between B and B. The delay circuit 13 gives a delay amount corresponding to one pixel pitch to the image pickup signal read via the second horizontal transfer register HE _REG . Thereby, the process processing circuit 3
The image pickup signals read out from the CCD image sensor 1 for two lines at the same time are supplied to A and 3B in a state where the phases thereof match.

Then, each of the process processing circuits 3A, 3
Each image pickup signal processed by B is sampled by the A / D converters 4A and 4B at a sampling frequency f _SP corresponding to one pixel pitch and digitized to be the first and second field memories. 5
It is supplied to A and 5B.

The above first and second field memories 5
In A and 5B, the image pickup signals digitized by the A / D converters 4A and 4B are sampled at the sampling frequency f.
Writing is performed with a write clock having a clock rate equal to _SP , and as shown in FIG. 4, image pickup signals for all pixels are written for each one-field scan of the CCD image sensor 1. Then, these field memories 5A, 5B
The respective image pickup signals written in 1) are read out by a read clock having a clock rate twice as high as the write clock during the next 1-field scanning period. That is, the image pickup signals for all pixels written for each one-field scan of the CCD image sensor 1 are read out from the first and second field memories 5A and 5B at a read speed twice as fast as the write speed. .. Here, the first and second field memories 5A and 5B are controlled by a read enable signal supplied from the controller 12,
One of the read operations is performed only in the first half of the one-field scanning period, and the other read operation is performed only in the second half of the one-field scanning period.

Then, these field memories 5A,
Each double-speed image pickup signal read from 5B is supplied to the D / A converter 7 via the demultiplexer 6.

The demultiplexer 6 includes the controller 1
Under the control of the control signal supplied from the No. 2, the image pickup signal read from the first field memory 5A is selected in the first half of the one field scanning period, and the second field memory 5B is selected in the second half of the one field scanning period. By selecting the image pickup signal read from, the 1-channel image pickup signal is formed as shown in FIG. That is, the 2-channel image pickup signal read out for each field scanning of the CCD image sensor 1 is converted into the double-speed 1-channel image pickup signal.

2 obtained by this demultiplexer 6
The double-speed image pickup signal is converted into an analog signal by the D / A converter 7 and then supplied to the encoder 8. The encoder 8 adds a blanking signal, a synchronizing signal, or the like to the analogized double-speed imaging signal to form a video in a desired format. The video signal obtained as an encoded output by the encoder 8 has a characteristic impedance of 7 from the output terminal 10 via the output buffer 9.
It is output to the 5Ω transmission line.

Further, the control section 12 for applying various clock signals to the CCD drive circuit 11 and the like to control the operation includes a synchronizing signal generator 14, a clock generator 15, a timing signal generator 16 and the like. ..

The synchronizing signal generator 14 supplies the vertical synchronizing signal VD and the horizontal synchronizing signal H to the timing signal generator 16.
In addition to supplying D, the encoder 8 is supplied with a blanking pulse BLK and a synchronization signal SYNC. The clock generator 15 applies a clock pulse having a frequency 2f _SP , which is twice the sampling frequency f _SP , to the D / A converter 7 and the timing signal generator 16.
And a read clock to the first and second field memories 5A and 5B. Further, the timing signal generator 16 forms various clock signals necessary for driving the CCD image sensor 1 on the basis of the vertical synchronizing signal VD, the horizontal synchronizing signal HD and the clock pulse to generate the CCD driving circuit 11.
Is being supplied to. In addition, the sampling frequency f _SP
The clock pulse is generated, and this clock pulse is supplied to the A / D converters 3A and 3B and is also supplied to the first and second field memories 5A and 5B as a write clock. Further, the image pickup signal read from the first field memory 5A is selected in the first half of the one field scanning period, and the image pickup signal read from the second field memory 5B is selected in the second half of the one field scanning period. A control signal for generating the control signal is generated, and this control signal is supplied to the demultiplexer 6.

In the solid-state image pickup device having such a structure, the image signals read from the 2-line simultaneous read-out type solid-state image sensor 1 through the horizontal transfer registers HO _REG and HE _REG are used as first and second field memories. 5A, 5
B can be written, read at a read speed twice as fast as the write speed, and output as a 1-channel video signal via the demultiplexer 6. This video signal is a double speed video signal formed from the image pickup signals for all pixels obtained by the solid-state image sensor 1 and is suitable for photographing a fast-moving subject with high dynamic resolution. Further, since it is not necessary to drive the solid-state image sensor 1 at high speed, it is possible to reliably perform the image pickup operation.

In the above embodiment, each image signal read from the two-line simultaneous read-out type solid-state image sensor 1 is written in the first and second field memories 5A and 5B, and each image signal is read from each field memory 5A and 5B. The video signal is read at high speed by dividing it into the first half and the second half of one field scanning period.
Instead of B, a line memory may be used.
In this case, each image signal read from the solid-state image sensor 1 for two lines simultaneously is written in each line memory,
By reading the first line scanning period in the first half and the latter half at high speed, the video signals for all pixels read out from the solid-state image sensor 1 in one field scanning period are read by one.
A so-called non-interlaced video signal used as a channel video signal can be obtained at double speed.

[0031]

As is apparent from the above description, in the solid-state image pickup device according to the present invention, each image information read from the two-line simultaneous readout type solid-state image sensor via each horizontal transfer register is used as the first and the first image information. By writing in two memories and reading out at a reading speed twice as fast as the writing speed, and alternately outputting each image information through the information switching means, a high field frequency suitable for industrial use or image processing is provided. The image pickup signal can be reliably obtained.

Therefore, according to the present invention, it is possible to provide a solid-state image pickup device having a high dynamic resolution and suitable for photographing a fast-moving subject.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a solid-state imaging device according to the present invention.

FIG. 2 is a schematic plan view showing a configuration of a 2-line simultaneous readout type CCD image sensor used in the solid-state imaging device.

FIG. 3 is a diagram showing a transfer state of image pickup charges by each horizontal transfer register in the CCD image sensor.

FIG. 4 is a timing chart showing the operation of the solid-state imaging device.

[Explanation of symbols]

1 --- CCD image sensor 4A, 4B --- A / D converter 5A, 5B --- field memory 6 --- Demultiplexer 7 ... D / A converter 8 ... Encoder 11 ... CCD drive circuit 12 ...・ ・ ・ Control unit SO, SE ・ ・ ・ Photosensitive element IM ・ ・ ・ ・ ・ Image pickup unit ST ・ ・ ・ ・ ・ Storage unit HO _REG , HE _REG ... Horizontal transfer registers

Claims (1)

[Claims] 1. Horizontal transfer of two pieces of image information of all pixels from a photoelectric conversion unit that photoelectrically converts optical information in pixel units and accumulates and outputs a plurality of pixel information obtained by the photoelectric conversion for a predetermined time. A two-line simultaneous read-out type solid-state image sensor which is read out for each field via a register, and a first memory which stores at least one line of imaging information read from the solid-state image sensor through one horizontal transfer register. A second memory for storing at least one line of image information read from the image sensor via the other horizontal transfer register, and the image information read from the first and second memories are alternately switched and output. Information switching means for controlling the image information and the image information read out from the solid-state image sensor for two lines at the same time. Write to memory,
Read at twice the read speed of that write speed,
A solid-state imaging device, comprising: a control unit that performs control to alternately output each image information via the information switching unit.