JPH05102305A - Automatic layout method of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make the length of wiring short by a method wherein, in addition to wiring layer which is used for wiring on lattices in the transverse and longitudinal directions in conventional cases, a wiring layer which is used for lattice-shaped wiring in the oblique direction is used. CONSTITUTION:In addition to lattices 1 in the transverse direction and lattices 1 in the longitudinal direction, lattices 3 in the rightward ascending oblique direction and lattices 4 in the rightward descending oblique direction are set, they are used as wiring layers which are used mainly for wiring on the respective lattices 1, 2, 3, 4, and a first inter-connection layer to a fourth wiring layer are allotted. Thereby, the length of the wiring can be shortened to 0.7 times at the most, and the wiring resistance and wiring capacitance are reduced. As a result, the operating speed of the title integrated circuit can be made fast.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout method for a semiconductor integrated circuit, and more particularly to an automatic layout method using an algorithm for wiring a predetermined grid on a predetermined wiring layer.

[0002]

2. Description of the Related Art A conventional automatic layout method of a semiconductor integrated circuit using an algorithm for wiring on a predetermined grid on a predetermined wiring layer is, for example, as shown in FIG. In addition, the second wiring layer is mainly used for the wiring on the grid 11 in the horizontal direction and the second wiring layer is mainly used for the wiring on the grid 12 in the vertical direction. Further, when three or more wiring layers are used, the third wiring layer is formed on the same grid 11 in the lateral direction as the first wiring layer and the fourth wiring layer.
On the same vertical grid 12 as the second wiring layer,
It was sequentially allocated and used like so.

FIG. 4 is a pattern diagram in which wiring is actually performed according to the grid of FIG. In FIG. 4, there is a first wiring layer 15 in the horizontal direction and a second wiring layer 16 in the vertical direction, and they are electrically connected by a connection pattern 17 of the wiring layers 15 and 16. These are wiring patterns for electrically connecting points A, B, C, D.

[0004]

In such a conventional automatic layout method for a semiconductor integrated circuit, even if three or more wiring layers are used, the grids 11 and 1 in the horizontal or vertical direction are formed.
Since the wiring is provided only on the upper side of the wiring 2, there is a problem that even if the number of wiring layers is increased, the wiring is easy and the length of the wiring is not so short.

An object of the present invention is to provide an automatic layout method for a semiconductor integrated circuit which solves the above problems and shortens the length of wiring.

[0006]

A structure of an automatic layout method for a semiconductor integrated circuit according to the present invention is provided with at least one wiring layer used for wiring on a horizontal grid and at least one wiring on a vertical grid. It is characterized by using a wiring layer used and at least one wiring layer used for wiring on a diagonal grid.

[0007]

FIG. 1 is a wiring grid diagram used in an embodiment of the present invention. In FIG. 1, in addition to the horizontal grid 1 and the vertical grid 2, a grid 3 in the upper right diagonal direction and a grid 4 in the lower right diagonal direction are set.
As the wiring layers mainly used for the wirings on 3 and 4,
Assign the wiring layer of.

FIG. 2 is a pattern diagram in which the wiring pattern is obtained by using the lattice diagram of FIG.

In FIG. 2, there are a first wiring layer 7, a second wiring layer 8, a third wiring layer 5 and a fourth wiring layer 6, and a connection pattern 9 between the wiring layers is used as a connection point or the like. It is provided.

FIG. 2 shows an example of wiring between the points A and B and between the points C and D. The wiring length is 0.7 to 0.8 times shorter than that in the conventional case of FIG. ing.

[0011]

As described above, according to the present invention, in addition to the conventional wiring layers used for wiring on the horizontal and vertical grids,
By using the wiring layer used for wiring on the diagonal grid, the length of the wiring can be shortened by up to 0.7 times, the wiring resistance and the wiring capacitance are reduced, and the operating speed is said to be high. Have an effect.

[Brief description of drawings]

FIG. 1 is a wiring grid diagram used in a semiconductor integrated circuit automatic layout method according to an embodiment of the present invention.

FIG. 2 is a wiring pattern diagram created along the grid of FIG.

FIG. 3 is a wiring grid diagram used in a conventional automatic layout method.

FIG. 4 is a wiring pattern diagram created along the grid of FIG.

[Explanation of symbols]

 1, 11 Horizontal grid 2, 22 Vertical grid 3 Right upward diagonal grid 4 Right downward diagonal grid 5, 6, 15, 16 Wiring pattern between two points

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7353-4M H01L 21/88 A

Claims (1)

[Claims] 1. A wiring layer used for wiring on at least one lateral grid, a wiring layer used for at least one wiring on a vertical grid, and a wiring used for at least one wiring on a diagonal grid. A method for automatically laying out a semiconductor integrated circuit characterized by using layers.