JPH0473334B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission method applicable to recording and reproducing digital audio signals.

For example, one field of a digital audio signal accompanying a video signal is a predetermined amount of data, so as shown in FIG.
It is considered as a unit of (m blocks), and error correction correction encoding processing is performed for each unit. Cross interleaving has been proposed as one method for making digital audio signals have a code structure that allows error correction.

Cross interleaving is a method of performing two types of interleaving, in which each symbol of a digital information signal is included in two error correction code sequences. In the following description, P and Q sequences, which are parity code sequences, are used as error correction code sequences. This cross-interleaving can be applied to the data in the arrangement shown in FIG.

Error correction coding is performed by this block-complete cross interleaving, and the data to which the P sequence and Q sequence are added is stored in the vertical direction, starting from the first block, as shown by the arrows in Figure 1. transmitted to. During this transmission, a synchronization signal, a block address signal, and a CRC code for error detection are added and recorded for each block.

The error correction encoding method using cross interleaving has a feature of high error correction ability because each word of the digital audio signal is included in two parity sequences. Furthermore, in this cross-interleaving error correction encoding method, the probability that error correction will be impossible differs depending on the position within one block.

For ease of explanation, consider the case of cross interleaving in which two words of parity are added to four words of digital data.The parity sequence can be expressed as shown in FIG. In FIG. 2, each black circle indicates one word of a code symbol, and attention is paid to S ₀ to _{S 5} with white circles added. Further, in FIG. 2, the five words in the vertical direction are one series of parity P, and the six words in the diagonal direction are the series of parity Q on the other side.

The transmission system is random, and the decoder performs P decoding using parity P and Q using parity Q.
When decoding and decoding are alternately repeated a plurality of times, let us consider how often errors in each of the symbols S ₀ to _{S 5} become impossible to correct. For example, if the symbol S ₀ contains this symbol S ₀ , i.e.
For the sake of explanation, for example, if the symbol located near the left of symbol S ₀ is S ₆ , the symbol located near the right of symbol S ₂ is S ₇ , and the symbol located near the right of symbol S ₁ is S ₈ , then a trapezoid is formed. The 4 constituent symbols S ₀ ,
If S ₆ , S ₇ and S ₈ become error words at the same time, each of the two parity sequences will contain two error words, and this error cannot be corrected. By counting such trapezoidal patterns, the probability that error correction becomes impossible can be determined. Also, the symbols S ₁ , S ₂ , S ₃ ,
Regarding S ₄ and S ₅ , for example, considering the symbol S ₂ , the four words that include this symbol and make up a parallelogram, that is, for example, the left neighbor symbol of the symbol S ₁ are S ₉ , and the symbol S 2 is the left neighbor of the symbol S ₂ . The neighboring symbol S ₁₀ and the right neighboring symbol of symbol S ₃ are
S ₁₁ , symbol S ₄ , the right neighboring symbol is S ₁₂ and the minimum parallelogram is constructed (S ₂ , S ₉ , S ₁₀ ,
S ₃ ), (S ₂ , S ₃ , S ₁₂ , S ₁₁ ), (S ₂ , S ₁₁ , S ₇ , S ₁ ),
When four words consisting of the combination (S ₂ , S ₁ , S ₆ , S ₉ ) are simultaneously erroneous, error correction becomes impossible. For example (symbol in data W ₀ to the right of S ₁ , S ₂ , S ₃ , symbol in data W ₁ to the right of S ₃ )
If these symbols occur simultaneously, there will be two symbol errors in any P sequence or Q sequence that includes these symbols, which cannot be corrected.

If the probability that one word makes an error is P _S , the probability that error correction will be impossible for each word S ₀ to S ₅ is as shown below.

P _{0 =} 10P _S ⁴ P ₁ = 10P _S ⁴ P ₂ = 13P _S ⁴ P ₂ = 14P _S 4 P ⁴ = 13P _S ⁴ P ₅ = 10P _S ^4Of course, more than 5 words are wrong at the same time, and error correction is impossible. In some cases, the probability (P _S ⁵ or less) is ignored. Furthermore, the same tendency exists not only in the case of 4 words but also in the case of n words and 2 parity.

As mentioned above, conventional error correction encoding methods do _not take into consideration that the probability _that errors cannot be corrected differs depending on _the data channel. Parity data was placed in . However, information data is more important than parity for error correction, so
It is desirable to place PCM data in a position where there is a low probability that error correction will become impossible.

When digitizing a stereo audio signal accompanying an NTSC video signal, the digital audio signal for one field when the sampling frequency is 2 _h ( _h is the horizontal frequency) is:
It will be 1050 words. In other words, one field is
It consists of 262.5 lines, so when sampling for 2 _hours , the left and right channels are (262.5 x 2 x 2
= 1050 words) digital audio signal is generated. 6 words of control data are added to these 1050 words (n = 8 words) (m
= 132 blocks) (n x m = 1056 words). FIG. 3 shows a configuration example in which P and Q parity sequences are added to this 1056 word data.

In FIG. 3, W ₁ to _{W 8} indicate information data series in the horizontal direction, and parity is determined by 8 words (x marks) included in the husband and wife of this information data series and having a distance of 14 blocks each. A series P is formed. Distance between these two words (D=14 blocks)
is the maximum possible value. In other words, since the cycle of block change is in units of 132 blocks, the distance between two words from the first block P parity position is 14 blocks each.
When the series is formed, the block position of W ₈ on the P series becomes 112 (=14×8), and the remaining distance is 20 (132
-112) has 14 or more blocks. Therefore,
From the position of the 132nd block of the P series in Fig. 3,
Even when the signal is looped back toward the first block, the transmission interval between the symbol in the folded data _W8 and the parity symbol in the parity P of this P sequence becomes 20, and the distance between the two symbols becomes smaller. , the problem of deterioration of burst error correction ability does not occur.

However, if a P sequence is formed by taking a distance of 15 blocks, the block position of W ₈ on the P sequence will be 120 (=15 x 8), and the remaining distance will be 12 (=132 - 120). ). Therefore, considering the case of folding as described above, if the distance between two words is 15 blocks, there will be one where the distance between two words is 15 blocks and one where the distance is 12 blocks. For words 12 blocks apart, the ability to correct burst errors will be reduced. On the other hand, if the distance is set by 14 blocks, the distance between two words will never be less than 14 for all words. In this way, the distance D is maximized for all words, and the ability to correct burst errors can be enhanced.

Further, the other parity series Q is included in each of the information data series W ₁ to W ₈ and the parity series P,
It is formed by 9 words (indicated by *) with a distance of 11 blocks. In this example, when considering the distance between each word forming this parity sequence Q, that is, a certain word sequence,
The distance between the words targeted for generating parity from this series is smaller than in the case of the parity series P described above.

In the data structure shown in FIG. 3, two parity series P and Q are located at the ends of one block. However, as mentioned above, there is a low probability that error correction will be impossible at the position of the end of one block, and therefore it is not desirable to place a parity sequence with redundant data at this position. .

Therefore, if the two parity sequences P and Q are placed in the center of one block, the data structure will be as shown in FIG. 4. As is clear from FIG. 4, since one parity series P does not include the data included in the other parity series Q, the difference between two words included in each of data series _W4 and parity series P is Therefore, the distance D between two words cannot be set to 14 blocks.

That is, if parity sequences P and Q are simply placed at the center of one block, there will be a distance between two words of 28 blocks. By the way, in this example, since the distance D between two words is set to the maximum value in units of 132 blocks, that is, D = 14 blocks, there are cases where the distance between the two words is 28 blocks. D=13 blocks, and the error correction ability is degraded.

In consideration of the above points, this invention arranges redundant symbols for error correction in the vicinity of the center position of one block while maintaining the maximum distance between two words of one error correction code series. This is what I did.

As described above, (n=8, m=132)
A sequence applied to the case of is shown in FIG.

One parity series P is formed by 9 words located at equal intervals of 14 blocks. Further, when forming the parity sequence Q, nine words extracted from each of the information data sequences W ₁ to W ₈ and the parity sequence P are used. The parity of this result is the information data series as shown in Figure 5.
For the block number of the symbol included in W ₄
It is placed at the position of the block number plus 66 blocks. That is, when considering the block position, if symbol W ₄ is located at the position of, for example, 33 (=11×3) blocks, then the block position of parity series Q is 11 blocks away from symbol W ₈₉₉ . (=11×9) Place it at the block position. Therefore, based on the block position of symbol W ₄ , the block position of parity series Q is 66
(=99−33). The parity sequence Q returns to a position 11 blocks away from symbol _W4 , that is, 44 blocks. Therefore, the block number of the symbol included in the parity series P is obtained by subtracting 55 blocks from this parity block number. That is, it is assumed that the row in which Q parity is arranged is deleted so that each word constituting the parity matrix Q is arranged linearly. In this case, if each of the words W ₅ , ..., W ₈ in the latter half of the parity sequence Q is carried forward by one line, the parity generated based on this parity sequence Q will be the block number of W ₄ . against
By being placed 66 blocks apart.
Furthermore, if each word W ₁ , ..., W ₄ in the first half of the parity series Q is moved down by one line and each word is arranged in a straight line, the generated parity will be the block number of W _4. In contrast, it is placed -44 points away.

In such a parity series Q, the distance between two words included in each of the information data series W ₄ and the parity series P is 11 blocks, and the distance between the words included in the information data series W ₈ and the words of the parity series Q is 11 blocks. The distance between them is also 11 blocks. Therefore, in the parity sequence Q, the distance between each word is equal, 11 blocks.

Furthermore, as shown by the broken line in FIG. 5, the words of the parity series Q may be arranged at positions obtained by subtracting 44 from the block number of the words included in the information data series _W4 . That is, in the previous example, regarding the block position, the parity sequence Q was set to be located next to symbol _W8 , but
In this example, symbol _W1 is positioned next to the parity series. Therefore, if the block position of symbol _W4 is used as a reference, the parity sequence word will be placed at a block position subtracted by 44 (=11×-4). The distance between the word of parity series Q and the word of parity series P is 55 blocks.

In the above explanation, the distance D between two words of the parity sequence P is 14 blocks. As a result, 20
There are extra blocks, but by using them, we can create six locations where the distance between two words is 15 blocks, as shown in FIG. Furthermore, the distance between two words of the parity series Q is 12 blocks.

Then, as shown in FIG. 6, the data series W ₄
The data of the parity series Q is allocated to the block number that is obtained by adding 72 blocks to the block number containing one word. In this way, the distance between each two words of the parity sequence Q becomes equal, 12 blocks.

Also, as shown by the broken line in Fig. 6, from the block number of the word included in the data series _W4 ,
The data of the parity series Q may be allocated to the block number with 48 subtracted. In this example as well, the position of parity Q can be found in the same manner as in the case of FIG. That is, delete the row where Q parity is placed and write each word W ₅ ,...
W ₈ are each carried forward by one line, or W ₁ ,...
If each W ₄ is moved down by one row so that the parity sequence Q becomes linear, the parity positions generated will be separated by 70 or -48 from the block number of the word in W ₄ .

FIG. 7 shows the configuration of an embodiment in which the present invention is applied to the case of recording digital audio signals on a magnetic tape.

In FIG. 7, a recording audio signal is supplied to an input terminal indicated by 1, and is digitized by an A/D converter 2. In FIG. The solid arrows in FIG. 7 indicate the direction of the signal during recording, and the broken arrows indicate the direction of the signal during reproduction.

A digital audio signal from A/D converter 2 is written into RAM3 or RAM4. Each of RAM3 and RAM4 can store one field's worth of digital audio signals, and while input data is being written to one RAM, the data of the previous field is being written to the other RAM.
is read from the P,Q encoder/decoder 6 to form two parities, which are written to the other RAM. This RAM3
An address generation circuit 5 is provided to write predetermined data into the respective memory areas of the RAM 4 and to read it out in an interleaved manner.
This address generation circuit 5 includes an address counter,
A predetermined block address is generated by the ROM and adder.

Further, the digital audio signal and parity data read from the RAM 3 or RAM 4 are supplied to an adder 7, to which a block address from a block address generator 8 is added. The output of the adder 7 is then serialized by a parallel-to-serial converter 9 and supplied to a CRC encoder/decoder 10.

The CRC encoder/decoder 10 has, for example, (X ¹⁶ +X ¹² +X ⁵ +1) as a generating polynomial, and generates a 16-bit CRC code and adds it to each block. The operation of this CRC encoder/decoder 10 is controlled by a CRC timing generator 11. In this example, since the FM modulation method is used, the output of the CRC encoder/decoder 10 is supplied to the FM encoder/decoder 12.

Furthermore, the adder 13 adds a block synchronization signal from the synchronization signal generator 14 to the output terminal 15.
It is taken out. The digital signal taken out to this output terminal 15 is recorded on a magnetic tape by a rotating head.

Further, a digital signal reproduced from the magnetic tape is supplied to the input terminal 16, and the synchronization detection circuit 17
The signal is supplied to the FM encoder/decoder 12 via the FM encoder/decoder 12, where it is FM demodulated. This FM demodulated playback data is supplied to the CRC encoder/decoder 10, where each block is checked for errors using a CRC code, and the result is taken out as a 1-bit error pointer. This error pointer is stored in pointer RAMs 18 and 19. These pointer RAMs 18 and 19 correspond to RAMs 3 and 4, and their (10×132=1320 blocks)
An error pointer is written to each address. In other words, from address generation circuit 5, RAM 3 and 4
The common block address is pointer RAM18.
and 19.

Furthermore, the reproduced data is supplied to the RAMs 3 and 4 via the buffer 20 and the serial/parallel converter 21. This buffer 20 delays the reproduced data until an error pointer is formed as a result of the CRC check.

RAM3 and RAM4 operate in the same way as during recording, so that in a field in which playback data is written to one of them, errors in playback data read from the other are corrected. this
When writing reproduced data to RAM3 or RAM4, the error word indicated by the error pointer is prevented from being written. Therefore, the error point read from the pointer RAM 18 or 19 is supplied to the timing generator 22, which generates a control signal for the RAM 3 or 4.

The reproduced data read from the RAM 3 or 4 is supplied to the P, Q encoder/decoder 6, error correction is performed using parity, and the error-corrected data is written to the RAM 3 or 4 again. During this error correction, the error word only needs information that this is an error, and therefore, as described above, the error word itself
Writing to RAM3 or RAM4 is not performed.
Furthermore, if one parity generation sequence contains two or more error words, error correction cannot be performed, but error correction using a parity P sequence and error correction using a parity Q sequence may be performed repeatedly and alternately. This reduces the number of words for which error correction is impossible.

The error-corrected reproduced data read from the RAM 3 and RAM 4 is supplied to the correction circuit 23, and words whose errors cannot be corrected are subjected to average value interpolation processing. Then, the output of this correction circuit 23 is converted into an analog signal by a D/A converter 24, and a reproduced audio signal is taken out at an output terminal 25. In addition, corresponding to the 2-channel signal, A/
A D converter 2 and a D/A converter 24 are provided.

As can be understood from the above description, according to the present invention, even if the redundant symbol of the error correction code series is arranged at approximately the center position of each block, the arrangement of the redundant symbol makes it possible to The distance between two words never becomes smaller. However, since the digital information signal that should originally be transmitted is placed in a block position where there is a low probability that error correction will not be possible, the error correction ability can be further improved.

Note that an adjacent code or a Reed-Solomon code can be used as the error correction code, and different codes can also be combined. In the case of these codes, two or more redundant codes are used.

[Brief explanation of the drawing]

Figures 1 and 2 are schematic diagrams used to explain error correction encoding using cross interleaving;
4 and 4 are schematic diagrams used to explain error correction encoding using block-contained cross interleaving, FIG. 5 is a schematic diagram used to explain the data structure in an embodiment of the present invention, and FIG. The figure is a schematic diagram used to explain the data structure in another embodiment of the invention, and FIG. 7 is a block diagram showing the structure of an error correction encoder and an error correction decoder to which the invention is applied. 1... Audio signal input terminal, 3, 4...
RAM, 6...P, Q encoder/decoder, 1
0...CRC encoder/decoder, 15...Output terminal for recording signal, 16...Input terminal for playback signal, 18, 19...Pointer RAM, 23...Correction circuit, 25...Output terminal for playback audio signal.

Claims (1)

[Claims] 1. A predetermined number of digital information signals to be transmitted is n
A data transmission method in which a two-dimensional array of rows and m columns is formed, and interleaving for error correction encoding is completed in the two-dimensional array, and the data transmission method is performed at predetermined intervals in the column direction of the two-dimensional array. The first symbol consists of n symbols selected in different rows.
A first redundant symbol is generated from a sequence subjected to error correction encoding, and the n symbols and the first redundant symbol are selected at predetermined intervals different from the column direction predetermined intervals and in different rows. A second redundant symbol is generated from a sequence subjected to second error correction encoding consisting of the first and second
A redundant symbol is arranged at a substantially central row position of the two-dimensional array, and a second redundant symbol is arranged at a column position constituting one end of the series subjected to the second error correction encoding, 1. A data transmission method, characterized in that data transmission is performed sequentially together with digital information signals to be transmitted.