JPH0423048A - Error detection/correction integrated circuit, error detection/correction circuit, and data processor - Google Patents

Abstract

PURPOSE:To shorten the time needed for decision of data by attaining the error detecting/correcting operation only with the a single exchange of the partial syndrome generated between the error detection/correction LSIs. CONSTITUTION:A data LSI 3-1 generates a partial syndrome from the input data and the check bit of an error detecting/correcting circuit (ECC) through a partial syndrome editing circuit 4-1. This generated syndrome is outputted to the total syndrome editing circuits 6-1 and 6-2 of its own and another one. An LSI 3-2 also has the same operation. Then both circuits 6-1 and 6-2 generate the same syndromes from those partial syndromes collected by both LSIs. Then the decoders 7-1 and 7-2 decodes the syndromes generated by both circuits 6-1 and 6-2, and the correctable errors are corrected by a correction circuit 8-1 and 8-2. The partial syndromes of the read data controlled by both LSI 3-1 and 3-2 are exchanged between them. Then both LSIs correct each charging data bit and finish the transfer of partial syndromes only in a single operation. As a result, the high speed working is ensured for the ECC.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data error detection/correction (herein referred to as rECCJ) circuit used in a data processing device such as an electronic computer.

[Conventional technology]

The restorer part of the conventional ECC circuit using linear codes is as follows:
For example, 5 Nikkei Electronics November 26, 1979
As stated on page 106 of the issue, generally,
It consists of a syndrome generating section from read data, a syndrome decoding section for error detection and pointing out the error position, an error bit correction section, etc.

As an FCC using these linear codes, B CF (
1 using CRC such as CRC and expanded 11an+ming code
Hamming codes such as bit correction and 2-bit detection (SEC/DEC codes) are widely used in the fields of communications and information processing.

Generally, in FCC using linear codes, when the parity check matrix is 11 and the code word is V and its transposed matrix is V.

Error detection and correction are performed using syndrome S defined by S = T4-V.

Therefore, when these ECC circuits are integrated using an LSI or the like, all code words must be input into one LSI if one LST is to be used.

However, especially when the processing data width for performing FCC is large, due to constraints such as the number of LSI pins/simultaneous switching pins, etc.
It is difficult to input all code words. Also, L.S.
There are also restrictions such as the number of bins that can be switched simultaneously.

Therefore, conventionally, a plurality of LSIs (referred to as "r data LS r") are used to input a part of a code word and generate a partial syndrome as an intermediate result of syndrome calculation calculation. One LSI that calculates syndromes from partial syndromes from multiple LSIs (rECC-LSIJ
), it was common to configure an ECC circuit.

In this case, the FCC-LSI decodes the syndrome to detect errors, and sends the error correction signal to each data LS.
In response to this, each data LSI corrects errors in the data input to itself.

[Problem to be solved by the invention]

As described above, according to the conventional ECC circuit, each data L
The SI supplies data information such as a partial syndrorum signal to the FCC-LSI, generates a syndrorum in the FCC-LSI, decodes the syndrorum, and outputs the syndrorum to the FCC-LSI.
Since error correction is realized by supplying an error correction signal from I to the data LSI, when a correctable error occurs.

Signals had to be exchanged between the LSIs twice before correction was made, and corrected data could not be obtained until after this.

Further, even if no error generally occurs, the determination will take the same amount of time as in Section L to determine the data.

However, in general, signals are exchanged between LSIs.

The amount of delay is large because there is a hairline between the input/output gates (particularly large output gates) and the LSI, which have a larger gate delay than the internal gates of the LSI.

Therefore, exchanging signals twice between LSIs means
In contrast to the delay of the ECC circuit itself due to the internal gates of the LSI, the delay due to the exchange of signals between LSIs becomes noticeable.
This delays the finalization of data, which poses a problem in that it impedes speeding up of data processing, such as an increase in read access speed to a storage device in an electronic computer.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an ECC circuit that can shorten the time required to finalize data.

[Means to solve the problem]

To achieve the above object, the present invention receives input from the outside. 5. A partial syndrome generating means for generating a partial syndrome which is an intermediate result of the syndrome calculation calculation of the code word from a part of the code word; a means for outputting the generated partial syndrome to the outside; 5. The generated partial syndrome; , a syndrome generating means for generating a syndrome of a code word from a partial syndrome corresponding to a code word part other than the part of the code word; and a syndrome generating means for decoding the generated syndrome and error correction registration of the part of the input code word. An integrated circuit for detecting and correcting errors such as an LSI is provided.

In addition, in this integrated circuit for error detection and correction.

The partial syndrome generating means generates a partial syndrome according to an instruction of a responsible portion of a code word inputted from the outside, and the error correction means performs the error correction.

In response to the instruction, the generated syndrome may be decoded and the error correction of the specified portion of the input code word may be performed.

Furthermore, in order to achieve the above object, the present invention is characterized by comprising a plurality of the error detection/correction integrated circuits each responsible for each part of a divided code word that exchanges generated partial syndromes with each other. The present invention provides an error detection/correction circuit for detecting and correcting errors.

In addition, the present invention also provides a memory for storing information as a code word together with inspection information of the information, a processing device that utilizes the information stored in the memory, and error detection and correction of the code word read from the memory. The present invention also provides a data processing device characterized by comprising the error detection/correction circuit described above.

[For production]

The error detection/° correction integrated circuit according to the present invention inputs only a part of the code word from the outside according to the limitation of the number of pins, and
Partial error correction of the input code word is performed using the partial syndrome generated by itself and the partial syndrome input from the outside.

Therefore, according to the error detection/correction circuit according to the present invention,
Error detection and correction can be realized by mutually exchanging generated partial syndromes only once between the plurality of error detection/correction integrated circuits responsible for each part of a divided code word. In one integrated circuit for error detection and correction, the partial syndrome generation means generates a partial syndrome according to an instruction of a responsible portion of a code word inputted from the outside, and the means/means for performing error correction is provided.

If the generated syndrome is decoded and inputted in accordance with the instruction, and the error correction is performed for the designated portion of the code word, an error detection/correction circuit can be realized with one type of integrated circuit. be able to.

〔Example〕

An embodiment of the ECC circuit according to the present invention will be described below.

In this example, for convenience of explanation, 1-bit correction and 2-bit correction are used.
This will be explained by taking 8-byte-ECC that supports bit detection as an example. Further, a case will be taken as an example in which an LSI is used as an integrated circuit used in an ECC circuit.

FIG. 1 shows the configuration of a data processing device using an ECC circuit according to this embodiment.

In the illustrated ECC circuit, the encoder section that generates ECC check pits is omitted, and only the restorer section that performs error detection and correction is shown.

In the figure, 1 is a memory section, 3-1 and 3-2 are memory sections 1
The data LS performs data error detection and correction.
1.2 is a processing device that uses data after error correction.

The data LSIs 3-1 and 3-2 constitute an ECC circuit, including a syndroram editing port ij&4-1 or 4-2, a parity generation circuit 5-1 or 5-2, and an overall syndroram editing circuit 6-1 or 6-. 2. Syndrome decoder 7-1 or 7-2, error bit correction circuit 8-
1 or 8-2, respectively.

The operation will be explained below.

The ECC circuit consisting of data LSIs 3-1 and 3-2 transfers 8-byte data (code word) including ECC check pits (8 bits) read from memory section 1 to data LSIs 3-1 and 3-2.
3, performs error detection and correction, adds a parity check bit to each byte, and sends it to the processing device 2.

Data LSI 3-1 is in charge of byte O-3 and ECC check bit O-3, and data LSI 3-2 is in charge of byte 4-7 and ECC check pit 4-7.

Data LSI 3-1 input data and ECC
Partial Syndrome Edit Circuit 4-1 from Check Pit
A partial syndroram is generated, and the partial syndroram is connected to the entire syndroram knitting circuit 6-1 in the own LSI and other LSIs.
It is output to the SI overall syndrome editing circuit 6-2.

Further, the same operation is performed for the data LSI 3-2.

In response to this, the entire syndrome circuit 1 circuits 6-1 and 6-2 generate the same syndrome I from the seven partial syndromes collected in both data LSIs.

The syndrome decoders 7-1 and 7-2 decode the syndrome μ, and if there is a correctable error in the data bits handled by their own LSI, the data is sent to the error bit correction circuit t18-1 or IJ8-2. Correct it with.

In addition, in this embodiment, in parallel with error detection and correction, the parity generation circuit 5
-1 or 5-2 to generate byte parity. Therefore, if data errors are corrected,
The error bit correction circuit 8-1 or 8-2 also corrects byte parity.

Note that the syndroram decoder 7-1 or 7-2 reports error detection to the processing device 2, etc., as necessary.

As described above, according to this embodiment, the partial syndrome of read data handled by the data LSI is transferred to each data LSI.
The entire syndroram editing circuit by exchanging between 6
-1.6-2 and Syndroram decoder 7-1.7~
2 can be installed for each data LSI, and each data LSI corrects the data bit in charge of the LSI.
You can complete the exchanges in between in one go.

It is possible to increase the speed of the ECC circuit.

By the way, the ByteO-3 side where the data is divided into two and the ByteO-3 side
On the te4-7 side, the circuits for partial syndroram generation, syntroram decoding, etc. are different, but the data LSI is configured to include these different circuits and divides the data supplied from the input pin of the LSI or the register within the LSI. By using identification information, etc., the circuit can be switched depending on the purpose.

One type of data LSI in charge of each byte, SI
It may also be configured as follows.

Note that the ECC circuit according to this embodiment has different widths of Read-Data, number of correction bits,
The same can be achieved for the FCC of the number of detection bits. Further, in this embodiment, the number of data LSIs is two, but the necessary number should be provided depending on the number of bytes to be subject to FCC.

As described above, according to this embodiment, signals can be exchanged only once between LSIs, and the ECC circuit can be made high-speed.

Furthermore, the FCC-LS I in the conventional ECC circuit
It also has the effect of reducing

〔Effect of the invention〕

As described in 1- above, according to the present invention, it is possible to provide an ECC circuit that can shorten the time until data is finalized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an ECC circuit according to an embodiment of the present invention. 1...Memory unit, 2...Processing device, 3...Data I
, S.I. 4.Partial syndroram editing circuit (PSG), 5.Parity generation circuit (PG), 6..General syndroram editing circuit (SG), 7..Syndroram decoder (DEC)
), 8...Error bit correction circuit (Co). Applicant Hitachi Manufacturing Co., Ltd. Representative Patent Attorney Tomi 1) Kazuko

Claims (1)

[Claims] 1. Partial syndrome generation means for generating a partial syndrome that is an intermediate result of syndrome calculation of a code word from a part of the code word inputted from the outside, and outputting the generated partial syndrome to the outside. a syndrome generating means for generating a syndrome of a code word from the generated partial syndrome and a partial syndrome inputted from the outside and corresponding to a code word part other than the part of the code word; and a syndrome generating means for decoding the generated syndrome. , means for correcting errors in part of the input code word. 2. An error detection/correction circuit comprising a plurality of error detection/correction integrated circuits according to claim 1, which mutually exchange generated partial syndromes and are in charge of respective parts of divided code words. 3. A memory for storing information as a code word together with check information of the information, a processing device for utilizing the information stored in the memory, and detecting and correcting errors in the code word read from the memory. A data processing device comprising an error detection/correction circuit. 4. The partial syndrome generating means generates a partial syndrome in accordance with an instruction of the responsible part of the code word inputted from the outside, and the partial syndrome generating means decodes the generated syndrome according to the instruction and inputs the generated syndrome. 2. The error detection/correction integrated circuit according to claim 1, further comprising means for performing said error correction in a portion in charge of said error correction.