JPH0410635A - Flip chip package mounting - Google Patents
Flip chip package mountingInfo
- Publication number
- JPH0410635A JPH0410635A JP2113447A JP11344790A JPH0410635A JP H0410635 A JPH0410635 A JP H0410635A JP 2113447 A JP2113447 A JP 2113447A JP 11344790 A JP11344790 A JP 11344790A JP H0410635 A JPH0410635 A JP H0410635A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- board
- solder
- bump
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 abstract description 20
- 125000006850 spacer group Chemical group 0.000 abstract description 14
- 238000004382 potting Methods 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 abstract 3
- 238000010276 construction Methods 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明はＩＣチップ等を基板に実装する方法に関する。[Detailed description of the invention] <Industrial application field> The present invention relates to a method for mounting an IC chip or the like on a substrate.
〈従来の技術〉
ＩＣチップ等を基板に実装する技術として、ワイヤボン
ディング法やＴ Ａ Ｂ （Ｔａｐｅ Ａｕｔｏｍａｔ
ｅｄ Ｂｏ−１ｄｉｎｇ）法、あるいはフリップチップ
実装法等がある。これらの技術のうち、フリップチップ
実装法は、実装に要するスペースがチッ、プ自体の大き
さ程度でよいことから、高密度の実装に適している。<Conventional technology> Wire bonding method and TAB (Tape Automat
ed Bo-Iding) method, flip-chip mounting method, etc. Among these techniques, the flip-chip mounting method is suitable for high-density mounting because the space required for mounting is approximately the size of the chip itself.
フリップチップ実装法は、ＩＣチップ等の表面に形成さ
れたパッド上に、バンプ状（通常、半球状）の導電材、
例えばはんだバンプを形成し、チップを実装基板上に位
置合わせした状態で、はんだをリフローすることによっ
て、その基板の導体部にチップを直接接続する方法であ
る。なお、このフリップチップ実装法においては、接続
に用いる、はんだバンプ等を基板側に形成する場合もあ
る。In the flip chip mounting method, a bump-shaped (usually hemispherical) conductive material,
For example, this method involves forming solder bumps, aligning the chip on a mounting board, and then reflowing the solder to directly connect the chip to the conductor portion of the board. Note that in this flip-chip mounting method, solder bumps and the like used for connection may be formed on the substrate side.
〈発明が解決しようとする課題〉
ところで、従来のフリップチップ実装法によれば、バン
プ形状が不均一であったり、実装時にチップが傾いたり
すること、また、チップの熱膨張によりバンプ部に熱応
力が作用してバンプ部にりラックが生じる、等の原因に
より、接続不良が起こり易く、接続の信顧性に欠けると
いった問題が残されていた。<Problems to be Solved by the Invention> However, according to the conventional flip-chip mounting method, the shape of the bumps may be uneven, the chip may be tilted during mounting, and heat may be generated in the bump portion due to thermal expansion of the chip. The problem remains that poor connections tend to occur due to stress acting on the bumps and racks, etc., resulting in poor connection reliability.
〈課題を解決するための手段〉
本発明は、上記問題点を解決すべくなされたもので、そ
の実装方法を実施例に対応する第１図を参照しつつ説明
すると、本発明は、バンプ状導電材（はんだバンプ）３
・・・３に相応する位置に貫通孔４ａ・・・４ａが穿た
れた絶縁板４を、（Ｃ）に示すように、回路チップ１と
実装基板２との間に挟み込んだ状態で、バンプ状導電材
３・・・３のリフローを行うことを特徴としている。<Means for Solving the Problems> The present invention has been made to solve the above-mentioned problems, and the implementation method thereof will be explained with reference to FIG. 1 corresponding to the embodiment. Conductive material (solder bump) 3
. . . With the insulating plate 4 having through-holes 4 a bored at positions corresponding to 3 sandwiched between the circuit chip 1 and the mounting board 2 as shown in (C), bump It is characterized by performing reflow of the shaped conductive materials 3...3.
〈作用〉
バンプ状導電材３・・・３のリフローによって回路チッ
プ１を基板２の導体部２ａに直接接続するわけであるが
、そのリフロー時に、回路チップ１と基板２との間に絶
縁板４を存在させることによって、回路チップ１の基板
２に対する距離が一様となり、回路チップ１が傾くこと
を防止できる。しかも、リフロー後の導電材３・・・３
は絶縁板４によって固定されるので、そのバンプ部に熱
応力等が作用しても、バンプ部にクランクが発生する等
の確率は少なくなる。<Function> The circuit chip 1 is directly connected to the conductor portion 2a of the board 2 by reflowing the bump-shaped conductive material 3...3, but during the reflow, an insulating plate is inserted between the circuit chip 1 and the board 2. 4, the distance between the circuit chip 1 and the substrate 2 becomes uniform, and it is possible to prevent the circuit chip 1 from tilting. Moreover, the conductive material 3...3 after reflow
Since it is fixed by the insulating plate 4, even if thermal stress or the like is applied to the bump portion, the probability that a crank will occur in the bump portion is reduced.
〈実施例〉 本発明実施例を、以下、図面に基づいて説明する。<Example> Embodiments of the present invention will be described below based on the drawings.
第１図は本発明のフリップチップ実装方法の手順を説明
する。FIG. 1 explains the procedure of the flip-chip mounting method of the present invention.
まず、第１図（ａ）に示すように、公知の方法により、
ＩＣチップ１表面のパッド１ａ・・・１ａ上に、はんだ
バンプ３・・・３を形成しておき、また基板２の表面上
に、パッシベーション膜（図示せず）を形成し、導体パ
ターン２ａ・・・２ａのランド部が露呈するようにパッ
シベーション膜の窓明けを行っておく。さらに、絶縁性
のスペーサ４を後述する方法で作成しておく。このスペ
ーサ４には、ＩＣチップ１と基板２との接続部、つまり
はんだバンプ３・・・３に相応する位置に貫通孔４ａ・
・・４ａが穿たれている。First, as shown in FIG. 1(a), by a known method,
Solder bumps 3...3 are formed on the pads 1a...1a on the surface of the IC chip 1, and a passivation film (not shown) is formed on the surface of the substrate 2. ...Open a window in the passivation film so that the land portion of 2a is exposed. Furthermore, an insulating spacer 4 is created by a method described later. This spacer 4 has through holes 4a and 4a at positions corresponding to the connection parts between the IC chip 1 and the substrate 2, that is, the solder bumps 3...3.
...4a is drilled.
さて、（ロ）に示すように、基板２上にスペーサ４を、
その各貫通孔４ａが接続部に位置するように載置し、さ
らにそのスペーサ４上にＩＣチップ１を、その各はんだ
バンプ３がそれぞれ対応する貫通孔４ａに位置するよう
に載置する（Ｃ）。Now, as shown in (b), spacers 4 are placed on the substrate 2,
The IC chip 1 is placed on the spacer 4 so that each through hole 4a is located at the connection part, and the IC chip 1 is placed on the spacer 4 so that each solder bump 3 is located in the corresponding through hole 4a (C ).
次いで、はんだバンプ３・・・３のリフローを行う。Next, the solder bumps 3...3 are reflowed.
このリフローにより、はんだは貫通孔４ａの下方へと流
出し、基板２表面上の導体パターン２ａ・・・２ａに濡
れる（ｄ）。この状態で、はんだを硬化させることによ
って、ＩＣチップ１が基板２に電気的に接続される同時
に固定される。そして、ＩＣチップ１の周辺に樹脂５を
ポツティングすることにより、（ｅ）に示すような実装
構造を得る。As a result of this reflow, the solder flows out below the through hole 4a and wets the conductor patterns 2a...2a on the surface of the substrate 2 (d). By curing the solder in this state, the IC chip 1 is electrically connected to the substrate 2 and fixed at the same time. Then, by potting resin 5 around the IC chip 1, a mounting structure as shown in (e) is obtained.
以上のような手順により、ＩＣチップ１に形成したはん
だバンプ３・・・３の形状が不均一であっても、リフロ
ー時には、ＩＣチップ１はスペーサ４によって基板２に
対して平行に保持されるので、実装時にＩＣチップ１が
傾くことを防止できる。Through the above procedure, even if the shapes of the solder bumps 3...3 formed on the IC chip 1 are uneven, the IC chip 1 is held parallel to the substrate 2 by the spacers 4 during reflow. Therefore, it is possible to prevent the IC chip 1 from tilting during mounting.
しかも、リフロー・硬化後のはんだバンプ３の側面部は
スペーサ４に密着するので、バンプ部にリフロー時のＩ
Ｃチップ１の熱膨張等による熱応力が作用しても、その
バンプ部は保持され、バンプ部にクラック等が発生する
ことを防止することができる。Moreover, since the side surfaces of the solder bumps 3 after reflow and hardening are in close contact with the spacers 4, the bumps are exposed to the I/O during reflow.
Even if thermal stress is applied due to thermal expansion of the C-chip 1, the bump portion is maintained, and cracks or the like can be prevented from occurring in the bump portion.
次に、スペーサ４の製造手順を説明する。第２図はその
手順を説明する図である。Next, the manufacturing procedure of the spacer 4 will be explained. FIG. 2 is a diagram explaining the procedure.
まず、（ａ）に示すように、Ｓｉ基板４１の表面に低圧
ＣＶＤ法等により、酸化膜あるいは窒化膜等の絶縁膜４
２を形成した後、フォトリソグラフィ法により、絶縁膜
４２の窓明けを行って、バンプ接続部に相応する部分の
Ｓｉ基板４２を露呈させる（口）。次いで絶縁膜４２を
マスクとしてＳｉ基板４１のエツチングを行ってその部
分を開孔する（Ｃ）。First, as shown in (a), an insulating film 4 such as an oxide film or a nitride film is formed on the surface of a Si substrate 41 by low-pressure CVD or the like.
2, a window is opened in the insulating film 42 by photolithography to expose a portion of the Si substrate 42 corresponding to the bump connection portion (opening). Next, using the insulating film 42 as a mask, the Si substrate 41 is etched to open a hole in that portion (C).
このとき、Ｓｉ基板４１のエツチング面を（１００）面
とし、かつ、アルカリ溶液でエツチングを行えば、その
エツチング面は四角錐形状となる。At this time, if the etched surface of the Si substrate 41 is a (100) plane and etching is performed with an alkaline solution, the etched surface will have a quadrangular pyramid shape.
そして、エツチング面に、再度、低圧ＣＶＤ法により絶
縁膜を形成することによって、（ｄ）に示すように、バ
ンプ接続部に相応する位置に、貫通孔４ａ・・・４ａが
形成された絶縁性のスペーサ４を得る。Then, by forming an insulating film on the etched surface again by low-pressure CVD, an insulating film is formed with through holes 4a...4a formed at positions corresponding to the bump connection parts, as shown in (d). spacer 4 is obtained.
一
なお、本発明はＩＣチップのみならず、例えばＬＳＩチ
ップ等の半導体チップ、あるいは各種チップ状電気部品
等にも適用できることはいうまでもない。It goes without saying that the present invention is applicable not only to IC chips, but also to semiconductor chips such as LSI chips, and various chip-shaped electrical components.
〈発明の効果〉
以上説明したように、本発明によれば、ＩＣチップとそ
の実装基板との間に、その接続部に相応する位置に貫通
孔が穿たれた絶縁板を挟み込んだ状態で、接続に用いる
バンプ状導電材のリフローを行うので、チップと基板と
の相互の位置精度が向上するとともに、バンプ部に作用
する熱応力によるクラック等の発生確率等が減少して、
高密度実装においても、その接続の信軌性が高い実装を
実現できる。また、絶縁板が放熱板の機能を果たし、回
路増産時の電力消費による発熱に対して冷却効率が向上
するという点の効果もある。<Effects of the Invention> As explained above, according to the present invention, an insulating plate having a through hole bored at a position corresponding to the connection part is sandwiched between an IC chip and its mounting board, and Since the bump-shaped conductive material used for connection is reflowed, the mutual positional accuracy between the chip and the substrate is improved, and the probability of cracks etc. occurring due to thermal stress acting on the bumps is reduced.
Even in high-density mounting, it is possible to realize mounting with high connection reliability. Another advantage is that the insulating plate functions as a heat sink, improving cooling efficiency against heat generated by power consumption during increased circuit production.
第１図は本発明のフリップチップ実装方法の手順を説明
する図、第２図はそのスペーサ４の製作する手順を説明
するための図である。
１ ・
１ ａ・・・１ ａ ・
２ ・
２ａ・・・２ａ ・
３・・・３ ・
４ ・
４ａ・・・４ａ ・
ＩＣチップ
パッド
基板
導体パターン
はんだバンプ
スペーサ（絶縁板）
貫通孔FIG. 1 is a diagram for explaining the procedure of the flip-chip mounting method of the present invention, and FIG. 2 is a diagram for explaining the procedure for manufacturing the spacer 4. 1 ・ 1 a...1 a ・ 2 ・ 2a... 2a ・ 3... 3 ・ 4 ・ 4a... 4a ・ IC chip pad board conductor pattern solder bump spacer (insulating plate) through hole
Claims (1)
の実装基板の導体部のいずれか一方にバンプ状の導電材
を形成しておき、上記回路チップと上記実装基板とを位
置合わせした状態で、上記バンプ状導電材のリフローを
行うことによって、上記回路チップを上記実装基板の導
体部に接続する方法において、上記バンプ状導電材に相
応する位置に貫通孔が穿たれた絶縁板を、上記回路チッ
プと上記実装基板との間に挟み込んだ状態で、上記リフ
ローを行うことを特徴とする、フリップチップ実装方法
。A bump-shaped conductive material is formed on either a pad on the surface of a circuit chip such as an IC chip or a conductor portion of its mounting board, and when the circuit chip and the mounting board are aligned, the bump is In the method of connecting the circuit chip to the conductor portion of the mounting board by reflowing the bump-shaped conductive material, an insulating plate having through holes bored at positions corresponding to the bump-shaped conductive material is connected to the circuit chip. A flip chip mounting method characterized in that the reflow is performed while the flip chip is sandwiched between the mounting board and the mounting board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2113447A JPH0410635A (en) | 1990-04-27 | 1990-04-27 | Flip chip package mounting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2113447A JPH0410635A (en) | 1990-04-27 | 1990-04-27 | Flip chip package mounting |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0410635A true JPH0410635A (en) | 1992-01-14 |
Family
ID=14612466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2113447A Pending JPH0410635A (en) | 1990-04-27 | 1990-04-27 | Flip chip package mounting |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0410635A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06232203A (en) * | 1993-02-03 | 1994-08-19 | Nec Corp | Lsi packaging structure |
| US5730620A (en) * | 1995-09-08 | 1998-03-24 | International Business Machines Corporation | Method and apparatus for locating electrical circuit members |
| KR100411810B1 (en) * | 1995-12-27 | 2004-03-31 | 앰코 테크놀로지 코리아 주식회사 | Chip size type semiconductor package using flip chip technique |
| KR100411809B1 (en) * | 1995-12-27 | 2004-03-31 | 앰코 테크놀로지 코리아 주식회사 | Chip size type semiconductor package |
| US6905915B2 (en) | 2002-02-18 | 2005-06-14 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, and electronic instrument |
-
1990
- 1990-04-27 JP JP2113447A patent/JPH0410635A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06232203A (en) * | 1993-02-03 | 1994-08-19 | Nec Corp | Lsi packaging structure |
| US5730620A (en) * | 1995-09-08 | 1998-03-24 | International Business Machines Corporation | Method and apparatus for locating electrical circuit members |
| KR100411810B1 (en) * | 1995-12-27 | 2004-03-31 | 앰코 테크놀로지 코리아 주식회사 | Chip size type semiconductor package using flip chip technique |
| KR100411809B1 (en) * | 1995-12-27 | 2004-03-31 | 앰코 테크놀로지 코리아 주식회사 | Chip size type semiconductor package |
| US6905915B2 (en) | 2002-02-18 | 2005-06-14 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, and electronic instrument |
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