JP7552358B2 - LIQUID EJECTION DEVICE AND POWER CIRCUIT - Google Patents

Description

The present invention relates to a liquid ejection device and a power supply circuit.

In electronic devices such as liquid ejection devices that form images on media by ejecting liquid from a liquid ejection head, a voltage of a desired value is supplied to a drive unit such as a liquid ejection head, causing the drive unit to start operating and perform the desired operation. However, when a power supply voltage is supplied to the drive unit, an inrush current may occur due to a capacitive element or the like provided in the supply path of the power supply voltage. Such inrush currents are large in amount and may cause abnormalities in the circuit elements that make up electronic devices such as liquid ejection devices, so various measures are taken.

For example, Patent Document 1 discloses a configuration in which an inrush current reduction circuit is provided in a power supply voltage supply path, and when the supply of the power supply voltage starts, a switch element of the inrush current reduction circuit is pulse-driven to reduce the current value of the inrush current and reduce the risk of causing an abnormality in a circuit element constituting an electronic device such as a liquid ejection device.

JP 2020-189430 A

Discrete components are widely used in the circuit elements constituting the inrush current reduction circuit described in Patent Document 1 because a large current flows due to the power supply voltage for driving the drive unit and because it is necessary to select optimal components according to the characteristics of the drive unit. However, when the inrush current reduction circuit is composed of discrete components, the circuit scale of the power supply circuit including the inrush current reduction circuit becomes large, resulting in a problem that it is difficult to miniaturize the power supply circuit including the inrush current reduction circuit. In other words, there is room for improvement in terms of miniaturizing the power supply circuit including the inrush current reduction circuit compared to the invention described in Patent Document 1.

One aspect of the liquid ejection device according to the present invention is to
A liquid ejection device that ejects liquid,
A drive unit that ejects liquid when driven;
a power supply circuit for supplying a power supply voltage to the driving unit;
Equipped with
The power supply circuit includes:
a power supply voltage output circuit that outputs the power supply voltage;
a first transistor having one end electrically connected to the power supply voltage output circuit and the other end electrically connected to the drive unit, the first transistor being operated based on an input to a first control terminal;
an integrated circuit device including a first terminal electrically connected to the power supply voltage output circuit, a second terminal electrically connected to the drive unit, and a third terminal electrically connected to a control terminal of the first transistor;
having
The integrated circuit device comprises:
a second transistor having one end electrically connected to the first terminal and the other end electrically connected to the second terminal, and operating based on an input to a second control terminal;
a first transistor control circuit electrically connected to the third terminal and configured to control an operation of the first transistor;
a second transistor control circuit electrically connected to the second control terminal and configured to control an operation of the second transistor;
Includes.

One aspect of the power supply circuit according to the present invention is
A power supply circuit for supplying a power supply voltage to a drive unit,
a power supply voltage output circuit that outputs the power supply voltage;
a first transistor having one end electrically connected to the power supply voltage output circuit and the other end electrically connected to the drive unit, the first transistor being operated based on an input to a first control terminal;
an integrated circuit device including a first terminal electrically connected to the power supply voltage output circuit, a second terminal electrically connected to the drive unit, and a third terminal electrically connected to a control terminal of the first transistor;
having
The integrated circuit device comprises:
a second transistor having one end electrically connected to the first terminal and the other end electrically connected to the second terminal, and operating based on an input to a second control terminal;
a first transistor control circuit electrically connected to the third terminal and configured to control an operation of the first transistor;
a second transistor control circuit electrically connected to the second control terminal and configured to control an operation of the second transistor;
Includes.

FIG. 1 is a diagram illustrating a schematic configuration of a liquid ejection device. FIG. 2 is a diagram illustrating a functional configuration of the liquid ejection device. FIG. 4 is a diagram showing an example of a drive signal COM. FIG. 4 is a diagram illustrating a functional configuration of a drive signal selection control circuit. FIG. 4 is a diagram showing the electrical configuration of a selection circuit corresponding to one ejection portion. FIG. 2 is a diagram showing the decoded contents in a decoder. 5 is a diagram for explaining the operation of a drive signal selection control circuit. FIG. FIG. 2 is a diagram showing a schematic configuration of a discharge unit. 4 is a diagram showing an electrical connection relationship between a drive signal output circuit and a power supply circuit. FIG. FIG. 2 is a diagram illustrating a functional configuration of a drive signal output circuit. FIG. 4 is a diagram showing a configuration of a drive signal discharge circuit. FIG. 2 is a diagram illustrating a configuration of a reference voltage signal output circuit. FIG. 2 is a diagram showing a configuration of a VHV control signal output circuit. FIG. 2 is a diagram illustrating a configuration of a status signal input/output circuit. FIG. 2 is a diagram illustrating a configuration of an error signal input/output circuit. FIG. 2 is a diagram illustrating a configuration of a power supply circuit. 11 is a diagram for explaining an operation when starting to supply the voltage VHV to the print head and the drive signal output circuit. FIG. FIG. 11 is a diagram showing a configuration of a power supply circuit according to a second embodiment. 13 is a diagram for explaining an operation when starting to supply the voltage VHV to the print head and the drive signal output circuit in the second embodiment. FIG. FIG. 13 is a diagram showing a configuration of a power supply circuit according to a third embodiment.

Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings are used for the convenience of explanation. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

1. First embodiment 1.1 Configuration of the liquid ejection device The liquid ejection device according to the first embodiment is an inkjet printer that forms dots on a printing medium such as paper by ejecting ink in accordance with image data input from an external host computer, and prints images including characters, figures, etc. in accordance with the image data.

Figure 1 is a diagram showing the schematic configuration of a liquid ejection device 1. Figure 1 shows a direction X in which a medium P is transported, a direction Y in which a moving body 2 reciprocates intersecting with direction X, and a direction Z in which ink is ejected. Note that in this embodiment, directions X, Y, and Z are described as mutually orthogonal axes, but this is not limited to the various components of the liquid ejection device 1 being disposed orthogonal to each other. In the following description, direction Y in which the moving body 2 moves may be referred to as the main scanning direction.

As shown in FIG. 1, the liquid ejection device 1 includes a moving body 2 and a moving mechanism 3 that reciprocates the moving body 2 along direction Y. The moving mechanism 3 includes a carriage motor 31 that serves as the drive source for the moving body 2, a carriage guide shaft 32 that has both ends fixed, and a timing belt 33 that extends substantially parallel to the carriage guide shaft 32 and is driven by the carriage motor 31.

The carriage 24 included in the moving body 2 is supported by a carriage guide shaft 32 so as to be freely movable back and forth, and is fixed to a part of a timing belt 33. Then, by driving the timing belt 33 by a carriage motor 31, the carriage 24 is guided by the carriage guide shaft 32 and moves back and forth along the direction Y. Also, a print head 20 having a large number of nozzles is provided on a part of the moving body 2 facing the medium P. A control signal and the like are input to the print head 20 via a cable 190. Then, the print head 20 ejects ink, an example of a liquid, from the nozzles based on the input control signal.

The liquid ejection device 1 also includes a transport mechanism 4 that transports the medium P on the platen 40 along the direction X. The transport mechanism 4 includes a transport motor 41, which is a drive source, and a transport roller 42 that is rotated by the transport motor 41 to transport the medium P along the direction X.

In the liquid ejection device 1 configured as described above, an image is formed on the surface of the medium P by ejecting ink from the print head 20 at the timing when the medium P is transported by the transport mechanism 4.

2 is a diagram showing the functional configuration of the liquid ejection device 1. As shown in Fig. 2, the liquid ejection device 1 has a control circuit 100, a carriage motor driver 35, a carriage motor 31, a transport motor driver 45, a transport motor 41, an oscillation circuit 91, a drive signal output circuit 51, a power supply circuit 52, and a print head 20.

The control circuit 100 generates a plurality of control signals for controlling various components based on image data input from the host computer, and outputs the signals to the corresponding components. Specifically, the control circuit 100 supplies a control signal CTR1 to the carriage motor driver 35. The carriage motor driver 35 drives the carriage motor 31 according to the control signal CTR1. This controls the movement of the carriage 24 in the direction Y shown in FIG. 1. The control circuit 100 also supplies a control signal CTR2 to the transport motor driver 45. The transport motor driver 45 drives the transport motor 41 according to the control signal CTR2. This controls the movement of the medium P in the direction X shown in FIG. 1.

The control circuit 100 also outputs a drive data signal DATA to the drive signal output circuit 51, and outputs a clock signal SCK, a print data signal SI, a latch signal LAT, and a change signal CH to the print head 20.

The oscillator circuit 91 outputs the clock signal MCK to the drive signal output circuit 51. Here, the oscillator circuit 91 may be configured independent of the control circuit 100 as shown in FIG. 2, or may be configured inside the control circuit 100. Furthermore, the clock signal MCK may be supplied to various components of the liquid ejection device 1 in addition to the drive signal output circuit 51.

The power supply circuit 52 generates and outputs voltages VHV and VDD from a commercial AC power supply input to the liquid ejection device 1 as power supply voltages used by each part of the liquid ejection device 1. The voltage VHV is, for example, a DC voltage of 42 V, and is supplied to each part of the liquid ejection device 1 including the drive signal output circuit 51 and the print head 20. The voltage VDD is, for example, a DC voltage of 3.3 V, and is supplied to each part of the liquid ejection device 1 including the drive signal output circuit 51 and the print head 20.

The drive signal output circuit 51 receives the voltages VHV, VDD, the drive data signal DATA, and the clock signal MCK. Based on the input voltages VHV, VDD, the drive data signal DATA, and the clock signal MCK, the drive signal output circuit 51 generates the drive signal COM and the reference voltage signal VBS and outputs them to the print head 20. Here, the reference voltage signal VBS is a DC voltage whose potential is the reference for the drive signal COM, and is a constant voltage signal such as ground potential, 5V, or 6V. The configurations and operations of the drive signal output circuit 51 and the power supply circuit 52 will be described in detail later.

The print head 20 has a drive signal selection control circuit 200 and multiple ejection units 600. Each ejection unit 600 includes a piezoelectric element 60. A clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, a drive signal COM, and a voltage VHV are input to the drive signal selection control circuit 200. The drive signal selection control circuit 200 selects or deselects the drive signal COM based on the clock signal SCK, the print data signal SI, the latch signal LAT, the change signal CH, and the voltage VHV to generate a drive signal VOUT and output it to the corresponding ejection unit 600.

The drive signal VOUT is supplied to one end of a piezoelectric element 60 included in each of the multiple ejection sections 600. The other end of the piezoelectric element 60 is supplied with a reference voltage signal VBS output by the drive signal output circuit 51. The piezoelectric element 60 is driven by the potential difference between the drive signal VOUT and the reference voltage signal VBS. Ink is ejected from the ejection section 600 by driving the piezoelectric element 60.

As described above, the liquid ejection device 1 includes a print head 20 that includes a piezoelectric element 60 and ejects ink when the piezoelectric element 60 is driven, and a power supply circuit 52 that supplies a power supply voltage VHV to the print head 20. Here, the print head 20 that includes a piezoelectric element 60 and ejects ink when the piezoelectric element 60 is driven is an example of a drive unit and a liquid ejection head.

1.3 Configuration and operation of liquid ejection head Next, the configuration and operation of the drive signal selection control circuit 200 of the print head 20 will be described. In describing the configuration and operation of the drive signal selection control circuit 200, first, an example of the drive signal COM input to the drive signal selection control circuit 200 will be described using Figure 3. Then, the configuration and operation of the drive signal selection control circuit 200 will be described using Figures 4 to 7.

Figure 3 is a diagram showing an example of the drive signal COM. Figure 3 shows a period T1 from when the latch signal LAT rises until the change signal CH rises, a period T2 from when the change signal CH rises again after period T1, and a period T3 from when the latch signal LAT rises after period T2. The cycle consisting of periods T1, T2, and T3 becomes the cycle Ta for forming new dots on medium P. That is, as shown in Figure 3, the latch signal LAT is a signal that specifies the cycle for forming new dots on medium P, and the change signal CH is a signal that specifies the switching timing of the waveform included in the drive signal COM.

As shown in FIG. 3, the drive signal output circuit 51 generates a trapezoidal waveform Adp in a period T1. When the trapezoidal waveform Adp is supplied to the piezoelectric element 60, a predetermined amount, specifically a medium amount, of ink is ejected from the corresponding ejection section 600. The drive signal output circuit 51 also generates a trapezoidal waveform Bdp in a period T2. When the trapezoidal waveform Bdp is supplied to the piezoelectric element 60, a small amount of ink less than the predetermined amount is ejected from the corresponding ejection section 600. The drive signal output circuit 51 also generates a trapezoidal waveform Cdp in a period T3. When the trapezoidal waveform Cdp is supplied to the piezoelectric element 60, the piezoelectric element 60 is driven to such an extent that ink is not ejected from the corresponding ejection section 600. Therefore, when the trapezoidal waveform Cdp is supplied to the piezoelectric element 60, no dots are formed on the medium P. This trapezoidal waveform Cdp is a waveform for preventing the viscosity of the ink from increasing by micro-vibrating the ink near the nozzle opening of the ejection section 600. In the following description, driving the piezoelectric element 60 to such an extent that ink is not ejected from the ejection portion 600 in order to prevent the viscosity of the ink from increasing is referred to as "micro-vibration."

Here, the voltage values at the start timing and end timing of each of the trapezoidal waveforms Adp, Bdp, and Cdp are all common to the voltage Vc. In other words, the trapezoidal waveforms Adp, Bdp, and Cdp are waveforms that start and end at voltage Vc. Therefore, the drive signal output circuit 51 outputs a drive signal COM in which the trapezoidal waveforms Adp, Bdp, and Cdp are continuous in the period Ta. Note that the waveform of the drive signal COM shown in FIG. 3 is an example, and is not limited to the waveform shown in FIG. 3.

Figure 4 is a diagram showing the functional configuration of the drive signal selection control circuit 200. The drive signal selection control circuit 200 generates and outputs the drive signal VOUT supplied to the piezoelectric element 60 in the cycle Ta by switching whether or not to select the trapezoidal waveforms Adp, Bdp, and Cdp included in the drive signal COM during each of the periods T1, T2, and T3. As shown in Figure 4, the drive signal selection control circuit 200 includes a selection control circuit 210 and a plurality of selection circuits 230.

The selection control circuit 210 is supplied with a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, and a voltage VHV. The selection control circuit 210 is provided with a set of a shift register 212 (S/R), a latch circuit 214, and a decoder 216 corresponding to each of the ejection sections 600. In other words, the print head 20 is provided with n sets of shift registers 212, latch circuits 214, and decoders 216, the same number as the total number of n ejection sections 600.

The shift register 212 temporarily holds 2-bit print data [SIH, SIL] included in the print data signal SI for each corresponding ejection unit 600. In detail, the shift registers 212, the number of stages of which corresponds to the ejection units 600, are connected in cascade, and the print data signal SI supplied in serial is sequentially transferred to the subsequent stages in accordance with the clock signal SCK. In Fig. 4, in order to distinguish the shift registers 212, they are denoted as 1st stage, 2nd stage, ..., nth stage in order from the upstream side to which the print data signal SI is supplied.

Each of the n latch circuits 214 latches the print data [SIH, SIL] held in the corresponding shift register 212 at the rising edge of the latch signal LAT. Each of the n decoders 216 decodes the 2-bit print data [SIH, SIL] latched by the corresponding latch circuit 214 to generate a selection signal S and supplies it to the selection circuit 230.

The selection circuits 230 are provided corresponding to each of the ejection sections 600. In other words, the number of selection circuits 230 that one print head 20 has is the same as the total number of ejection sections 600 included in the print head 20. The selection circuits 230 control the supply of the drive signal COM to the piezoelectric elements 60 based on the selection signal S supplied from the decoder 216.

Figure 5 is a diagram showing the electrical configuration of the selection circuit 230 corresponding to one of the ejection parts 600. As shown in Figure 5, the selection circuit 230 has an inverter 232 and a transfer gate 234. In addition, the transfer gate 234 includes a transistor 235 which is an NMOS transistor and a transistor 236 which is a PMOS transistor.

The selection signal S is supplied from the decoder 216 to the gate terminal of the transistor 235. The selection signal S is also logically inverted by the inverter 232 and supplied to the gate terminal of the transistor 236. The drain terminal of the transistor 235 and the source terminal of the transistor 236 are connected to the terminal TG-In, which is one end of the transfer gate 234. The drive signal COM is input to the terminal TG-In of the transfer gate 234. Then, the transistors 235 and 236 are controlled to be turned on or off according to the selection signal S, and the drive signal VOUT is output from the terminal TG-Out, which is the other end of the transfer gate 234 to which the source terminal of the transistor 235 and the drain terminal of the transistor 236 are commonly connected. The terminal TG-Out of the transfer gate 234 from which the drive signal VOUT is output is electrically connected to the electrode 611 of the piezoelectric element 60, which will be described later. In the following description, when transistors 235 and 236 are controlled to be in a conductive state, this may be referred to as being on, and when transistors 235 and 236 are controlled to be in a non-conductive state, this may be referred to as being off.

Next, the contents of the decoded data by the decoder 216 will be described with reference to FIG. 6. FIG. 6 is a diagram showing the contents of the decoded data by the decoder 216. The decoder 216 receives two-bit print data [SIH, SIL], a latch signal LAT, and a change signal CH. For example, when the print data [SIH, SIL] is [1, 0] that specifies a "medium dot", the decoder 216 outputs a selection signal S that is at H, L, and L levels during periods T1, T2, and T3. Here, the logical level of the selection signal S is level-shifted to a high amplitude logic based on the voltage VHV by a level shifter (not shown).

7 is a diagram for explaining the operation of the drive signal selection control circuit 200. As shown in FIG. 7, the print data signal SI is serially supplied to the drive signal selection control circuit 200 in synchronization with the clock signal SCK, and is sequentially transferred in the shift register 212 corresponding to the ejection unit 600. Then, when the supply of the clock signal SCK is stopped, the shift register 212
Each of these holds print data [SIH, SIL] corresponding to the ejection unit 600. The print data signal SI is supplied in an order corresponding to the ejection units 600 of the final n-th stage, ..., 2nd stage, and 1st stage in the shift register 212.

Here, when the latch signal LAT rises, each of the latch circuits 214 simultaneously latches the print data [SIH, SIL] held in the corresponding shift register 212. LT1, LT2, ..., LTn shown in FIG. 7 are the print data [SIH, SIL] latched by the latch circuits 214 corresponding to the 1st, 2nd, ..., nth stages of the shift register 212.

The decoder 216 outputs a selection signal S with a logic level according to the contents shown in FIG. 6 during each of periods T1, T2, and T3, depending on the dot size specified by the latched print data [SIH, SIL].

When the print data [SIH, SIL] is [1, 1], the selection circuit 230 selects the trapezoidal waveform Adp in the period T1, selects the trapezoidal waveform Bdp in the period T2, and does not select the trapezoidal waveform Cdp in the period T3 in accordance with the selection signal S. As a result, the drive signal VOUT corresponding to the large dot shown in FIG. 7 is generated. Therefore, a medium amount of ink and a small amount of ink are ejected from the ejection unit 600. Therefore, the inks are combined to form a large dot on the medium P. Also, when the print data [SIH, SIL] is [1, 0], the selection circuit 230 selects the trapezoidal waveform Adp in the period T1 in accordance with the selection signal S, does not select the trapezoidal waveform Bdp in the period T2, and does not select the trapezoidal waveform Cdp in the period T3. As a result, the drive signal VOUT corresponding to the medium dot shown in FIG. 7 is generated. Therefore, a medium amount of ink is ejected from the ejection unit 600. Therefore, a medium dot is formed on the medium P. Also, when the print data [SIH, SIL] is [0, 1], the selection circuit 230 does not select the trapezoidal waveform Adp in the period T1, selects the trapezoidal waveform Bdp in the period T2, and does not select the trapezoidal waveform Cdp in the period T3 in accordance with the selection signal S. As a result, the drive signal VOUT corresponding to the small dot shown in FIG. 7 is generated. Therefore, a small amount of ink is ejected from the ejection unit 600. Thus, a small dot is formed on the medium P. Also, when the print data [SIH, SIL] is [0, 0], the selection circuit 230 does not select the trapezoidal waveform Adp in the period T1, does not select the trapezoidal waveform Bdp in the period T2, and selects the trapezoidal waveform Cdp in the period T3 in accordance with the selection signal S. As a result, the drive signal VOUT corresponding to the micro-vibration shown in FIG. 7 is generated. Therefore, ink is not ejected from the ejection unit 600, and micro-vibration occurs.

As described above, the drive signal selection control circuit 200 generates the drive signal VOUT by selecting the trapezoidal waveform included in the drive signal COM output by the drive signal output circuit 51, and outputs it to the ejection unit 600. Here, the configuration and operation of the ejection unit 600 including the piezoelectric element 60 will be described with reference to FIG. 8. FIG. 8 is a diagram showing the schematic configuration of the ejection unit 600 when the print head 20 is cut to include the ejection unit 600.

As shown in FIG. 8, the print head 20 includes an ejection section 600 and a reservoir 641. Ink is introduced into the reservoir 641 from a supply port 661. A reservoir 641 is provided for each ink color.

The ejection section 600 includes a piezoelectric element 60, a vibration plate 621, a cavity 631, and a nozzle 651. The vibration plate 621 is provided between the cavity 631 and the piezoelectric element 60. The vibration plate 621 is displaced by the piezoelectric element 60 provided on the upper surface being driven. That is, the vibration plate 621 functions as a diaphragm that expands/contracts the internal volume of the cavity 631 by being displaced. The cavity 631 is filled with ink. The cavity 631 functions as a pressure chamber whose internal volume changes by the driving of the piezoelectric element 60. The nozzle 651 is provided in the nozzle plate 632 and is an opening portion that communicates with the cavity 631.

The piezoelectric element 60 has a structure in which a piezoelectric body 601 is sandwiched between a pair of electrodes 611, 612. A drive signal VOUT is supplied to the electrode 611, and a reference voltage signal VBS is supplied to the electrode 612. The piezoelectric element 60 having such a structure is driven according to the potential difference between the electrodes 611 and 612. As the piezoelectric element 60 is driven, the electrodes 611, 612 and the central portion of the vibration plate 621 are displaced in the vertical direction relative to both end portions. As the vibration plate 621 is displaced, the internal volume of the cavity 631 changes, and the ink filled inside the cavity 631 is ejected from the nozzle 651.

1.4 Configuration and operation of the drive signal output circuit and power supply circuit Next, the configuration and operation of the drive signal output circuit 51 and the power supply circuit 52 will be described. Fig. 9 is a diagram showing the electrical connection relationship between the drive signal output circuit 51 and the power supply circuit 52. As shown in Fig. 9, the power supply circuit 52 supplies a voltage VDD to the drive signal output circuit 51, and outputs a voltage VHV to the drive signal output circuit 51 and the print head 20 based on a VHV control signal VHV_CNT output by the drive signal output circuit 51. The drive signal output circuit 51 operates based on the voltage VDD output by the power supply circuit 52, thereby generating and outputting a drive signal COM according to the voltage value of the voltage VHV.

Here, the voltage VHV output by the power supply circuit 52 is supplied to the drive signal output circuit 51 via the fuse 80, and is also supplied to the drive signal output circuit 51 and the print head 20 via the fuses 80 and 81. In the following description, the voltage VHV output by the power supply circuit 52 and input to the fuse 80 may be referred to as voltage VHVa, the voltage VHV output from the fuse 80 and input to the drive signal output circuit 51 and the fuse 81 may be referred to as voltage VHVb, and the voltage VHV output from the fuse 81 and input to the drive signal output circuit 51 and the print head 20 may be referred to as voltage VHVc. In addition, the propagation path through which the voltage VHVa propagates may be referred to as propagation wiring a, the propagation path through which the voltage VHVb propagates may be referred to as propagation wiring b, and the propagation path through which the voltage VHVc propagates may be referred to as propagation wiring c. That is, at least one of the propagation wirings a, b, and c is an example of a propagation path.

1.4.1 Configuration and operation of the drive signal output circuit First, the functional configuration of the drive signal output circuit 51 will be described with reference to FIG. 10. FIG. 10 is a diagram showing the functional configuration of the drive signal output circuit 51. As shown in FIG. 10, the drive signal output circuit 51 includes an integrated circuit 500, an amplifier circuit 550, a demodulation circuit 560, and a feedback circuit 570. The drive signal output circuit 51 outputs a drive signal COM based on the input voltages VDD, VHVb, VHVc, a clock signal MCK, and a drive data signal DATA. In addition, an error signal ERR and a status signal BUSY are mutually propagated between the drive signal output circuit 51 and the control circuit 100.

The integrated circuit 500 includes an amplification control signal generation circuit 502, an internal voltage generation circuit 400, an oscillation circuit 410, a clock selection circuit 420, an abnormality detection circuit 430, a register control circuit 440, a drive signal discharge circuit 450, a reference voltage signal output circuit 460, a VHV control signal output circuit 470, a status signal input/output circuit 480, and an error signal input/output circuit 490.

The internal voltage generating circuit 400 is supplied with a voltage VDD. The internal voltage generating circuit 400 generates a voltage GVDD of, for example, DC 7.5 V by boosting the input voltage VDD. The voltage GVDD is input to various components of the integrated circuit 500, including the gate driving unit 540 described below.

The amplification control signal generation circuit 502 generates the amplification control signals Hgd and Lgd based on a data signal that defines the waveform of the drive signal COM contained in the drive data signal DATA input from the terminal DATA-In. The amplification control signal generation circuit 502 includes a DAC interface (DAC_I/F: Digital to Analog Converter Interface) 510, a DAC section 520, a modulation section 530, and a gate driver 540.

The DAC interface 510 receives the drive data signal DATA supplied from the terminal DATA-In and the clock signal MCK supplied from the terminal CLK-In. The DAC interface 510 accumulates the drive data signal DATA based on the clock signal MCK to generate, for example, 10-bit drive data dA that defines the waveform of the drive signal COM. The drive data dA is input to the DAC unit 520. The DAC unit 520 converts the input drive data dA into an original drive signal aA, which is an analog signal. This original drive signal aA is the target signal before the drive signal COM is amplified. The original drive signal aA is input to the modulation unit 530. The modulation unit 530 outputs a modulated signal Ms obtained by performing pulse width modulation on the original drive signal aA. The gate drive unit 540 receives the voltages VHV, GVDD and the modulated signal Ms. The gate driver 540 amplifies the input modulation signal Ms based on the voltage GVDD, and generates an amplification control signal Hgd that is level-shifted to a high amplitude logic based on the voltage VHV, and an amplification control signal Lgd that inverts the logic level of the input modulation signal Ms and amplifies it based on the voltage GVDD. That is, the amplification control signal Hgd and the amplification control signal Lgd are mutually exclusive to each other at the H level. The amplification control signal Hgd is output from the integrated circuit 500 via the terminal Hg-Out and input to the amplifier circuit 550. Similarly, the amplification control signal Lgd is output from the integrated circuit 500 via the terminal Lg-Out and input to the amplifier circuit 550.

The amplifier circuit 550 operates based on the amplification control signals Hgd and Lgd to output the amplified modulation signal AMs. The amplifier circuit 550 includes transistors 551 and 552.
Each of the transistors 551 and 552 is, for example, an N-channel type field effect transistor (FET).

A voltage VHV is supplied to the drain terminal of transistor 551. An amplification control signal Hgd is supplied to the gate terminal of transistor 551 via terminal Hg-Out. A source terminal of transistor 551 is electrically connected to the drain terminal of transistor 552. An amplification control signal Lgd is supplied to the gate terminal of transistor 552 via terminal Lg-Out. A source terminal of transistor 552 is connected to ground. Transistor 551 connected as above operates according to the amplification control signal Hgd, and transistor 552 operates according to the amplification control signal Lgd. That is, transistors 551 and 552 are exclusively turned on. As a result, an amplified modulation signal AMs obtained by amplifying modulation signal Ms based on voltage VHV is generated at the connection point between the source terminal of transistor 551 and the drain terminal of transistor 552.

The amplified modulation signal AMs generated by the amplifier circuit 550 is input to the demodulation circuit 560. The demodulation circuit 560 includes a coil 561 and a capacitor 562. One end of the coil 561 is commonly connected to the source terminal of the transistor 551 and the drain terminal of the transistor 552. The other end of the coil 561 is connected to one end of the capacitor 562. The other end of the capacitor 562 is connected to the ground. In other words, the coil 561 and the capacitor 562 form a low-pass filter. Then, when the amplified modulation signal AMs is supplied to the low-pass filter, the amplified modulation signal AMs is demodulated and the drive signal COM is generated. This drive signal COM is output from the drive signal output circuit 51.

The drive signal COM generated by the demodulation circuit 560 is fed back to the modulation unit 530 via a feedback circuit 570. The feedback circuit 570 includes resistors 571 and 572. One end of the resistor 571 is connected to the other end of the coil 561, and the other end of the resistor 571 is connected to one end of the resistor 572. A voltage VHVc is supplied to the other end of the resistor 572. The other end of the resistor 571 and one end of the resistor 572 are connected in common to a terminal Com-Dis, and are connected to the demodulation circuit 560 via the terminal Com-Dis. That is, the drive signal COM is pulled up by the voltage VHVc and fed back to the modulation unit 530 via the feedback circuit 570.

Here, in the following description, the configuration including the amplification control signal generation circuit 502, the amplification circuit 550, the demodulation circuit 560, and the feedback circuit 570 included in the integrated circuit 500 may be referred to as the drive signal generation circuit 501 that generates the drive signal COM based on the drive data signal DATA.

The oscillator circuit 410 generates and outputs a clock signal LCK that defines the operation timing of the integrated circuit 500. The clock signal LCK is input to the clock selection circuit 420 and the anomaly detection circuit 430.

The clock selection circuit 420 receives the clock signals MCK, LCK, and the clock selection signal CSW. Based on the logic level of the clock selection signal CSW, the clock selection circuit 420 switches between outputting the clock signal MCK to the register control circuit 440 as the clock signal RCK, or outputting the clock signal LCK to the register control circuit 440 as the clock signal RCK. In this embodiment, the clock selection circuit 420 outputs the clock signal MCK to the register control circuit 440 as the clock signal RCK when the clock selection signal CSW is at an H level, and outputs the clock signal LCK to the register control circuit 440 as the clock signal RCK when the clock selection signal CSW is at an L level.

The abnormality detection circuit 430 includes an oscillation abnormality detection unit 431, an operation abnormality detection unit 432, and a power supply voltage abnormality detection unit 433.

The clock signal LCK output by the oscillation circuit 410 is input to the oscillation abnormality detection unit 431. The oscillation abnormality detection unit 431 detects whether the input clock signal LCK is normal or not, and outputs a clock selection signal CSW and an error signal NES of a logic level based on the detection result. For example, the oscillation abnormality detection unit 431 detects at least one of the frequency and voltage level of the clock signal LCK. Then, when at least one of the frequency and voltage level of the clock signal LCK is abnormal, the oscillation abnormality detection unit 431 outputs an H-level clock selection signal CSW to the clock selection circuit 420 and outputs an H-level error signal NES to the register control circuit 440. Also, when both the frequency and voltage level of the clock signal LCK are normal, the oscillation abnormality detection unit 431 outputs an L-level clock selection signal CSW to the clock selection circuit 420 and outputs an L-level error signal NES to the register control circuit 440.

The operation abnormality detection unit 432 receives an operation status signal ASS indicating the operation status of the various components of the drive signal output circuit 51. The operation abnormality detection unit 432 detects whether the various components of the drive signal output circuit 51 are operating normally based on the logic level of the input operation status signal ASS. In this embodiment, if any of the various components of the drive signal output circuit 51 is abnormal, an H-level operation status signal ASS is input to the operation abnormality detection unit 432. Then, if an H-level operation status signal ASS is input to the operation abnormality detection unit 432, the operation abnormality detection unit 432 outputs an H-level error signal NES to the register control circuit 440.

The power supply voltage abnormality detection unit 433 receives the voltage VHVc supplied to the print head 20. The power supply voltage abnormality detection unit 433 detects the voltage value of the voltage VHVc. Then, based on the voltage value of the voltage VHVc, the power supply voltage abnormality detection unit 433 detects whether the voltage level of the voltage VHVc supplied to the print head 20 is normal or not. In this embodiment, if the power supply voltage abnormality detection unit 433 determines that the voltage level of the voltage VHVc supplied to the print head 20 is abnormal, the power supply voltage abnormality detection unit 433 outputs an H-level error signal FES to the register control circuit 440.

The register control circuit 440 includes a sequence register 441, a status register 442, and a register control unit 443. The sequence register 441 and the status register 442 hold operation information that is input as a drive data signal DATA in synchronization with the clock signal MCK. The register control unit 443 then generates and outputs control signals CNT1 to CNT6 in synchronization with the clock signal RCK, based on the information held in the sequence register 441 and the status register 442. This controls the operation of the drive signal output circuit 51.

The control signal CNT1 is input to the drive signal discharge circuit 450. The drive signal discharge circuit 450 controls the release of charge based on the drive signal COM output from the drive signal output circuit 51. FIG. 11 is a diagram showing the configuration of the drive signal discharge circuit 450. The drive signal discharge circuit 450 includes a resistor 451, a transistor 452, and an inverter 453. In the following explanation, the transistor 452 will be explained as an NMOS transistor.

One end of resistor 451 is connected to terminal Com-Dis. The other end of resistor 451 is connected to the drain terminal of transistor 452. The source terminal of transistor 452 is connected to ground. A control signal CNT1 is input to the gate terminal of transistor 452 via inverter 453. When a high-level control signal CNT1 is input to the drive signal discharge circuit 450 configured as described above, transistor 452 is controlled to be off. Therefore, drive signal discharge circuit 450 does not discharge the charge stored in terminal Com-Dis. On the other hand, when a low-level control signal CNT1 is input to drive signal discharge circuit 450, transistor 452 is controlled to be on. Therefore, drive signal discharge circuit 450 discharges the charge stored in terminal Com-Dis. That is, the drive signal discharge circuit 450 discharges the charge stored in the path through which the drive signal COM is supplied to the print head 20 based on the control signal CNT1.

The control signal CNT2 is input to the reference voltage signal output circuit 460. The reference voltage signal output circuit 460 generates and outputs a reference voltage signal VBS that is supplied to the piezoelectric element 60. FIG. 12 is a diagram showing the configuration of the reference voltage signal output circuit 460. The reference voltage signal output circuit 460 includes a comparator 461, transistors 462 and 463, resistors 464, 465 and 466, and an inverter 467. In the following description, the transistor 462 is described as a PMOS transistor, and the transistor 463 is described as an NMOS transistor.

A reference voltage Vref is supplied to an input terminal (-) of the comparator 461. In addition, an input terminal (+) of the comparator 461 is commonly connected to one terminal of the resistor 464 and one terminal of the resistor 465. An output terminal of the comparator 461 is connected to a gate terminal of a transistor 462. A voltage GVDD is supplied to a source terminal of the transistor 462. A drain terminal of the transistor 462 is commonly connected to the other terminal of the resistor 464, one terminal of the resistor 466, and a terminal VBS-Out from which a reference voltage signal VBS is output. The other terminal of the resistor 466 is connected to a drain terminal of a transistor 463. A control signal CNT2 is input to a gate terminal of the transistor 463 via an inverter 467. A source terminal of the transistor 463 and the other terminal of the resistor 465 are connected to ground.

In the reference voltage signal output circuit 460 configured as described above, when the voltage supplied to the input terminal (+) of the comparator 461 is greater than the reference voltage Vref supplied to the input terminal (-) of the comparator 461, the comparator 461 outputs an H-level signal. At this time, the transistor 462 is controlled to be OFF. Therefore, the voltage GVDD is not supplied to the terminal VBS-Out. On the other hand, when the voltage supplied to the input terminal (+) of the comparator 461 is less than the reference voltage Vref supplied to the input terminal (-) of the comparator 461, the comparator 461 outputs an L-level signal. At this time, the transistor 462 is controlled to be ON. Therefore, the voltage GVDD is supplied to the terminal VBS-Out. That is, the comparator 461 operates so that the voltage value obtained by dividing the reference voltage signal VBS by resistors 464 and 465 is equal to the reference voltage Vref, and the reference voltage signal output circuit 460 generates a reference voltage signal VBS with a constant voltage value based on the voltage GVDD.

When the control signal CNT2 of H level is input to the reference voltage signal output circuit 460 configured as above, the transistor 463 is controlled to be off. Therefore, the path electrically connecting the terminal VBS-Out and the ground via the resistor 466 and the transistor 463 is controlled to be high impedance. As a result, the reference voltage signal VBS of a constant voltage value is output from the terminal VBS-Out. On the other hand, when the control signal CNT2 of L level is input to the reference voltage signal output circuit 460, the transistor 463 is controlled to be on. Therefore, the terminal VBS-Out is electrically connected to the ground via the resistor 466. As a result, the reference voltage signal VBS of the ground potential is output. In other words, when the control signal CNT2 of L level is input to the reference voltage signal output circuit 460, the reference voltage signal output circuit 460 stops outputting the reference voltage signal VBS.

The control signal CNT3 is input to the VHV control signal output circuit 470. The VHV control signal output circuit 470 outputs a VHV control signal VHV_CNT that is supplied to the power supply circuit 52. FIG. 13 is a diagram showing the configuration of the VHV control signal output circuit 470. The VHV control signal output circuit 470 includes a transistor 471. In the following explanation, the transistor 471 will be explained as a PMOS transistor.

A voltage VDD is supplied to the source terminal of transistor 471. A drain terminal of transistor 471 is connected to terminal VHV_CNT-Out. A control signal CNT3 is input to the gate terminal of transistor 471. When an L-level control signal CNT3 is input to the VHV control signal output circuit 470 configured as described above, voltage VDD is supplied to terminal VHV_CNT-Out, and when an H-level control signal CNT3 is input, a signal of ground potential is supplied to terminal VHV_CNT-Out. In other words, the VHV control signal output circuit 470 inverts the logical level of the control signal CNT3, and outputs a signal amplified by voltage VDD as the VHV control signal VHV_CNT.

The VHV control signal VHV_CNT output from the VHV control signal output circuit 470 is input to the power supply circuit 52 as shown in FIG. 9. Then, as will be described in detail later, the power supply circuit 52 controls whether or not to supply the voltage VHV to the drive signal output circuit 51 and the print head 20 based on the input VHV control signal VHV_CNT. In other words, the VHV control signal VHV_CNT is a signal that controls the output of the power supply circuit 52.

The control signal CNT4 is input to the status signal input/output circuit 480. The status signal input/output circuit 480 outputs a status signal BUSY indicating the operating state of the drive signal output circuit 51, and inputs a status signal BUSY output from another component. Here, the other component may be, for example, a different drive signal output circuit 51 in a case where the liquid ejection device 1 has a plurality of drive signal output circuits 51, or may be the control circuit 100. FIG. 14 is a diagram showing the configuration of the status signal input/output circuit 480. The status signal input/output circuit 480 includes a transistor 481 and an inverter 482. In the following description, the transistor 481 is described as a PMOS transistor. The inverter 482 functions as a COMS input terminal of the integrated circuit 500. That is, the status signal input/output circuit 480 outputs a status signal BUSY from a terminal BUSY-Out based on the control signal CNT4 output from the register control circuit 440, and inputs a signal input to the terminal BUSY-Out to the register control circuit 440. In FIG. 14, the control signal CNT4 output from the register control circuit 440 is illustrated as a control signal CNT4-out, and the control signal CNT4 input to the register control circuit 440 is illustrated as a control signal CNT4-in.

A voltage GVDD is supplied to the source terminal of the transistor 481. A drain terminal of the transistor 481 is connected to the input terminal of the inverter 482 and the terminal BUSY-Out. A control signal CNT4-out output from the register control circuit 440 is input to the gate terminal of the transistor 481. A control signal CNT4-in is output from the output terminal of the inverter 482 to be input to the register control circuit 440. When an L-level control signal CNT4 is input to the status signal input/output circuit 480 configured as described above, a voltage GVDD is supplied to the terminal BUSY-Out. In other words, an H-level status signal BUSY is output.

The control signal CNT5 is input to the error signal input/output circuit 490. The error signal input/output circuit 490 outputs an error signal ERR indicating whether or not an abnormality has occurred in the drive signal output circuit 51, and inputs an error signal ERR output from another configuration. Here, the other configuration may be, for example, a different drive signal output circuit 51 in a case where the liquid ejection device 1 has a plurality of drive signal output circuits 51, or may be the control circuit 100. FIG. 15 is a diagram showing the configuration of the error signal input/output circuit 490. The error signal input/output circuit 490 includes a transistor 491 and an inverter 492. In the following description, the transistor 491 is described as a PMOS transistor. The inverter 492 functions as a COMS input terminal of the integrated circuit 500. That is, the error signal input/output circuit 490 outputs an error signal ERR from the terminal ERR-Out based on the control signal CNT5 output from the register control circuit 440, and inputs the signal input to the terminal ERR-Out to the register control circuit 440. In addition, in FIG. 15, the control signal CNT5 output from the register control circuit 440 is illustrated as the control signal CNT5-out, and the control signal CNT5 input to the register control circuit 440 is illustrated as the control signal CNT5-in.

A voltage GVDD is supplied to the source terminal of the transistor 491. A drain terminal of the transistor 491 is connected to the input terminal of the inverter 492 and the terminal ERR-Out. A control signal CNT5-out output from the register control circuit 440 is input to the gate terminal of the transistor 491. A control signal CNT5-in input to the register control circuit 440 is output from the output terminal of the inverter 492. When an L-level control signal CNT5 is input to the error signal input/output circuit 490 configured as described above, a voltage GVDD is supplied to the terminal ERR-Out. In other words, an H-level error signal ERR is output.

As described above, by providing the drive signal output circuit 51 with the status signal input/output circuit 480 and the error signal input/output circuit 490, when the liquid ejection device 1 has a plurality of drive signal output circuits 51, it becomes possible to share error information and operation information between the drive signal output circuits 51. Therefore, when an abnormality occurs in any of the plurality of drive signal output circuits 51, it becomes possible to control the operation of the other drive signal output circuits 51 that are not experiencing an abnormality based on the status information indicating the abnormality.

The control signal CNT6 is input to the amplified control signal generating circuit 502. When the control signal CNT6 is input to the amplified control signal generating circuit 502, the waveform of the drive signal COM generated by the drive signal generating circuit 501 is determined by the control signal CNT6, regardless of the drive data signal DATA. Specifically, the control signal CNT6 may be a signal that causes the drive signal generating circuit 501 to generate a drive signal COM that is constant at a predetermined voltage value, or may be a signal that causes the drive signal generating circuit 501 to generate a drive signal COM that is constant at ground potential.

In the drive signal output circuit 51 configured as described above, operation information input as the drive data signal DATA in synchronization with the clock signal MCK is held in the sequence register 441. The register control unit 443 then executes sequence control of the drive signal output circuit 51 based on the operation information held in the sequence register 441. Thereafter, as the sequence control is executed, information indicating the operation mode associated with the execution of the sequence control is held in the status register 442. The register control circuit 440 controls the output of the control signals CNT1 to CNT6 based on the information indicating the operation mode held in the status register 442. This controls the various signals output from the drive signal output circuit 51.

1.4.2 Configuration and operation of the power supply circuit Next, the configuration and operation of the power supply circuit 52 will be described with reference to Fig. 16. Fig. 16 is a diagram showing the configuration of the power supply circuit 52. As shown in Fig. 16, the power supply circuit 52 has a power supply voltage output circuit 71 that outputs a voltage VHV, a transistor 72 that has a source terminal at one end electrically connected to the power supply voltage output circuit 71 and a drain terminal at the other end electrically connected to the print head 20 and operates based on an input to a gate terminal, an integrated circuit 73 that includes terminals Dc, Gs, Sc, Ld, and Vci, and a step-down circuit 74 that generates a voltage VDD by stepping down the voltage VHV.

The power supply voltage output circuit 71 is supplied with an AC power supply voltage from a commercial AC power supply (not shown). The power supply voltage output circuit 71 converts the supplied AC power supply voltage into a voltage VHV, which is a DC voltage of 42 V, and supplies it to each part of the liquid ejection device 1, including the print head 20 and the drive signal output circuit 51. That is, the power supply voltage output circuit 71 outputs the voltage VHV, which is a power supply voltage. As such a power supply voltage output circuit 71, for example, an AC/DC converter that converts an AC voltage into a DC voltage, such as a flyback circuit, can be used. The voltage VHV output by the power supply voltage output circuit 71 is then supplied to the step-down circuit 74, the source terminal of the transistor 72, and the terminal Dc of the integrated circuit 73.

The step-down circuit 74 generates a DC voltage VDD of, for example, 3.3 V by stepping down the input voltage VHV, and outputs it to various components of the liquid ejection device 1 including the drive signal output circuit 51. Such a step-down circuit 74 is composed of a known DC/DC converter circuit, such as a step-down regulator circuit or a resistive voltage divider circuit.

The integrated circuit 73 includes a control unit 730 and transistors 740 and 750, and is electrically connected to a circuit external to the integrated circuit 73 via terminals Dc, Gs, Sc, Ld, and Vci.

The control unit 730 includes an external Tr control unit 731, an internal Tr control unit 732, and a discharge Tr control unit 733, and operates based on the logic level of the VHV control signal VHV_CNT input from the drive signal output circuit 51 via the terminal Vci.

The external Tr control unit 731 is electrically connected to the terminal Gs. The external Tr control unit 731 outputs a gate signal Sgd to the terminal Gs based on the logic level of the VHV control signal VHV_CNT input to the control unit 730. The internal Tr control unit 732 is electrically connected to the gate terminal of the transistor 740. The internal Tr control unit 732 outputs a gate signal Rgd that controls the operation of the transistor 740 based on the logic level of the VHV control signal VHV_CNT input to the control unit 730. The discharge Tr control unit 733 is electrically connected to the gate terminal of the transistor 750. The internal Tr control unit 732 outputs a gate signal Dgd that controls the operation of the transistor 750 based on the logic level of the VHV control signal VHV_CNT input to the control unit 730.

The transistor 740 is a PMOS transistor, and one end of the transistor 740 is electrically connected to the terminal Dc at its source terminal, the other end of the transistor 740 is electrically connected to the terminal Sc at its drain terminal, and the gate terminal of the transistor 740 is electrically connected to the internal Tr control unit 732 of the control unit 730. The transistor 740 operates based on the gate signal Rgd output by the internal Tr control unit 732. As shown in FIG. 16, the terminal Dc is electrically connected to the power supply voltage output circuit 71 provided outside the integrated circuit 73 and the source terminal of the transistor 72, and the terminal Sc is electrically connected to the print head 20 (not shown in FIG. 16) to which the voltage VHV is supplied from the power supply circuit 52. The transistor 740 operates based on the gate signal Rgd to switch whether or not the voltage VHV supplied from the power supply voltage output circuit 71 to the source terminal is output from the drain terminal. That is, the transistor 740 switches whether or not to supply the voltage VHV to the print head 20 and the drive signal output circuit 51 based on the gate signal Rgd.

The transistor 750 is an NMOS transistor, and one end, or drain terminal, is electrically connected to the terminal Ld, and the other end, or source terminal, is supplied with a ground potential. The gate terminal is electrically connected to the discharge Tr control unit 733 of the control unit 730. The transistor 750 operates based on a gate signal Dgd output by the discharge Tr control unit 733. Here, the terminal Ld is electrically connected to the print head 20 (not shown in FIG. 16) to which the voltage VHV is supplied from the power supply circuit 52. The transistor 750 operates based on the gate signal Dgd, and releases the charge stored in the propagation wiring a, b, and c shown in FIG. 9, which is a propagation path along which the voltage VHV supplied to the print head 20 is propagated.

The transistor 72 is a PMOS transistor, and the source terminal, which is one end, is electrically connected to the power supply voltage output circuit 71, the drain terminal, which is the other end, is electrically connected to the print head 20 and the drive signal output circuit 51, and the gate terminal is electrically connected to the terminal Gs of the integrated circuit 73. The transistor 72 operates based on a gate signal Sgd input to the gate terminal from the external Tr control unit 731 of the integrated circuit 73 via the terminal Gs. That is, the transistor 72 is connected in parallel with the transistor 740 provided inside the integrated circuit 73. The transistor 72 switches whether or not to output the voltage VHV supplied to the source terminal from the drain terminal. That is, the transistor 72 functions as a switch circuit that switches whether or not to supply the voltage VHV to the print head 20 and the drive signal output circuit 51 based on the gate signal Sgd.

As described above, the power supply circuit 52 in this embodiment includes the power supply voltage output circuit 71 that outputs the voltage VHV that is the power supply voltage, the transistor 72 that has a source terminal that is one end electrically connected to the power supply voltage output circuit 71 and a drain terminal that is the other end electrically connected to the print head 20 and the drive signal output circuit 51 and operates based on the gate signal Sgd input to the gate terminal, the terminal Dc that is electrically connected to the power supply voltage output circuit 71, and the print head 20.
0 and the drive signal output circuit 51, and a terminal Gs electrically connected to the gate terminal of the transistor 72, and the integrated circuit 73 includes a transistor 740 having a source terminal electrically connected to the terminal Dc and a drain terminal electrically connected to the terminal Sc and operating based on an input to the gate terminal, an external Tr control unit 731 electrically connected to the terminal Gs and controlling the operation of the transistor 72 provided outside the integrated circuit 73, and an internal Tr control unit 732 electrically connected to the gate terminal of the transistor 740 and controlling the operation of the transistor 740. In other words, the power supply circuit 52 includes a transistor 72 that switches whether or not to supply a voltage VHV as a power supply voltage to various components including the print head 20 and the drive signal output circuit 51, and a transistor 740 that is connected in parallel with the transistor 72 and switches whether or not to supply a voltage VHV as a power supply voltage to various components including the print head 20 and the drive signal output circuit 51 inside the integrated circuit 73.

As a result, at least one of the transistors 72 and 740 can reduce the inrush current, while at least the other of the transistors 72 and 740 can supply the voltage VHV as a power supply voltage to the print head 20 and the drive signal output circuit 51 during steady-state operation. As a result, the inrush current reduction circuit, which was previously configured with discrete components, can be configured as an integrated circuit 73, thereby realizing a miniaturized power supply circuit 52. Furthermore, by controlling the supply of the voltage VHV as a power supply voltage to the print head 20 and the drive signal output circuit 51 with the discrete transistor 72, even if the amount of output current changes due to a change in the number of nozzles in the print head 20 or a change in the waveform of the drive signal COM output by the drive signal output circuit 51, the specification change can be easily accommodated, and a highly versatile power supply circuit 52 can be provided.

Here, the operation of the power supply circuit 52 in this embodiment will be described with reference to FIG. 17. FIG. 17 is a diagram for explaining the operation when starting to supply the voltage VHV to the print head 20 and the drive signal output circuit 51.

As shown in FIG. 17, before time t0, the power supply voltage output circuit 71 outputs the voltage VHV. In this case, the external Tr control unit 731 and the internal Tr control unit 732 control the transistors 72 and 740 to be non-conductive. That is, the power supply circuit 52 does not supply the voltage VHV to the print head 20 and the drive signal output circuit 51. In addition, in the period before time t0, the discharge Tr control unit 733 controls the transistor 750 to be conductive. As a result, a signal of ground potential is supplied to the print head 20 and the drive signal output circuit 51. That is, a signal of an unintended potential caused by a leakage current generated in various circuit elements including the transistor 72 is not supplied to the print head 20 and the drive signal output circuit 51. This reduces the risk of malfunction of the print head 20 and the drive signal output circuit 51.

Then, at time t0, the drive signal output circuit 51 outputs an H-level VHV control signal VHV_CNT to the integrated circuit 73 in the power supply circuit 52. When the H-level VHV control signal VHV_CNT is supplied to the control unit 730 in the integrated circuit 73, the internal Tr control unit 732 generates a pulse signal gate signal Rgd and supplies it to the gate terminal of the transistor 740, and the discharge Tr control unit 733 controls the transistor 750 to be non-conductive. In other words, the internal Tr control unit 732 controls the transistor 740 to be intermittently conductive. This causes the potential of the voltage VHVa to gradually increase, as shown in FIG. 17.

As described above, at time t0, the internal Tr control unit 732 generates the gate signal Rgd, which is a pulse signal, and supplies it to the transistor 740, thereby reducing the risk of the potential of the voltage VHVa increasing abruptly. As a result, it is possible to reduce the inrush current that occurs when the supply of the voltage VHV to the print head 20 and the drive signal output circuit 51 is started. In other words, the risk of a large inrush current occurring is reduced. Here, the pulse width and duty of the gate signal Rgd, which is a pulse signal output by the internal Tr control unit 732, may be changeable according to the potential of the voltage VHV, the load capacitance, the magnitude of the inrush current, and the temperature of the transistor 740.

Then, at time t1, when a predetermined time tb has elapsed after the H-level VHV control signal VHV_CNT is supplied to the control unit 730 of the integrated circuit 73, the external Tr control unit 731 outputs a gate signal Sgd that makes the transistor 72 conductive. As a result, the voltage VHV is supplied to the print head 20 and the drive signal output circuit 51 as the voltage VHVa via the transistor 72. Here, in the period from time t0 to time t1, the transistor 740 is driven intermittently, so the potential on the drain side of the transistor 72 gradually increases. Therefore, the difference between the potential of the voltage VHV supplied to the source terminal side of the transistor 72 at time t1 and the potential of the voltage VHVa output from the drain terminal side of the transistor 72 is small, and therefore, even if the transistor 72 is controlled to be conductive at time t1, the risk of a large inrush current occurring is reduced.

Then, at time t2, when a predetermined time tc has elapsed after the transistor 72 is controlled to be conductive, the internal Tr controls the transistor 740 to be non-conductive. As a result, the voltage VHV is supplied to the print head 20 and the drive signal output circuit 51 via the transistor 72.

In other words, in the power supply circuit 52 of this embodiment, when the power supply voltage output circuit 71 starts outputting the voltage VHV, the external Tr control unit 731 controls the transistor 72 to be non-conductive, and the internal Tr control unit 732 controls the transistor 740 to be conductive. This makes it possible to gradually increase the potential of the voltage VHV supplied to the print head 20 and the drive signal output circuit 51, reducing the risk of a large inrush current. Then, at a subsequent time t1, the external Tr control unit 731 controls the transistor 72 to be conductive, so that the voltage VHV is supplied to the print head 20 and the drive signal output circuit 51 via the transistor 72.

In this embodiment, it has been described that in the period from time t0 to time t1, the external Tr control unit 731 controls the transistor 72 to be non-conductive, and the internal Tr control unit 732 controls the transistor 740 to be conductive, and at time t1, the external Tr control unit 731 controls the transistor 72 to be conductive; however, in the period from time t0 to time t1, the external Tr control unit 731 may control the transistor 72 to be conductive, and the internal Tr control unit 732 may control the transistor 740 to be non-conductive, and at time t1, the internal Tr control unit 732 may control the transistor 740 to be conductive.

However, as described above, the inrush current is reduced by pulse driving the transistor 72 or the transistor 740 using a pulse signal. That is, the inrush current generated when the voltage VHV is supplied to the print head 20 and the drive signal output circuit 51 can be dealt with arbitrarily by adjusting the pulse width and duty of the pulse signal that drives the transistor 72 or the transistor 740. In contrast, in a steady state, the current generated by supplying the voltage VHV to the print head 20 and the drive signal output circuit 51 is determined by the number of nozzles the print head 20 has and the current caused by the drive signal COM output by the drive signal output circuit 51.

Taking this into consideration, the inrush current that occurs when the voltage VHV is supplied is reduced by the transistor 740 provided inside the integrated circuit 73, and the print head 2 is
By supplying the voltage VHV supplied to the input terminal 50 and the drive signal output circuit 51 via a transistor 72, it is possible to provide a power supply circuit 52 with improved versatility without increasing the size of the power supply circuit 52.

Here, the transistor 72 is an example of a first transistor, the transistor 740 is an example of a second transistor, and the transistor 750 is an example of a discharge circuit. The gate terminal of the transistor 72 is an example of a first control terminal, and the gate terminal of the transistor 740 is an example of a second control terminal. The external Tr control unit 731 that controls the operation of the transistor 72 is an example of a first transistor control circuit, and the internal Tr control unit 732 that controls the operation of the transistor 740 is an example of a second transistor control circuit. The terminal Dc is an example of a first terminal, the terminal Sc is an example of a second terminal, the terminal Gs is an example of a third terminal, and the terminal Ld is an example of a fourth terminal. The integrated circuit 73 that includes the transistor 740, the external Tr control unit 731, the internal Tr control unit 732, and the transistor 750, and is electrically connected to the outside via the terminals Dc, Sc, Gs, and Ld is an example of an integrated circuit device.

1.5 Effects As described above, the liquid ejection device 1 and power supply circuit 52 in this embodiment include the power supply voltage output circuit 71 that outputs the voltage VHV that is the power supply voltage, the transistor 72 having a source terminal at one end electrically connected to the power supply voltage output circuit 71 and a drain terminal at the other end electrically connected to the print head 20 and the drive signal output circuit 51 and operating based on a gate signal Sgd input to the gate terminal, a terminal Dc electrically connected to the power supply voltage output circuit 71, a terminal Sc electrically connected to the print head 20 and the drive signal output circuit 51, and the transistor The integrated circuit 73 includes a transistor 740 having a source terminal electrically connected to a terminal Dc and a drain terminal electrically connected to a terminal Sc and operating based on an input from the gate terminal, an external Tr control unit 731 electrically connected to the terminal Gs and controlling the operation of the transistor 72 provided outside the integrated circuit 73, and an internal Tr control unit 732 electrically connected to the gate terminal of the transistor 740 and controlling the operation of the transistor 740. In other words, the power supply circuit 52 includes a transistor 72 that switches whether or not to supply a voltage VHV as a power supply voltage to various components including the print head 20 and the drive signal output circuit 51, and a transistor 740 that is connected in parallel with the transistor 72 and switches whether or not to supply a voltage VHV as a power supply voltage to various components including the print head 20 and the drive signal output circuit 51 inside the integrated circuit 73.

As a result, at least one of the transistors 72 and 740 can reduce the inrush current, while at least the other of the transistors 72 and 740 can supply the voltage VHV as a power supply voltage to the print head 20 and the drive signal output circuit 51 during steady-state operation. As a result, the inrush current reduction circuit, which was previously configured with discrete components, can be configured as an integrated circuit 73, thereby realizing a miniaturized power supply circuit 52. Furthermore, by controlling the supply of the voltage VHV as a power supply voltage to the print head 20 and the drive signal output circuit 51 with the discrete transistor 72, even if the amount of output current changes due to a change in the number of nozzles in the print head 20 or a change in the waveform of the drive signal COM output by the drive signal output circuit 51, the specification change can be easily accommodated, and a highly versatile power supply circuit 52 can be provided.

2. Second embodiment A liquid ejection device 1 and a power supply circuit 52 in the second embodiment will be described. In describing the liquid ejection device 1 and the power supply circuit 52 in the second embodiment, the same reference numerals are used for the same configurations as those in the liquid ejection device 1 and the power supply circuit 52 in the first embodiment, and the description thereof will be omitted or simplified.

Figure 18 is a diagram showing the configuration of the power supply circuit 52 in the second embodiment. As shown in Figure 18, the power supply circuit 52 in the second embodiment differs from the liquid ejection device 1 and power supply circuit 52 in the first embodiment in that the integrated circuit 73 includes a voltage detection circuit 760 that detects the voltage value of the voltage VHVa.

The voltage detection circuit 760 detects the voltage value of the voltage VHVa via the terminal Vdi of the integrated circuit 73. When the voltage value of the voltage VHVa exceeds a predetermined threshold voltage Vth, the voltage detection circuit 760 outputs a voltage detection signal Vdet to the control unit 730. When the voltage detection signal Vdet indicating that the voltage VHVa has exceeded the threshold voltage Vth is input to the control unit 730, the external Tr control unit 731 outputs a gate signal Sgd to control the transistor 72 to be conductive.

Figure 19 is a diagram for explaining the operation when starting to supply voltage VHV to the print head 20 and the drive signal output circuit 51 in the second embodiment.

As shown in FIG. 19, in the power supply circuit 52 in the second embodiment, similar to the power supply circuit 52 in the first embodiment, before time t0, the power supply voltage output circuit 71 outputs the voltage VHV, the external Tr control unit 731 and the internal Tr control unit 732 control the transistors 72 and 740 to be non-conductive, and the discharge Tr control unit 733 controls the transistor 750 to be conductive. As a result, a signal of ground potential is supplied to the print head 20 and the drive signal output circuit 51.

Then, at time t0, an H-level VHV control signal VHV_CNT is supplied to the integrated circuit 73 of the power supply circuit 52, causing the internal Tr control unit 732 in the control unit 730 of the integrated circuit 73 to generate a pulse signal, a gate signal Rgd, and supply it to the gate terminal of the transistor 740, while the discharge Tr control unit 733 controls the transistor 750 to be non-conductive. This causes the potential of the voltage VHVa to gradually increase.

Then, at time t1a when the voltage detection circuit 760 of the integrated circuit 73 detects that the potential of the voltage VHVa has exceeded the threshold voltage Vth, the external Tr control unit 731 outputs a gate signal Sgd that turns on the transistor 72. As a result, the voltage VHV is supplied to the print head 20 and the drive signal output circuit 51 as the voltage VHVa via the transistor 72.

After that, at time t2a when a predetermined time td has elapsed, the internal Tr control unit 732 controls the transistor 740 to be non-conductive. As a result, the voltage VHV is supplied to the print head 20 and the drive signal output circuit 51 via the transistor 72.

In other words, in the power supply circuit 52 in the first embodiment, the external Tr control unit 731 controls the conduction/non-conduction of the transistor 72 based on the elapsed time, whereas in the power supply circuit 52 in the second embodiment, the external Tr control unit 731 controls the conduction/non-conduction of the transistor 72 based on the potential of the voltage VHVa output from the transistor 72. That is, in the power supply circuit 52 in the second embodiment, the integrated circuit 73 includes a voltage detection circuit 760 that detects the voltage value of the voltage VHV, and when the power supply voltage output circuit 71 starts to output the voltage VHV, the external Tr control unit 731 controls the transistor 72 to be non-conductive, and the internal Tr control unit 732 controls the transistor 740 to be conductive. Then, when the voltage detection circuit 760 detects that the voltage value of the voltage VHV is greater than the threshold voltage Vth, which is a predetermined value, the external Tr control unit 731 controls the transistor 72 to be conductive.

This makes it possible to control the operation of the integrated circuit 73 according to the amount of charge actually stored by the voltage VHVa, thereby further reducing with greater precision the risk of large inrush currents occurring in the print head 20 and the drive signal output circuit 51.

In other words, the liquid ejection device 1 and power supply circuit 52 in the second embodiment can achieve the same effects as the first embodiment while further reducing the risk of a large inrush current.

Here, the voltage detection circuit 760 is an example of a detection circuit.

3. Third embodiment A liquid ejection device 1 and a power supply circuit 52 in the third embodiment will be described. In describing the liquid ejection device 1 and the power supply circuit 52 in the third embodiment, the same reference numerals are used for configurations similar to those of the liquid ejection device 1 and the power supply circuit 52 in the first and second embodiments, and descriptions thereof will be omitted or simplified.

Figure 20 is a diagram showing the configuration of the power supply circuit 52 in the third embodiment. As shown in Figure 20, the power supply circuit 52 in the third embodiment differs from the liquid ejection device 1 and power supply circuit 52 in the first and second embodiments in that it has a terminal Mi to which a mode signal MODE for switching the operating mode of the integrated circuit 73 is input.

The mode signal MODE input to the integrated circuit 73 is a signal that switches the operation mode of the integrated circuit 73, and is output, for example, by the control circuit 100 shown in FIG. 2. Based on the input mode signal MODE, the integrated circuit 73 may change the predetermined time tb during which the internal Tr control unit 732 shown in FIG. 17 generates the gate signal Rgd, which is a pulse signal, and supplies it to the transistor 740, and may also change the potential of the threshold voltage Vth shown in FIG. 19 based on the input mode signal MODE.

In other words, the control conditions under which the external Tr control unit 731 controls the operation of the transistor 72 in the first operating mode defined by the mode signal MODE are different from the control conditions under which the external Tr control unit 731 controls the operation of the transistor 72 in the second operating mode, and the control conditions under which the internal Tr control unit 732 controls the operation of the transistor 740 in the first operating mode defined by the mode signal MODE are different from the control conditions under which the internal Tr control unit 732 controls the operation of the transistor 740 in the second operating mode.

The capacitance component of the configuration to which the voltage VHV is supplied varies depending on the number of nozzles of the print head 20 to which the voltage VHV is supplied and the circuit configuration of the drive signal output circuit 51. Therefore, the time required for the voltage VHV to store charge after the supply of the voltage VHV begins also varies. In addition, the voltage value of the voltage VHV also varies depending on the conditions of the device in which it is used. Therefore, if the period Tb and the value of the threshold voltage Vth are uniquely defined, the versatility of the power supply circuit 52 decreases.

In response to such problems, the integrated circuit 73 has multiple operating modes that can be switched based on the mode signal MODE, so that the liquid ejection device 1 and power supply circuit 52 in the third embodiment can further increase the versatility of the power supply circuit 52. In other words, the liquid ejection device 1 and power supply circuit 52 in the third embodiment can achieve the same effects as the liquid ejection device 1 and power supply circuit 52 shown in the first and second embodiments, and can further increase the versatility of the power supply circuit 52.

Although the embodiments have been described above, the present invention is not limited to these embodiments, and can be implemented in various forms without departing from the spirit of the invention. For example, the above embodiments can be combined as appropriate.

The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effect). The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments, or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

The following can be derived from the above-described embodiment and variant examples.

One aspect of the liquid ejection device is
A liquid ejection device that ejects liquid,
A drive unit that ejects liquid when driven;
a power supply circuit for supplying a power supply voltage to the driving unit;
Equipped with
The power supply circuit includes:
a power supply voltage output circuit that outputs the power supply voltage;
a first transistor having one end electrically connected to the power supply voltage output circuit and the other end electrically connected to the drive unit, the first transistor being operated based on an input to a first control terminal;
an integrated circuit device including a first terminal electrically connected to the power supply voltage output circuit, a second terminal electrically connected to the drive unit, and a third terminal electrically connected to a control terminal of the first transistor;
having
The integrated circuit device comprises:
a second transistor having one end electrically connected to the first terminal and the other end electrically connected to the second terminal, and operating based on an input to a second control terminal;
a first transistor control circuit electrically connected to the third terminal and configured to control an operation of the first transistor;
a second transistor control circuit electrically connected to the second control terminal and configured to control an operation of the second transistor;
Includes.

According to this liquid ejection device, when a power supply voltage is supplied to the drive unit in the power supply circuit, a first transistor and a second transistor are provided in parallel in the path along which the power supply voltage propagates, and the second transistor is provided inside a single integrated circuit along with a first transistor control circuit that controls the operation of the first transistor and a second transistor control circuit that controls the operation of the second transistor, thereby reducing the number of discrete components that make up the power supply circuit. This makes it possible to reduce the size of the power supply circuit while reducing the inrush current.

Furthermore, with this liquid ejection device, the first transistor provided in the path along which the power supply voltage propagates in the power supply circuit is configured as a discrete component, so that even if the specifications of the drive unit are changed, the first transistor can be easily changed in accordance with the current generated based on the power supply voltage. This makes it possible to provide a liquid ejection device equipped with a versatile power supply circuit that reduces inrush current.

In one aspect of the liquid ejection device,
When the power supply voltage output circuit starts outputting the power supply voltage,
the first transistor control circuit controls the first transistor to be non-conductive, and the second transistor control circuit controls the second transistor to be conductive;
The first transistor control circuit may then control the first transistor to be conductive.

According to this liquid ejection device, during steady state operation when there is a risk of the current and voltage values changing significantly due to changes in specifications, the first transistor supplies the power supply voltage to the drive unit, so that the power supply circuit can use a first transistor with optimal characteristics for the liquid ejection device and the drive unit according to the usage, without increasing the size of the power supply circuit. In other words, the inrush current can be reduced, and the versatility of the power supply circuit can be further increased without hindering the miniaturization of the power supply circuit.

In one aspect of the liquid ejection device,
the integrated circuit device includes a detection circuit that detects a voltage value of the power supply voltage;
When the power supply voltage output circuit starts outputting the power supply voltage,
the first transistor control circuit controls the first transistor to be non-conductive, and the second transistor control circuit controls the second transistor to be conductive;
When the detection circuit detects that the voltage value is greater than a predetermined value, the first transistor control circuit may control the first transistor to be conductive.

This liquid ejection device can switch the supply of power supply voltage through the first transistor at the optimal timing according to the state of the drive unit to which the power supply voltage is supplied.

In one aspect of the liquid ejection device,
the integrated circuit device has a first operating mode and a second operating mode;
a control condition under which the first transistor control circuit controls the operation of the first transistor in the first operation mode is different from a control condition under which the first transistor control circuit controls the operation of the first transistor in the second operation mode;
The control conditions under which the second transistor control circuit controls the operation of the second transistor in the first operating mode may be different from the control conditions under which the second transistor control circuit controls the operation of the second transistor in the second operating mode.

In this liquid ejection device, the integrated circuit device of the power supply circuit has multiple operating modes, including a first operating mode and a second operating mode, which does not hinder the miniaturization of the power supply circuit and further enhances versatility.

In one aspect of the liquid ejection device,
The integrated circuit device comprises:
A fourth terminal electrically connected to the driving unit;
a discharge circuit electrically connected to the fourth terminal, the discharge circuit discharging electric charges from a propagation path along which the power supply voltage propagates to the drive unit;
may have the following structure:

This liquid ejection device is provided with a discharge circuit that releases electric charge from the propagation path of the power supply voltage, thereby reducing the risk of unintended voltage being supplied to the liquid ejection device or the drive unit due to residual electric charge generated by the power supply voltage when the operation of the power supply voltage is stopped in the liquid ejection device or the drive unit. Furthermore, by providing the discharge circuit inside the integrated circuit device, it is possible to further miniaturize the power supply circuit.

In one aspect of the liquid ejection device,
The driving section may be a liquid ejection head including a piezoelectric element, and ejecting liquid by being driven by the piezoelectric element.

The amount of current for capacitive loads such as piezoelectric elements varies greatly depending on the number of piezoelectric elements. Therefore, in the case of a liquid ejection head whose drive unit has piezoelectric elements, it is necessary to meet various required specifications depending on the number of piezoelectric elements that the drive unit has. In response to such problems, this liquid ejection device can provide a highly versatile power supply circuit without hindering the miniaturization of the power supply circuit, so that the drive unit can reduce the risk of malfunction due to inrush current without increasing the size, even in liquid ejection heads that eject liquid by being driven by piezoelectric elements.

One aspect of the power supply circuit is
A power supply circuit for supplying a power supply voltage to a drive unit,
a power supply voltage output circuit that outputs the power supply voltage;
a first transistor having one end electrically connected to the power supply voltage output circuit and the other end electrically connected to the drive unit, the first transistor being operated based on an input to a first control terminal;
an integrated circuit device including a first terminal electrically connected to the power supply voltage output circuit, a second terminal electrically connected to the drive unit, and a third terminal electrically connected to a control terminal of the first transistor;
having
The integrated circuit device comprises:
a second transistor having one end electrically connected to the first terminal and the other end electrically connected to the second terminal, and operating based on an input to a second control terminal;
a first transistor control circuit electrically connected to the third terminal and configured to control an operation of the first transistor;
a second transistor control circuit electrically connected to the second control terminal and configured to control an operation of the second transistor;
Includes.

According to this power supply circuit, when a power supply voltage is supplied to the drive unit, a first transistor and a second transistor are provided in parallel in the path along which the power supply voltage propagates, and the second transistor is provided inside a single integrated circuit along with a first transistor control circuit that controls the operation of the first transistor and a second transistor control circuit that controls the operation of the second transistor, thereby reducing the number of discrete components that make up the power supply circuit. This makes it possible to reduce the size while reducing the inrush current.

Furthermore, with this power supply circuit, the first transistor provided in the path along which the power supply voltage propagates is configured as a discrete component, so that even if the specifications of the drive unit are changed, the first transistor can be easily changed in accordance with the current generated based on the power supply voltage. This makes it possible to provide a highly versatile power supply circuit while reducing inrush current.

REFERENCE SIGNS LIST 1...liquid ejection device, 2...moving body, 3...moving mechanism, 4...transport mechanism, 20...print head, 24...carriage, 31...carriage motor, 32...carriage guide shaft, 33...timing belt, 35...carriage motor driver, 40...platen, 41...transport motor, 42...transport roller, 45...transport motor driver, 51...drive signal output circuit, 52...power supply circuit, 60...piezoelectric element, 71...power supply voltage output circuit, 72...transistor, 73...integrated circuit, 74...step-down circuit, 80, 81...fuse, 91...oscillating circuit, 100...control circuit, 190...cable, 200...drive Signal selection control circuit, 210... selection control circuit, 212... shift register, 214... latch circuit, 216... decoder, 230... selection circuit, 232... inverter, 234... transfer gate, 235, 236... transistor, 400... internal voltage generation circuit, 410... oscillation circuit, 420... clock selection circuit, 430... abnormality detection circuit, 431... oscillation abnormality detection unit, 432... operation abnormality detection unit, 433... power supply voltage abnormality detection unit, 440... register control circuit, 441... sequence register, 442... status register, 443... register control unit, 450... drive signal discharge circuit, 451 ...resistor, 452...transistor, 453...inverter, 460...reference voltage signal output circuit, 461...comparator, 462, 463...transistor, 464, 465, 466...resistor, 467...inverter, 470...VHV control signal output circuit, 471...transistor, 480...status signal input/output circuit, 481...transistor, 482...inverter, 490...error signal input/output circuit, 491...transistor, 492...inverter, 500...integrated circuit, 501...drive signal generating circuit, 502...amplification control signal generating circuit, 510...DAC interface, 520...DA C section, 530...modulation section, 540...gate driving section, 550...amplification circuit, 551, 552...transistor, 560...demodulation circuit, 561...coil, 562...capacitor, 570...feedback circuit, 571, 572, 576...resistor, 600...ejection section, 601...piezoelectric body, 611, 612...electrode, 621...diaphragm, 631...cavity, 632...nozzle plate, 641...reservoir, 651...nozzle, 661...supply port, 730...control section, 731...external Tr control section, 732...internal Tr control section, 733...discharge Tr control section, 740, 750...transistor, 760...voltage detection circuit, P...medium

Claims (7)

A liquid ejection device that ejects liquid,
A drive unit that ejects liquid when driven;
a power supply circuit for supplying a power supply voltage to the driving unit;
Equipped with
The power supply circuit includes:
a power supply voltage output circuit that outputs the power supply voltage;
a first transistor having one end electrically connected to the power supply voltage output circuit and the other end electrically connected to the drive unit, the first transistor being operated based on an input to a first control terminal;
an integrated circuit device including a first terminal electrically connected to the power supply voltage output circuit, a second terminal electrically connected to the drive unit, and a third terminal electrically connected to a control terminal of the first transistor;
having
The integrated circuit device comprises:
a second transistor having one end electrically connected to the first terminal and the other end electrically connected to the second terminal, and operating based on an input to a second control terminal;
a first transistor control circuit electrically connected to the third terminal and configured to control an operation of the first transistor;
a second transistor control circuit electrically connected to the second control terminal and configured to control an operation of the second transistor;
Including,
A liquid ejection device comprising: When the power supply voltage output circuit starts outputting the power supply voltage,
the first transistor control circuit controls the first transistor to be non-conductive, and the second transistor control circuit controls the second transistor to be conductive;
Then, the first transistor control circuit controls the first transistor to be conductive.
The liquid ejection device according to claim 1 . the integrated circuit device includes a detection circuit that detects a voltage value of the power supply voltage;
When the power supply voltage output circuit starts outputting the power supply voltage,
the first transistor control circuit controls the first transistor to be non-conductive, and the second transistor control circuit controls the second transistor to be conductive;
When the detection circuit detects that the voltage value is greater than a predetermined value, the first transistor control circuit controls the first transistor to be conductive.
The liquid ejection device according to claim 1 . the integrated circuit device has a first operating mode and a second operating mode;
a control condition under which the first transistor control circuit controls the operation of the first transistor in the first operation mode is different from a control condition under which the first transistor control circuit controls the operation of the first transistor in the second operation mode;
a control condition under which the second transistor control circuit controls the operation of the second transistor in the first operation mode is different from a control condition under which the second transistor control circuit controls the operation of the second transistor in the second operation mode.
The liquid ejection device according to claim 1 . The integrated circuit device comprises:
A fourth terminal electrically connected to the driving unit;
a discharge circuit electrically connected to the fourth terminal, the discharge circuit discharging electric charges from a propagation path along which the power supply voltage propagates to the drive unit;
having
5. The liquid ejection device according to claim 1, wherein the liquid ejection device is a liquid ejection device. the driving unit is a liquid ejection head including a piezoelectric element and ejecting liquid by being driven by the piezoelectric element;
6. The liquid ejection device according to claim 1, A power supply circuit for supplying a power supply voltage to a drive unit,
a power supply voltage output circuit that outputs the power supply voltage;
a first transistor having one end electrically connected to the power supply voltage output circuit and the other end electrically connected to the drive unit, the first transistor being operated based on an input to a first control terminal;
an integrated circuit device including a first terminal electrically connected to the power supply voltage output circuit, a second terminal electrically connected to the drive unit, and a third terminal electrically connected to a control terminal of the first transistor;
having
The integrated circuit device comprises:
a second transistor having one end electrically connected to the first terminal and the other end electrically connected to the second terminal, and operating based on an input to a second control terminal;
a first transistor control circuit electrically connected to the third terminal and configured to control an operation of the first transistor;
a second transistor control circuit electrically connected to the second control terminal and configured to control an operation of the second transistor;
Including,
A power supply circuit comprising:

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