JP7375553B2 - power converter - Google Patents

Description

The present invention relates to a power conversion device that supplies at least one of active power and reactive power.

In order to maintain the quality of power systems, power converters that compensate for reactive power are used. It is desired to increase the capacity of such power conversion devices. Practical use of modular multilevel cascade converters is underway as a power conversion method that can achieve large capacity while reducing size by using self-extinguishing semiconductor switching elements (for example, patented Literatures 1 and 2 and Non-patent Literatures 1 and 2).

Japanese Patent Application Publication No. 2012-44839 Japanese Patent Application Publication No. 2017-143626

H. H. Akagi, "(Multilevel Converters: Fundamental Circuits and Systems)", (USA), Proceedings of the IEEE, pp2048-2065, V olume:105, Issue:11, Nov. 2017 T. T. Tanaka, “(Asymmetrical Reactive Power Capability of Modular Multilevel Cascade Converter (MMCC) based STATCOMs for Offshore Wind Farm), (USA), IEEE Transaction on Power Electronics, pp5147- 5164, Volume: 34, Number: 6, June. 2019

An object of the present invention is to provide a power conversion device that can continue to operate stably even if the power system fails and the system voltage becomes three-phase unbalanced.

In order to achieve the above object, a power conversion device according to one aspect of the present invention includes a plurality of legs each having a first arm and a second arm connected in series, and a plurality of legs provided on each of the plurality of legs. a first connecting portion in which the ends of one arm that are not connected to the second arm are connected to each other; and a first connecting portion in which the ends of one arm that are not connected to the second arm are connected to each other; and A second connecting portion whose ends not connected to the first arm are connected to each other, and a control device that controls the plurality of legs, and the first arm includes two semiconductor switches connected in series. and a first power inverter circuit cell having a power storage element connected in parallel to the two semiconductor switches, and a first coil connected in series to the first power inverter circuit cell; , a second power inverter circuit cell having two semiconductor switches connected in series and a storage element connected in parallel to the two semiconductor switches; and a second coil connected in series to the second power inverter circuit cell. and the control device adjusts the same voltage component included in each of the first voltage of the first connection portion and the second voltage of the second connection portion to generate voltage between each of the plurality of legs. It has a power control section that controls the first power flowing in and out.

According to one aspect of the present invention, even if the power system fails and the system voltage becomes three-phase unbalanced, stable operation can be continued.

1 is a circuit block diagram showing a schematic configuration of a power conversion device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a schematic configuration of a power conversion circuit cell provided in each of a plurality of legs included in the power conversion device according to the first embodiment of the present invention. 1 is a simple block diagram showing a schematic configuration of a power conversion device according to a first embodiment of the present invention. 1 is a block diagram showing a schematic configuration of a control device included in a power conversion device according to a first embodiment of the present invention. FIG. FIG. 2 is a block diagram showing a schematic configuration of a voltage suppressor provided in a control device included in a power conversion device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of an arm voltage command value generation section provided in a control device included in a power conversion device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of a control device included in a power conversion device according to a second embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of a voltage suppressor provided in a control device included in a power conversion device according to a second embodiment of the present invention. FIG. 3 is a block diagram showing a schematic configuration of an arm voltage command value generation section provided in a control device included in a power conversion device according to a second embodiment of the present invention. FIG. 2 is a diagram illustrating the effects of the power conversion device according to the first embodiment of the present invention, and is a graph showing a simulation result of the maximum value of reactive power at the time of a system failure. It is a figure explaining the effect of the power conversion device by a 2nd embodiment of the present invention, and is a graph showing the simulation result of the maximum value of reactive power at the time of a grid failure. It is a graph which shows the simulation result of the maximum value of reactive power at the time of a system failure in a reference example. FIG. 7 is a circuit diagram showing a schematic configuration of a power conversion circuit cell provided in each of a plurality of legs included in a power conversion device according to a third embodiment of the present invention.

[First embodiment]
A power conversion device according to a first embodiment of the present invention will be described using FIGS. 1 to 6. The power conversion device according to the present embodiment is of a double star bridge cell type (DSBC) assuming the use of a self-excited static var compensator (STATCOM) for power grids. A three-phase modular multilevel converter (hereinafter, "modular multilevel converter" may be abbreviated as "MMCC") will be described as an example.

(power control system)
A power control system using a power converter according to this embodiment will be described using FIG. 1. FIG. 1 is a circuit block diagram showing a schematic configuration of a power control system PS in which a power conversion device 1 according to the present embodiment is used.

As shown in FIG. 1, the power control system PS includes a three-phase power system 2, a load device (not shown) that operates using power supplied from the three-phase power system 2, and a load device (not shown) that is connected to the three-phase power system 2. The power converter 1 is equipped with a power converter 1 that is connected to the power converter 1. The three-phase power system 2 includes a three-phase AC power supply 21 that generates three-phase AC power, and a cable 22 to which the power generated by the three-phase AC power supply 21 is supplied. The three-phase AC power supply 21 includes a U-phase AC power supply 211 that supplies U-phase AC power, a V-phase AC power supply 212 that supplies V-phase AC power, and a W-phase AC power supply 213 that supplies W-phase AC power. have. The cables 22 include a U-phase cable 221 to which U-phase AC power generated by a U-phase AC power supply is supplied, and a V-phase cable 222 to which V-phase AC power generated by a V-phase AC power supply 212 is supplied. , and a W-phase cable 223 to which W-phase AC power generated by the W-phase AC power supply 213 is supplied.

(Power converter)
Next, the configuration of the power conversion device provided in the power control system PS will be described using FIG. 1.
As shown in FIG. 1, the power converter 1 according to the present embodiment includes a main circuit section 3 connected to a three-phase power system 2, a U-phase leg 31U, a V-phase leg 31V, and a U-phase leg 31U provided in the main circuit section 3. and a control device 5 (details will be described later) that controls the W-phase leg 31W (an example of a plurality of legs). The main circuit unit 3 provided in the power converter 1 includes a lower arm (an example of a first arm) 31Un, 31Vn, 31Wn and an upper arm (an example of a second arm) 31Up, 31Vp, 31Wp connected in series. It includes a phase leg 31U, a V-phase leg 31V, and a W-phase leg 31W. In this way, the power converter 1 is a three-phase voltage type power converter using the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W.

The main circuit section 3 is connected to upper arms 31Up, 31Vp, and 31Wp of both ends of lower arms 31Un, 31Vn, and 31Wn provided on each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W. A lower neutral point (an example of a first connection part) 32n is provided in which the opposite ends are connected to each other. Although the details will be described later, the lower arm 31Un, the lower arm 31Vn, and the lower arm 31Wn are star-connected (Y-connected). It has become a neutral point.

The main circuit section 3 is connected to lower arms 31Un, 31Vn, and 31Wn of both ends of upper arms 31Up, 31Vp, and 31Wp provided on each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W. An upper neutral point (an example of a second connection part) 32p is provided where the ends connected to each other are connected to each other. Although the details will be described later, the upper arm 31Up, the upper arm 31Vp, and the upper arm 31Wp are star-connected (Y-connected), and the connection portions of the respective ends of the upper arms 31Up, 31Vp, and 31Wp are connected to the star-connected It has become a neutral point.

The U-phase leg 31U has a lower arm 31Un and an upper arm 31Up. The V-phase leg 31V has a lower arm 31Vn and an upper arm 31Vp. The W-phase leg 31W has a lower arm 31Wn and an upper arm 31Wp. The U-phase leg 31U is connected to the U-phase cable 221 of the three-phase power system 2 via a terminal 31Ut provided at the connection between the lower arm 31Un and the upper arm Up. The V-phase leg 31V is connected to the V-phase cable 222 of the three-phase power system 2 via a terminal 31Vt provided at the connection between the lower arm 31Vn and the upper arm Vp. The W-phase leg 31W is connected to the W-phase cable 223 of the three-phase power system 2 via a terminal 31Wt provided at the connection between the lower arm 31Wn and the upper arm Wp.

As shown in FIG. 1, the lower arm 31Un provided on the U-phase leg 31U includes power inverter circuit cells 311Un1, . . . , 311Unx (an example of a first power inverter circuit cell) and power inverter circuit cells 311Un1, . ..., 311Unx and an AC reactor 312Un (an example of a first coil) connected in series. Here, x indicates the number of power conversion circuit cells provided in the lower arm 31Un. The upper arm 31Up provided on the U-phase leg 31U is connected in series to the power conversion circuit cells 311Up1, ..., 311Upx (an example of a second power conversion circuit cell) and the power conversion circuit cells 311Up1, ..., 311Upx. It has an AC reactor 312Up (an example of a second coil) connected thereto. Here, x indicates the number of power conversion circuit cells provided in the upper arm 31Up.

The lower arm 31Vn provided on the V-phase leg 31V is connected in series to the power conversion circuit cells 311Vn1, ..., 311Vnx (an example of the first power conversion circuit cell) and the power conversion circuit cells 311Vn1, ..., 311Vnx. It has a connected AC reactor 312Vn (an example of a first coil). Here, x indicates the number of power conversion circuit cells provided in the lower arm 31Vn. The upper arm 31Vp provided on the V-phase leg 31V is connected in series to the power inverter circuit cells 311Vp1,..., 311Vpx (an example of the second power inverter circuit cell) and the power inverter circuit cells 311Vp1,..., 311Vpx. It has a connected AC reactor 312Vp (an example of a second coil). Here, x indicates the number of power conversion circuit cells provided in the upper arm 31Vp.

The lower arm 31Wn provided on the W-phase leg 31W connects power conversion circuit cells 311Wn1, . . . , 311Wnx (an example of a first power conversion circuit cell) and power conversion circuit cells 311Wn1, . It has an AC reactor 312Wn (an example of a first coil) connected in series with an AC reactor 312Wn (an example of a power conversion circuit cell). Here, x indicates the number of power conversion circuit cells provided in the lower arm 31Wn. The upper arm 31Wp provided on the W-phase leg 31W is connected in series to the power inverter circuit cells 311Wp1,..., 311Wpx (an example of a second power inverter circuit cell) and the power inverter circuit cells 311Wp1,..., 311Wpx. It has a connected AC reactor 312Wp (an example of a second coil). Here, x indicates the number of power conversion circuit cells provided in the upper arm 31Wp.

As shown in FIG. 1, in the lower arm 31Un provided on the U-phase leg 31U, the power converter circuit cell 311Un1 of the power converter circuit cells 311Un1, . . . , 311Unx connected in series is connected to the AC reactor 312Un. ing. In the upper arm 31Up provided on the U-phase leg 31U, the power conversion circuit cell 311Upx of the power conversion circuit cells 311Up1, . . . , 311Upx connected in series is connected to the AC reactor 312Up. A connecting portion of AC reactor 312Un and AC reactor 312Up is connected to terminal 31Ut. A connecting portion of AC reactor 312Un and AC reactor 312Up is connected to U-phase cable 221 of three-phase power system 2 via terminal 31Ut.

In the lower arm 31Vn provided on the V-phase leg 31V, the power conversion circuit cell 311Vn1 of the power conversion circuit cells 311Vn1, . . . , 311Vnx connected in series is connected to the AC reactor 312Vn. In the upper arm 31Vp provided on the V-phase leg 31V, the power conversion circuit cell 311Vpx of the power conversion circuit cells 311Vp1, . . . , 311Vpx connected in series is connected to the AC reactor 312Vp. A connecting portion of AC reactor 312Vn and AC reactor 312Vp is connected to terminal 31Vt. A connecting portion of AC reactor 312Vn and AC reactor 312Vp is connected to V-phase cable 222 of three-phase power system 2 via terminal 31Vt.

In the lower arm 31Wn provided on the W-phase leg 31W, the power conversion circuit cell 311Wn1 of the power conversion circuit cells 311Wn1, . . . , 311Wnx connected in series is connected to the AC reactor 312Wn. In the upper arm 31Wp provided on the W-phase leg 31W, the power conversion circuit cell 311Wpx of the power conversion circuit cells 311Wp1, . . . , 311Wpx connected in series is connected to the AC reactor 312Wp. A connecting portion of AC reactor 312Wn and AC reactor 312Wp is connected to terminal 31Wt. A connecting portion of AC reactor 312Wn and AC reactor 312Wp is connected to W-phase cable 223 of three-phase power system 2 via terminal 31Wt.

As shown in FIG. 1, a power conversion circuit cell 311Unx provided on the lower arm 31Un and a power conversion circuit cell 311Up1 provided on the upper arm 31Up are arranged at both ends of the U-phase leg 31U. A power conversion circuit cell 311Vnx provided on the lower arm 31Vn and a power conversion circuit cell 311Vp1 provided on the upper arm 31Vp are arranged at both ends of the V-phase leg 31V. A power conversion circuit cell 311Wnx provided on the lower arm 31Wn and a power conversion circuit cell 311Wp1 provided on the upper arm 31Wp are arranged at both ends of the W-phase leg 31W.

An end of the power inverter circuit cell 311Unx that is not connected to the power inverter circuit cell (not shown), and an end of the power inverter circuit cell 311Vnx that is not connected to the power inverter circuit cell (not shown), Ends of the power inverter circuit cell 311Wnx that are not connected to the power inverter circuit cell (not shown) are connected to each other to form a lower neutral point 32n. An end of the power inverter circuit cell 311Up1 that is not connected to the power inverter circuit cell (not shown), and an end of the power inverter circuit cell 311Vp1 that is not connected to the power inverter circuit cell (not shown), The ends of the power inverter circuit cell 311Wp1 that are not connected to the power inverter circuit cell (not shown) are connected to each other to form an upper neutral point 32p.

The lower arm 31Un, the lower arm 31Vn, and the lower arm 31Wn are star-connected (Y-connected), and the upper arm 31Up, the upper arm 31Up, and the upper arm 31Wp are star-connected (Y-connected). Therefore, the main circuit section 3 has a double star connection structure. The lower neutral point 32n is formed at a connection portion where the lower arm 31Un, the lower arm 31Vn, and the lower arm 31Wn are connected to each other. The upper neutral point 32p is formed at a connection portion where the upper arm 31Up, the upper arm 31Up, and the upper arm 31Wp are connected to each other. The lower neutral point 32n and the upper neutral point 32p are electrically insulated.

(Power conversion circuit cell)
Next, the specific configuration of the power inverter circuit cells provided in each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W will be described using FIG. 2 while referring to FIG. 1. The power conversion circuit cells provided in each of the lower arm 31Un and upper arm 31Up of the U-phase leg 31U, the lower arm 31Vn and upper arm 31Vp of the V-phase leg 31V, and the lower arm 31Wn and upper arm 31Wp of the W-phase leg 31W are as follows: They have similar configurations. Therefore, regarding the specific configuration of the power inverter circuit cells provided in each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W, the power inverter circuit cells provided in the lower arm 31Un and upper arm 31Up are taken as an example. I will explain it to you.

FIG. 2 shows a power conversion circuit cell 311Uni (i is a natural number from 1 to x) of power conversion circuit cells 311Un1, ..., 311Unx provided in a lower arm 31Un of a U-phase leg 31U and a U-phase leg 31U. FIG. 3 is a diagram showing an example of the circuit configuration of a power conversion circuit cell 311Upi (i is a natural number from 1 to x) among power conversion circuit cells 311Up1, .

As shown in FIG. 2, the power conversion circuit cell 311Uni includes a plurality of (two in this embodiment) semiconductor modules Ma and a semiconductor module Mb connected in series (two in this embodiment), and a plurality (in this embodiment, two) of semiconductor modules Ma and Mb connected in series. It has a semiconductor module Mc and a semiconductor module Md. Semiconductor module Ma and semiconductor module Mb, and semiconductor module Mc and semiconductor module Md are connected in parallel. Furthermore, the power conversion circuit cell 311Uni has a capacitor C1 connected in parallel to the semiconductor modules Ma and Mb and the semiconductor modules Mc and Md. In this embodiment, the power storage element provided in the power conversion circuit cell 311Uni has a capacitor C1.

The semiconductor module Ma includes a semiconductor switch Qa and a freewheeling diode Da connected in antiparallel to the semiconductor switch Qa. The semiconductor module Mb includes a semiconductor switch Qb and a freewheeling diode Db connected in antiparallel to the semiconductor switch Qb. The semiconductor module Mc includes a semiconductor switch Qc and a freewheeling diode Dc connected in antiparallel to the semiconductor switch Qc. The semiconductor module Md includes a semiconductor switch Qd and a freewheeling diode Dd connected in antiparallel to the semiconductor switch Qd.

Therefore, the power inverter circuit cell 311Uni includes two semiconductor switches Qa and Qb connected in series and a capacitor C1 connected in parallel to the two semiconductor switches Qa and Qb. Furthermore, the power conversion circuit cell 311Uni has two semiconductor switches Qc and Qd connected in series. The two semiconductor switches Qc and Qd are connected in parallel to the two semiconductor switches Qa and Qb and the capacitor C1.

In this embodiment, the semiconductor switches Qa, Qb, Qc, and Qd are configured with, for example, insulated gate bipolar transistors (IGBTs). The collector terminal of the semiconductor switch Qa is connected to the cathode terminal of the freewheeling diode Da, the collector terminal of the semiconductor switch Qc, and the cathode terminal of the freewheeling diode Dc. The emitter terminal of the semiconductor switch Qa is connected to the anode terminal of the freewheeling diode Da, the collector terminal of the semiconductor switch Qb, and the cathode terminal of the freewheeling diode Db. A gate terminal of the semiconductor switch Qa is connected to the control device 5. As a result, the gate pulse signal S _{Uni_a} output from the control device 5 is input to the gate terminal of the semiconductor switch Qa, and the on/off of the semiconductor switch Qa is controlled.

The emitter terminal of the semiconductor switch Qb is connected to the emitter terminal of the semiconductor switch Qa and the anode terminal of the freewheeling diode Da. A gate terminal of the semiconductor switch Qb is connected to the control device 5. As a result, the gate pulse signal S _{Uni_b} output from the control device 5 is input to the gate terminal of the semiconductor switch Qb, and the on/off of the semiconductor switch Qb is controlled.

The emitter terminal of the semiconductor switch Qc is connected to the anode terminal of the freewheeling diode Dc, the collector terminal of the semiconductor switch Qd, and the cathode terminal of the freewheeling diode Dd. A gate terminal of the semiconductor switch Qc is connected to the control device 5. As a result, the gate pulse signal S _{Uni_c} output from the control device 5 is input to the gate terminal of the semiconductor switch Qb, and the on/off of the semiconductor switch Qc is controlled.

A gate terminal of the semiconductor switch Qd is connected to the control device 5. As a result, the gate pulse signal S _{Uni_d} output from the control device 5 is input to the gate terminal of the semiconductor switch Qd, and the on/off of the semiconductor switch Qd is controlled.

One electrode of the capacitor C1 is connected to the collector terminal of the semiconductor switch Qa, the cathode terminal of the freewheeling diode Da, the collector terminal of the semiconductor switch Qc, and the cathode terminal of the freewheeling diode Dc. The other electrode of the capacitor C1 is connected to the emitter terminal of the semiconductor switch Qb, the anode terminal of the freewheeling diode Db, the emitter terminal of the semiconductor switch Qd, and the anode terminal of the freewheeling diode Dd.

The connection portion between the semiconductor module Ma and the semiconductor module Mb is connected to the terminal T1 of the power conversion circuit cell 311Uni. A connecting portion between the semiconductor module Mc and the semiconductor module Md is connected to a terminal T2 of the power conversion circuit cell 311Uni. Terminal T1 of power inverter circuit cell 311Uni (i=2,3,...,x-1) is terminal T2 of power inverter circuit cell 311Uni-1 (i=2,3,...,x-1) It is connected to the. Terminal T2 of power inverter circuit cell 311Uni (i=1,2,...,x-1) is connected to terminal T1 of power inverter circuit cell 311Uni+1 (i=1,2,...,x-1) has been done. Terminal T1 of power conversion circuit cell 311Un1 is connected to one terminal of AC reactor 312Un. A terminal T2 of the power conversion circuit cell 311Unx is connected to the lower neutral point 32n. The terminal T2 of the power inverter circuit cell 311Unx is connected to the terminal T2 (not shown) and W of the power inverter circuit cell 311Vnx (see FIG. 1) provided on the lower arm 31Vn of the V-phase leg 31V via the lower neutral point 32n. It is connected to a terminal T2 (not shown) of a power conversion circuit cell 311Wnx (see FIG. 1) provided on the lower arm 31Wn of the phase leg 31W.

The voltage v _Uni , which is the potential difference between terminal T1 and terminal T2, is a positive voltage when the potential of terminal T1 is higher than the potential of terminal T2, and when the potential of terminal T1 is lower than the potential of terminal T2. Let be a negative voltage.

The power conversion circuit cell 311Uni has a voltage detection section 313 that detects the voltage between both electrodes of the capacitor C1. Voltage detection section 313 is connected to control device 5. The voltage detection unit 313 is configured to output the detected voltage v _{c_Uni} to the control device 5 . The voltage v _{c_Uni} is a positive voltage when the potential of one electrode connected to the semiconductor modules Ma, Mc is higher than the potential of the other electrode connected to the semiconductor modules Mb, Md. A case where the potential of the electrode is lower than the potential of the other electrode is considered to be a negative voltage.

As shown in FIG. 2, the power conversion circuit cell 311Upi has the same configuration as the power conversion circuit cell 311Uni. For this reason, regarding the power inverter circuit cell 311Upi, components having the same actions and functions as the power inverter circuit cell 311Uni are given the same reference numerals and explanations thereof will be omitted.

The power conversion circuit cell 311Upi includes two semiconductor switches Qa and Qb connected in series, and a capacitor C1 connected in parallel to the two semiconductor switches Qa and Qb. Furthermore, the power conversion circuit cell 311Upi has two semiconductor switches Qc and Qd connected in series. The two semiconductor switches Qc and Qd are connected in parallel to the two semiconductor switches Qa and Qb and the capacitor C1. In this embodiment, the power storage element provided in the power conversion circuit cell 311Upi includes a capacitor C1.

A gate terminal of the semiconductor switch Qa is connected to the control device 5. As a result, the gate pulse signal S _{Upi_a} output from the control device 5 is input to the gate terminal of the semiconductor switch Qa, and the on/off of the semiconductor switch Qa is controlled. A gate terminal of the semiconductor switch Qb is connected to the control device 5. As a result, the gate pulse signal S _{Upi_b} output from the control device 5 is input to the gate terminal of the semiconductor switch Qb, and the on/off of the semiconductor switch Qb is controlled. A gate terminal of the semiconductor switch Qc is connected to the control device 5. As a result, the gate pulse signal S _{Upi_c} output from the control device 5 is input to the gate terminal of the semiconductor switch Qc, and the on/off of the semiconductor switch Qc is controlled. A gate terminal of the semiconductor switch Qd is connected to the control device 5. As a result, the gate pulse signal S _{Upi_d} output from the control device 5 is input to the gate terminal of the semiconductor switch Qd, and the on/off of the semiconductor switch Qd is controlled.

A connection portion between the semiconductor module Ma and the semiconductor module Mb provided in the power conversion circuit cell 311Upi is connected to the terminal T1 of the power conversion circuit cell 311Upi. A connection portion between the semiconductor module Mc and the semiconductor module Md provided in the power conversion circuit cell 311Upi is connected to the terminal T2 of the power conversion circuit cell 311Upi. The terminal T1 of the power inverter circuit cell 311Upi (i=2,3,...,x-1) is the terminal T2 of the power inverter circuit cell 311Upi-1 (i=2,3,...,x-1). It is connected to the. Terminal T2 of power inverter circuit cell 311Upi (i=1,2,...,x-1) is connected to terminal T1 of power inverter circuit cell 311Upi+1 (i=1,2,...,x-1) has been done. Terminal T2 of power conversion circuit cell 311Upx is connected to the other terminal of AC reactor 312Up. Note that one terminal of the AC reactor 312Up is connected to the other terminal of the AC reactor 312Un. Terminal T1 of power conversion circuit cell 311Up1 is connected to upper neutral point 32p. The terminal T1 of the power inverter circuit cell 311Up1 is connected to the terminal T1 (not shown) of the power inverter circuit cell 311Vp1 (see FIG. 1) provided on the upper arm 31Vp of the V-phase leg 31V via the upper neutral point 32p and the W-phase It is connected to a terminal T1 (not shown) of a power conversion circuit cell 311Wp1 (see FIG. 1) provided on the upper arm 31Wp of the leg 31W.

The voltage v _Upi , which is the potential difference between the terminal T1 and the terminal T2 of the power conversion circuit cell 311Upi, is a positive voltage when the potential of the terminal T1 is higher than the potential of the terminal T2, and the potential of the terminal T1 is higher than the potential of the terminal T2. If the potential is lower than the potential of , it is considered a negative voltage.

The voltage detection unit 313 provided in the power conversion circuit cell 311Upi is configured to output the detected voltage v _{c_Upi} to the control device 5. The voltage v _{c_Upi} is a positive voltage when the potential of one electrode connected to the semiconductor modules Ma, Mc is higher than the potential of the other electrode connected to the semiconductor modules Mb, Md. A case where the potential of the electrode is lower than the potential of the other electrode is considered to be a negative voltage.

In this embodiment, the number of power conversion circuit cells arranged in each arm in series is determined according to the maximum output voltage, which is one of the device specifications of the power conversion device 1. Therefore, the power conversion device 1 may have one or more (two or more) power conversion circuit cells for each arm. Further, in this embodiment, the power conversion circuit cell has a circuit configuration of a two-level full-bridge converter cell, but other types (for example, a neutral point (clamp 3-level full bridge converter cell, etc.) may also be used.

(Control device)
Next, a control device (an example of a control unit) 5 that is included in the power conversion device 1 and controls the semiconductor switches Qa, Qb, Qc, and Qd will be described using FIGS. 3 to 6 with reference to FIGS. 1 and 2. I will explain. In explaining the control device 5, the voltage and current of each part of the power conversion device 1 will be defined. FIG. 3 illustrates the main circuit section 3 provided in the power conversion device 1 as a simple equivalent circuit, and also shows the voltage and current of each section. Further, in FIG. 3, illustration of the control device 5 is omitted. In the following explanation, for the sake of simplicity, the influence of harmonics generated by pulse width modulation (PWM) for generating gate pulse signals that control semiconductor switches Qa, Qb, Qc, and Qd will be ignored. . In addition, the lower arms 31Un, 31Vn, 31Wn and the upper arms 31Up, 31Vp, 31Wp provided in the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W, respectively, transmit only the voltage and current components according to the command values. Assume that you want to output.

As shown in FIG. 3, the system voltage and system current regarding the three-phase power system 2 are as follows. The polarity of the system current of each phase is such that a current flowing from the three-phase power system 2 toward the power converter 1 is positive, and a current flowing from the power converter 1 toward the three-phase power system 2 is negative.
v _u : System voltage outputted by the U-phase AC power supply 211 v _v : System voltage outputted by the V-phase AC power supply 212 v _w : System voltage outputted by the W-phase AC power supply 213 i _u : U-phase voltage outputted from the U-phase AC power supply 211 System current flowing into the leg 31U i _v : System current flowing into the V-phase leg 31V from the V-phase AC power supply 212 i _w : System current flowing into the W-phase leg 31W from the W-phase AC power supply 213

Each of the lower arm (hereinafter sometimes referred to as "U-phase lower arm") 31Un and upper arm (hereinafter sometimes referred to as "U-phase upper arm") 31Up provided on the U-phase leg 31U. The voltage at both ends (output voltage) is as follows. In addition, the lower arm (hereinafter sometimes referred to as "V-phase lower arm") 31Vn and upper arm (hereinafter sometimes referred to as "V-phase upper arm") 31Vp provided on the V-phase leg 31V. The voltage across each end (output voltage) is as follows. Furthermore, the lower arm (hereinafter sometimes referred to as "W-phase lower arm") 31Wn and upper arm (hereinafter sometimes referred to as "W-phase upper arm") 31Wp provided on the W-phase leg 31W. The voltage across each end (output voltage) is as follows.
v _Un : Voltage across the U-phase lower arm 31Un v _Up : Voltage across the U-phase upper arm 31Up v _Vn : Voltage across the V-phase lower arm 31Vn v _Vp : Voltage across the V-phase upper arm 31Vp v _Wn : Voltage across the W-phase lower arm 31Wn v _Wp : Voltage across the W-phase upper arm 31Wp

From one terminal to the other terminal of each of the U-phase lower arm 31Un, the U-phase upper arm 31Up, the V-phase lower arm 31Vn, the V-phase upper arm 31Vp, the W-phase lower arm 31Wn, and the W-phase upper arm 31Wp. The flowing output current is as follows. Regarding the polarity of the output current of each arm, a current flowing from the terminal T1 of the power conversion circuit cell toward the terminal T2 (see FIG. 2) is positive, and a current flowing from the terminal T2 toward the terminal T1 is negative.
i _Un : Output current of U-phase lower arm 31Un i _Up : Output current of U-phase upper arm 31Up i _Vn : Output current of V-phase lower arm 31Vn i _Vp : Output current of V-phase upper arm 31Vp i _Wn : Output current of W-phase lower arm 31Wn i _Wp : Output current of W-phase upper arm 31Wp

Circulating currents circulating through each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W are as follows. Regarding the polarity of the circulating current in each leg, a current flowing from the upper arm toward the lower arm is positive, and a current flowing from the lower arm toward the upper arm is negative.
i _{cir_u} : Circulating current circulating through the U-phase leg 31U i _{cir_v} : Circulating current circulating through the V-phase leg 31V i _{cir_w} : Circulating current circulating through the W-phase leg 31W

The zero-sequence voltage, which is the potential difference between the potential of the lower neutral point 32n and the ground potential, and the zero-sequence voltage, which is the potential difference between the potential of the upper neutral point 32p and the ground potential, are as follows.
v _Zn : Zero-sequence voltage at the lower neutral point 32n v _Zp : Zero-sequence voltage at the upper neutral point 32p

An AC reactor 312Un provided on the U-phase lower arm 31Un, an AC reactor 312Up provided on the U-phase upper arm 31Up, an AC reactor 312Vn provided on the V-phase lower arm 31Vn, and an AC reactor 312Vn provided on the V-phase upper arm 31Vp. The induced voltages generated in each of the AC reactor 312Vp provided in the AC reactor 312Vp, the AC reactor 312Wn provided in the W-phase lower arm 31Wn, and the AC reactor 312Wp provided in the W-phase upper arm 31Wp are as follows.
v _{L_Un} : Induced voltage of AC reactor 312Un v _{L_Up} : Induced voltage of AC reactor 312Up v _{L_Vn} : Induced voltage of AC reactor 312Vn v _{L_Vp} : Induced voltage of AC reactor 312Vp v _{L_Wn} : Induced voltage of AC reactor 312Wn v _{L_Wp} : AC reactor Tor 312Wp induced voltage

The average voltage value of the capacitor C1 provided in the power conversion circuit cell of each arm is as follows.
v _{C_Un} : Average voltage value of the capacitor at the lower arm 31Un of the U-phase leg 31U v _{C_Up} : Average voltage value of the capacitor at the upper arm 31Up of the U-phase leg 31U v _{C_Vn} : Average voltage value of the capacitor at the lower arm 31Vn of the V-phase leg 31V Value v _{C_Vp} : Average voltage value of the capacitor at the upper arm 31Vp of the V-phase leg 31V v _{C_Wn} : Average voltage value of the capacitor at the lower arm 31Wn of the W-phase leg 31W v _{C_Wp} : Voltage of the capacitor at the upper arm 31Wp of the W-phase leg 31W Average value

As shown in FIG. 1, among these voltages and currents, grid voltages v _u , v _v , v _w are detected by a voltage detection unit (not shown), grid currents i _u , i _v , i _w and output currents i _Un , i _Up , i _Vn , i _Vp , i _Wn , and i _Wp are detected by a current detection section (not shown) and input to the control device 5 . Furthermore, the voltages V _{C_Uni} , V _{C_Upi} , V _{C_Vni} , V _{C_Vpi} , V _{C_Wni} , and V _{C_Wpi} of the capacitors C1 provided in each of the power conversion circuit cells 311Uni, 311Upi, 311Vni, 311Vpi, 311Wni, and 311Wpi are determined by the voltage detection unit 313. (see FIG. 2) and is input to the control device 5.
The voltage detection unit that detects the grid voltages v _u , v _v , v _w , the current detection unit that detects the output currents i _Un , i _Up , i _Vn , i _Vp , i _Wn , i _Wp and the voltage detection unit 313 are This corresponds to a detection unit that detects the accumulated energy of the element or an amount equivalent to the accumulated energy. Although details will be described later, in this embodiment, the voltage detection unit 313 detects the voltages V _{C_Uni} , V _{C_Unp} , V _{C_Vni} , V _{C_Vnp} , V _{C_Wni} , and V _{C_Wpi} of the capacitor C1 as amounts corresponding to the stored energy, for example. The control device 5 is configured to control the semiconductor switches Qa, Qb, Qc, and Qd based on these currents and voltages input from the main circuit section 3 so that the power between the arms is balanced.

Specifically, as shown in FIG. 4, the control device 5 controls the zero-sequence voltage _vZn (an example of the first voltage) at the lower neutral point 32n and the zero-sequence voltage _vZp (the first voltage) at the upper neutral point 32p. The first zero-sequence power (one example of two voltages) flowing in and out between the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W is adjusted by adjusting the same voltage component contained in each of the It has an inter-leg power balancing control section (an example of a power control section) 5a that controls a power control section (an example of a power control section). The first zero-sequence power is the power generated by the system current (an example of current) flowing between each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W and the three-phase power system 2 and the voltage component. be.

The control device 5 also provides an arm voltage command value v _{u_acr_ref} of the voltage across the lower arm 31Un and upper arm 31Up of the U-phase leg 31U, and an arm voltage command value of the voltage across the lower arm 31Vn and upper arm 31Vp of the V-phase leg 31V. v _{v_acr_ref} and an arm voltage command value v _{w_acr_ref} of the voltage across the lower arm 31Wn and upper arm 31Wp of the W-phase leg 31W. Further, the control device 5 includes a gate pulse signal generation section 5c that generates a gate pulse signal. Further, the control device 5 includes a carrier wave generation section 5d that generates a carrier wave.

The inter-leg power balancing control unit 5a determines the average value of the voltage of the capacitor C1 provided in the U-phase leg 31U and the voltage of the capacitor C1 provided in each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W. and the average value of the voltage of the capacitor C1 provided on the V-phase leg 31V, and the average value of the voltage of the capacitor C1 provided on each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W. and the average value of the voltage of the capacitor C1 provided on the W-phase leg 31W, and the difference between the average value of the voltage of the capacitor C1 provided on each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W. The capacitor voltage balancing control section 51 controls the capacitor voltage so that the balance of the capacitor voltage is maintained.

The inter-leg power balancing control unit 5a controls a voltage v Un across the lower arm Un of the U-phase leg 31U and a voltage v _Up across the upper arm 31Up, a voltage v _Vn across the lower arm Vn of the V-phase leg 31V, and a voltage v _Vn across the lower arm 31V and the upper arm 31Vp. It has an arm voltage command value generation unit 52 that generates command values for the voltage v _Vp across the lower arm Wn of the W-phase leg 31W, and the voltage v _Wn across the lower arm Wn and the voltage v _Wp across the upper arm 31Wp of the W-phase leg 31W.

The capacitor voltage balancing control unit 51 controls the average value (voltage average value) of the voltage of the capacitor C1 provided in the lower arm Un of the U-phase leg 31U and the average value of the voltage average value of the capacitor C1 provided in the upper arm 31Up. and a capacitor voltage average difference detection unit 511 that detects a capacitor voltage average difference value that is the difference between the voltage average value of all the capacitors C1 provided in the main circuit unit 3. The average voltage value of all the capacitors C1 provided in the main circuit section 3 is the average voltage value of the capacitor C1 provided in the lower arm Un of the U-phase leg 31U, and the voltage average value of the capacitor C1 provided in the upper arm 31Up of the U-phase leg 31U. Average voltage value of C1, average voltage value of capacitor C1 installed in the lower arm Vn of V-phase leg 31V, average voltage value of capacitor C1 installed in upper arm 31Vp of V-phase leg 31V, lower voltage of W-phase leg 31W This is the average value of the voltage average value of the capacitor C1 provided in the arm Wn and the voltage average value of the capacitor C1 provided in the upper arm 31Wp of the W-phase leg 31W.

The capacitor voltage average difference detection unit 511 detects the average voltage value of the capacitor C1 provided in the lower arm Vn of the V-phase leg 31V and the average value of the voltage average value of the capacitor C1 provided in the upper arm 31Vp, and the main circuit unit 3 It is configured to also detect the difference between the voltage average value of all the capacitors C1 provided in the . Further, the capacitor voltage average difference detection unit 511 detects the average voltage value of the capacitor C1 provided in the lower arm Wn of the W-phase leg 31W and the average voltage value of the capacitor C1 provided in the upper arm 31Wp, and the main circuit. It is configured to also detect the difference between the voltage average value of all the capacitors C1 provided in the section 3.

Further, the capacitor voltage balancing control unit 51 adjusts the same voltage component included in each of the zero-sequence voltage _vZn of the lower neutral point 32n and the zero-sequence voltage _vZp of the upper neutral point 32p to adjust the capacitor voltage. It has a voltage suppression section 512 that suppresses the capacitor voltage average difference value detected by the average difference detection section 511.

Details of the inter-leg power balancing control section 5a, current adjustment section 5b, gate pulse signal generation section 5c, carrier wave generation section 5d, etc. will be described later.

Next, the function of the inter-leg power balancing control section 5a provided in the control device 5 will be explained first using mathematical formulas, and then the configuration in which the function is performed will be explained using a block diagram.

Here, as an example, attention will be paid to the U-phase lower arm 31Un. The voltage v _Un across the lower arm 31Un of the U phase can be defined by the following equation (1), where the voltage across the AC reactor 312Un is v _{L_Un} .

Further, the voltage average value v _{c_Up} of the capacitor C1 of the lower arm of the U phase can be defined by the following equation (2).

"i" in equations (1) and (2) is a natural number. Further, the voltages across the U-phase upper arm 31Up, the V-phase lower arm 31Vn and the upper arm 31Vp, and the W-phase lower arm 31Wn and the upper arm 31Wp, v _Up , v _Vn , v _Vp , v _Wn , v _Wp are calculated using the formula It can be defined similarly to (1). Further, the voltage average values of the capacitors C1 of the upper arm 31Up of the U phase, the lower arm 31Vn and the upper arm 31Vp of the V phase, and the lower arm 31Wn and the upper arm 31Wp of the W phase v _{C_Up} , v _{C_Vn} , v _{C_Vp} , v _{C_Wn} , v _{C_Wp} can be defined similarly to equation (1).

The circulating current i _{cir_u} circulating through the U-phase leg 31U, the circulating current i _{cir_v} circulating through the V-phase leg 31V, and the circulating current i _{cir_w} circulating through the W-phase leg 31W are subject to constraints as shown in equation (3) below.

The capacitor voltage average difference value v _{C_U} , which is the difference between the average voltage value of the capacitor C1 in the U-phase leg 31U and the average voltage value of the capacitor C1 in the entire main circuit section 3, can be defined by the following equation (4). . In addition, the capacitor voltage average difference value Δv _{C_V} , which is the difference between the average voltage value of the capacitor C1 in the V-phase leg 31V and the average voltage value of the capacitor C1 in the entire main circuit section 3, is defined by the following equation (5). Can be done. Furthermore, the capacitor voltage average difference value Δv _{C_W} , which is the difference between the average voltage value of the capacitor C1 in the W-phase leg 31W and the average voltage value of the capacitor C1 in the entire main circuit section 3, is defined by the following equation (6). Can be done.

In equations (4) to (6), the first term on the right side indicates the average voltage value of capacitor C1 in each leg, that is, the average value of the voltage average values of capacitor C1 in each of the upper and lower arms. . In addition, in equations (4) to (6), the second term on the right side is the average voltage value of the capacitor C1 in the entire main circuit section 3, that is, all the upper and lower arms provided in the main circuit section 3. The average value of the voltage average values of each capacitor C1 of the arm is shown.

The capacitor voltage average difference values Δv _{C_U} , Δv _{C_V} , Δv _{C_W} in each leg shown in equations (4) to (6) can be calculated as shown in equation (7) for convenience by performing three-phase and two-phase coordinate transformation. The capacitor voltage average difference values can be expressed as Δv _{C_α} , Δv _{C_β} , and Δv _{C_0} .

In the power converter 1, under ideal conditions in which three-phase balanced power is output and there are no variations in the characteristics of the parts used to configure the power converter 1, the capacitor voltage average difference values in each leg Δv _{C_α} , Δv _{C_β} , Δv _{C_0} becomes zero. However, if the power conversion device 1 continues to operate under the condition that the three-phase power system 2 has failed and the system voltages v _u , v _v , v _w are unbalanced in the three phases, the power conversion device 1 Three-phase unbalanced power will be output. Under the condition that the system voltages v _u , v _v , v _w are three-phase unbalanced, the voltage between both electrodes of the capacitor C1 between the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W is v _{c_Uni} , v _{c_Upi} , v _{c_Vni} , v _{c_Vpi} , v _{c_Wni} , and v _{c_Wpi} become unbalanced (unbalanced). Therefore, it is necessary to suppress the capacitor voltage average difference values Δv _{C_U} , Δv _{C_V} , and Δv _{C_W} in each leg within the range defined by the specifications of the power converter 1 . The power converter 1 according to the present embodiment maintains capacitor voltage average difference values Δv _{C_α} and Δv _{C_β} in the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W even under the condition of outputting three-phase unbalanced power. It is possible to keep it within a predetermined range, and stable operation can be continued. The predetermined range is, for example, within a range of 1% to 2% of the absolute maximum rating of the voltages v _{c_Uni} , v _{c_Upi} , v _{c_Vni} , v _{c_Vpi} , v _{c_Wni} , v _{c_Wpi} between both electrodes of the capacitor C1.

Therefore, the power converter 1 according to the present embodiment utilizes the same voltage component contained in each of the zero-sequence voltage _vZn of the lower neutral point 32n and the zero-sequence voltage _vZp of the upper neutral point 32p. It is configured. Thereby, even if the three-phase power system 2 fails and the system voltages v _u , v _v , v _w fall into three-phase imbalance, the power conversion device 1 can continue to operate stably.

Table 1 shows the voltages (output voltages), output currents, and It is a list showing output power.

In Table 1, the output power that each arm can output is as follows.
p _Un : Output power of U-phase lower arm 31Un p _Up : Output power of U-phase upper arm 31Up p _Vn : Output power of V-phase lower arm 31Vn p _Vp : Output power of V-phase upper arm 31Vp p _Wn : Output power of W-phase lower arm 31Wn p _Wp : Output power of V-phase upper arm 31Vp

The inflow power flowing into the three-phase power system 2 from the U-phase leg 31U is Δp _{_U} , the inflow power flowing into the three-phase power system 2 from the V-phase leg 31V is Δp _{_V} , and the inflow power flowing into the three-phase power system 2 from the W-phase leg 31W is Δp _V. Let Δp _{_W} be the inflow power flowing into the inflow, the respective inflow powers Δp _{_U} , Δp _{_V} , and Δp _{_W} can be defined as in the following equation (8).

Here, the first term on the right side of equation (8) is the power flowing in and out between the power conversion device 1 and the three-phase power system 2. Each of the first terms on the right side of equation (8) shows that under the condition that the power converter 1 is outputting positive-sequence reactive power, there is pulsation that is twice the grid frequency, but it becomes zero after time accumulation. . However, under the condition that the power converter 1 continues to operate and outputs reverse-phase reactive power when the three-phase power system 2 fails, each of the first terms on the right side of equation (8) performs time accumulation. and has a finite value. This finite value is in joules (J) and is an energy value. That is, if the power conversion device 1 continues to operate during a failure of the three-phase power system 2, the voltage of the capacitor C1 will be in an unbalanced state (unbalanced) between the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W. become. Therefore, by adjusting the values of the zero-sequence voltages v _Zp , v _Zn in the second term on the right side of equation (8) and the circulating currents i _{cir_u} , i _{cir_v} , i _{cir_w} in the third term on the right side of equation (8), By adjusting the values of the second term and the third term, it is possible to suppress the unbalanced state of the inflow powers Δp _{_U} , Δp _{_V} , and Δp _{_W} . The power conversion device 1 according to the present embodiment adjusts the value of the second term on the right side of equation (8) to adjust the capacitor voltage between the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W (the inter-leg capacitor It is characterized in that it controls the unbalanced state of the inflow power (ie, the unbalanced state of the inflow powers Δp _{_U} , Δp _{_V} , Δp _{_W} ).

The inflow power of the U-phase leg 31U is _{Δp_U} , the inflow power of the V-phase leg 31V is _{Δp_V} , and the inflow power of the W-phase leg _31W is Δp_W. ).

In this embodiment, the second term on the right side of equation (8), that is, the zero-sequence voltage vZn of the lower neutral point 32n, the zero-sequence voltage _vZp of the upper neutral point 32p, and _the U-phase from the three-phase power system 2 The capacitor voltage average difference values Δv _{C_α} , Δv C_β , Δv in each leg are determined by the first zero-sequence power generated by the system currents i _u , i _v , i _w flowing into the leg 31U, the V-phase leg _31V , and the W-phase leg 31W. _{C_0} is balanced. The power converter 1 balances the capacitor voltage average difference values Δv _{C_α} , Δv _{C_β} , Δv _{C_0} in each leg in the capacitor voltage balancing control unit 51 provided in the inter-leg power balancing control unit 5 a of the control device 5 ( balance). The power conversion device 1 can control the power balance between the legs by suppressing the capacitor voltage average difference values Δv _{C_U} , Δv _{C_V} , Δv _{C_W} in each leg within a predetermined range.

Specifically, the angular frequency of the system voltages v _u , v _v , v _w is ω _S , the effective value of the positive phase component is V _{S_p} , the effective value of the negative phase component is V _{S_n} , and the phase difference of the negative phase component is Φ _vn , the system voltages v _u , v _v , v _w can be defined as the following equation (10).

Under conditions where no failure has occurred in the three-phase power system 2, the effective value _{VS_n} of the negative phase components of the system voltages v _u , v _v , v _w is zero. However, when a system fault that causes three-phase unbalance, such as a single-phase ground fault or a two-phase short circuit, occurs in the three-phase power system 2, the effective value V _{S_n} of the negative phase component of the system voltages v _u , v _v , v _w becomes finite. It will have a value.

Assuming that the effective values of the grid currents i _u , i _v , i _w are I _S and the phase difference with respect to the phases of the grid voltages v _u , v _v , v _w is Φ _pf , the grid current i u flowing into the power conversion device 1 _is , i _v , i _w can be defined as the following equation (11). When the power conversion device 1 according to the present embodiment is assumed to operate as a reactive power compensator, the phase difference Φ _pf of the grid currents i _u , i _v , i _w is either ±π/2. will be taken.

The phase difference between the zero-sequence voltage vZp of the upper neutral point 32p and the zero-sequence voltage _vZn of the lower neutral point _32n injected into the power converter 1 with respect to the system voltage _vu is _Φz , and the effective value is V _z , the zero-sequence voltage v _Zp and the zero-sequence voltage v _Zn can be defined as the following equation (12). The effective value V _z corresponds to the same voltage component included in each of the zero-phase voltages v _Zp and v _Zn .

By substituting equations (10), (11), and (12) into equation (9), the DC component ΔP _{_α} of the inflow power Δp _{_α} and the DC component ΔP _{_β} of the inflow power Δp _{_β} are expressed by the following equation (13). It is determined as follows.

As shown in equation (13), the power converter 1 according to the present embodiment adjusts the effective value V _z of the zero-sequence voltages v _Zp , v _Zn , controls reactive power, and adjusts the system voltages v _u , v _v , By adjusting the effective value V _{S_p} of the positive phase component of v _w , the difference between the inflow powers Δp _{_α} and p _{_β} between the legs, that is, the capacitor voltage average difference values Δv _{C_U} , Δv _{C_V} , and Δv _{C_W} between the legs, can be adjusted to a predetermined value. It can be kept within the range.

Next, a control block of the control device 5 provided in the power conversion device 1 according to the present embodiment will be explained using FIGS. 4 to 6.

As shown in FIG. 4, the capacitor voltage average difference detection unit 511 provided in the capacitor voltage balancing control unit 51 of the inter-leg power balancing control unit 5a has a power inverter circuit cell 311Uni ( (i is a natural number from 1 to x) is inputted with the voltage v _{c_Uni} detected by the voltage detection unit 313 (see FIG. 2). In addition, the capacitor voltage average difference detection unit 511 includes a voltage detection unit 313 (see FIG. 2) provided in each of the power conversion circuit cells 311Upi (i is a natural number from 1 to x) of the upper arm 31Up of the U phase. The detected voltage v _{c_Upi} is input. In addition, the capacitor voltage average difference detection unit 511 has a power inverter circuit cell 311Vni of the lower arm 31Vn of the V phase and a power inverter circuit cell 311Vpi (i is a natural number from 1 to x) provided in the upper arm 31Vp. The voltages v _{c_Vni} and v _{c_Vpi} detected by the provided voltage detection section 313 are input. Furthermore, the capacitor voltage average difference detection unit 511 has a power conversion circuit cell 311Wni of the W-phase lower arm 31Wn and a power conversion circuit cell 311Wpi (i is a natural number from 1 to x) provided in the upper arm 31Wp. The voltages v _{c_Wni} and v _{c_Wpi} detected by the provided voltage detection unit 313 are input.

The capacitor voltage average difference detection unit 511 uses the voltage v _{c_Uni} and the voltage v _{c_Upi} input from the voltage detection unit 313 to perform calculation based on equation (2), and calculates the voltage of the capacitor C1 provided in the lower arm 31Un. The average value of v _{c_Uni} and the average value of voltage v _{c_Upi} of capacitor C1 provided in upper arm 31Up are calculated. Further, the capacitor voltage average difference detection unit 511 uses the voltage v _{c_Vni} and the voltage v _{c_Vpi} input from the voltage detection unit 313 to execute calculation based on equation (2), and calculates the capacitor C1 provided in the lower arm 31Vn. The average value of the voltage v _{c_Vni} of , and the average value of the voltage v _{c_Vpi} of the capacitor C1 provided in the upper arm 31Vp are calculated. Further, the capacitor voltage average difference detection unit 511 uses the voltage v _{c_Wni} and the voltage v _{c_Wpi} input from the voltage detection unit 313 to execute calculation based on equation (2), and calculates the capacitor C1 provided in the lower arm 31Wn. The average value of the voltage v _{c_Wni} of , and the average value of the voltage v _{c_Wpi} of the capacitor C1 provided in the upper arm 31Wp are calculated. Further, the capacitor voltage average difference detection unit 511 uses the voltages v _{c_Uni} , v _{c_Upi} , v _{c_Vni} , v _{c_Vpi} , v _{c_Wni} , v _{c_Wpi} input from the voltage detection unit 313 to detect all the voltages provided in the main circuit unit 3 . Calculate the average voltage value of capacitor C1.

The capacitor voltage average difference detection unit 511 uses these calculated average values to execute calculations based on equations (4) to (6), and calculates capacitor voltage average difference values Δv _{C_U} , Δv _{C_V} , Δv _{C_W} do. Furthermore, the capacitor voltage average difference detection unit 511 uses these calculated average values to execute the calculation based on equation (7), and obtains the capacitor voltage average difference values Δv _{C_α} , Δv _{C_β} after three-phase and two-phase coordinate transformation. , Δv _{C_0} . The capacitor voltage average difference detection unit 511 outputs the calculated capacitor voltage average difference values Δv _{C_α} and Δv _{C_β} to the voltage suppressing unit 512. In this way, the capacitor voltage average difference detection unit 511 uses the voltages v _{c_Uni} , v _{c_Upi} , v _{c_Vni} , v _{c_Vpi} , v _{c_Wni} , v _{c_Wpi} input from the voltage detection unit 313 to determine the capacitor voltage average difference values Δv _{C_α} , It is configured to detect Δv _{C_β} and output the detected capacitor voltage average difference values Δv _{C_α} and Δv _{C_β} to the voltage suppressor 512 .

As shown in FIG. 5, the voltage suppression section 512 provided in the capacitor voltage balancing control section 51 includes a feedback section 512FB and a feedforward section 512FF. Based on the capacitor voltage average difference values Δv _{C_α and} Δv _{C_β} inputted from the capacitor voltage average difference detection unit 511, the feedback unit 512FB calculates the zero-sequence voltage v _{Zp of the upper neutral point 32p and the zero-phase voltage v Zp} of the lower neutral point 32n. It is configured to generate a command value for the phase voltage _vZn . The feedforward unit 512FF is configured to correct an unbalanced state of output power between legs caused by a negative phase voltage component before the capacitor voltage between the legs becomes unbalanced.

As shown in FIG. 5, the feedback section 512FB provided in the voltage suppression section 512 is a low-pass filter that receives the capacitor voltage average difference value Δv _{C_α} output from the capacitor voltage average difference detection section 511 (see FIG. 4). It has a filter (Low Pass Filter: LPF) 512FBa. The feedback unit 512FB also includes a low-pass filter 512FBf into which the capacitor voltage average difference value Δv _{C_α} output from the capacitor voltage average difference detection unit 511 is input. The voltages _{vc_Uni} , _{vc_Upi} , _{vc_Vni} , _{vc_Vpi} , _{vc_Wni} , _{vc_Wpi} detected by the voltage detection unit 313 include a U-phase AC power supply 211, a V-phase AC power supply 212, and a W-phase AC power supply 213 (see FIG. 1). The pulsation of twice the frequency of the AC power source outputted from each of the two is superimposed. Therefore, the power conversion device 1 is provided with low-pass filters 512FBa and 512FBf for the purpose of attenuating the pulsation so that the pulsation does not affect the balancing control of the capacitor voltages of the upper and lower arms.

The feedback unit 512FB is an addition unit 512FBb to which a signal obtained by inverting the polarity of the capacitor voltage average difference value ΔV _{C_α} , which has passed through the low-pass filter 512FBa and from which high-frequency pulsation is removed from the capacitor voltage average difference value ΔV _{C_α,} is input. have. The adder 512FBb is configured so that a voltage of 0 volts (for example, a voltage at the same potential as ground) is also input. The adder 512FBb adds the 0 volt DC signal and the signal of the capacitor voltage average difference value ΔV _{C_α} whose polarity has been inverted, that is, outputs a signal obtained by subtracting the capacitor voltage average difference value ΔV _{C_α} signal from the 0 volt DC signal. is configured to do so.

The feedback section 512FB includes a PI control section 512FBc connected to the addition section 512FBb. The PI control section 512FBc is configured to perform proportional-integral control on the signal input from the addition section 512FBb. The proportional calculation performed in the PI control unit 512FBc includes a parameter for converting the unit of the addition result in the addition unit 512FBb from voltage to power. Thereby, the PI control unit 512FBc can output a DC component command value P _{α_ref} that is a command value of the DC component ΔP _{_α} of the inflow power Δp _{_α} . The DC component command value P _{α_ref} is a command value for bringing the capacitor voltage average difference value ΔV _{C_α} close to zero.

The feedback unit 512FB is an addition unit 512FBg that receives a signal obtained by inverting the polarity of the capacitor voltage average difference value ΔV _{C_β} , which has passed through the low-pass filter 512FBf and has high-frequency pulsations removed from the capacitor voltage average difference value ΔV _{C_β} . have. The adder 512FBg is configured so that a voltage of 0 volts (for example, a voltage at the same potential as ground) is also input. The adder 512FBg adds the 0 volt DC signal and the signal of the capacitor voltage average difference value ΔV _{C_β} whose polarity has been inverted, that is, outputs a signal obtained by subtracting the capacitor voltage average difference value ΔV _{C_β} signal from the 0 volt DC signal. is configured to do so.

The feedback section 512FB includes a PI control section 512FBh connected to the addition section 512FBg. The PI control section 512FBh is configured to perform proportional-integral control on the signal input from the addition section 512FBg. The proportional calculation performed in the PI control unit 512FBh includes a parameter for converting the unit of the addition result in the addition unit 512FBg from voltage to power. Thereby, the PI control unit 512FBh can output a DC component command value P _{β_ref} , which is a command value of the DC component ΔP _{_β} of the inflow power Δp _{_β} . The DC component command value P _{β_ref} is a command value for bringing the capacitor voltage average difference value ΔV _{C_β} close to zero.

As shown in FIG. 5, the feedback unit 512FB receives the DC component command value P _{α_ref} output from the PI control unit 512FBc and the DC component command value P _{β_ref} output from the PI control unit 512FBh, and outputs the first zero. It has an amplitude calculation unit 512FBd that calculates the amplitude of the phase power. The amplitude calculation unit 512FBd calculates the amplitude of the first zero-sequence power by the square root of the sum of the square of the DC component command value P _{α_ref} and the square of the DC component command value P _{β_ref} .

The feedback unit 512FB is a division unit that divides the amplitude signal of the first zero-sequence power output from the amplitude calculation unit 512FBd by a signal in which the polarity of the effective value _IS of the system currents i _u , i _v , i _w is inverted. It has 512FBe. The dividing unit 512FBe converts the signal of the amplitude of the first zero-sequence power output from the amplitude calculation unit 512FBd into a signal with the polarity of the effective value _IS of the system currents i _u , i _v , i _w inverted (a negative polarity signal). ), it is possible to calculate a signal (negative polarity signal) in which the polarity of the signal of the effective value V _z of the zero-phase voltages v _Zp and v _Zn is inverted. The voltage suppressing unit 512 uses the amplitude calculating unit 512FBd and the dividing unit 512FBe to calculate the effective value V _z of the zero-sequence voltages v _Zp and v _Zn corresponding to the same voltage component included in each of the zero-sequence voltages v _Zp and v _Zn . can be extracted.

The feedback unit 512FB receives the capacitor voltage average difference value ΔV _{C_α} output from the low-pass filter 512FBa and the capacitor voltage average difference value ΔV _{C_β} output from the low-pass filter 512FBf, and receives the inflow power Δp _{_α} , Δp It has a phase difference calculation unit 512FBi that calculates the phase difference between the DC component command values P _{α_ref} and P _{β_ref} of _{_β} . Here, the phase difference between the DC component command values P _{α_ref} and P _{β_ref of} the inflow powers Δp _α and p _{_β} is the DC component command value P _{α_ref} of the inflow powers Δp _{_α} and p _{_β} with respect to the phase of the U-phase grid voltage v _u P is the phase difference of _{β_ref} . The phase difference calculation section 512FBi has a calculation section 512FBi-1 that calculates the ratio of the capacitor voltage average difference value ΔV _{C_β} to the capacitor voltage average difference value ΔV _{C_α} . The phase difference calculation unit 512FBi calculates the command value of the phase of the first zero-sequence power by calculating the inverse function (arctangent) of the tangent of the calculation result input from the calculation unit 512FBi-1. -2. The zero-phase voltages v _Zp and v _Zn are in phase with the capacitor voltage average difference values ΔV _{C_α} and ΔV _{C_β} . Therefore, the command value of the phase of the first zero-phase power can be calculated using the capacitor voltage average difference values ΔV _{C_α} and ΔV _{C_β} .

The feedback unit 512FB receives a signal (negative polarity signal) obtained by inverting the polarity of the first zero-phase power phase command value signal input from the phase difference calculation unit 512FBi, and grid currents i _u , i _v , i It has an adding unit 512FBj that adds the phase difference Φ of _w and the signal of _pf . That is, the adder 512FBj performs an operation equivalent to subtracting the phase of the first zero-sequence power from the phase difference Φ _pf of the system currents i _u , i _v , i _w . Thereby, the adder 512FBj calculates the phase difference of the first zero-sequence power with respect to the grid currents i _u , i _v , i _w , that is, the _phase difference Φ _z of the zero-sequence voltages v _Zp , v _Zn with respect to the grid voltage v u .

The feedback unit 512FB receives a signal (negative polarity signal) obtained by inverting the polarity of the effective value V _z of the zero-sequence voltage outputted from the division unit 512FBe, and zero-phase voltages v _Zp , v _Zn outputted from the addition unit 512FBj. It has a zero-phase voltage calculation unit 512FBk to which a signal of phase difference Φ _z is input. The zero-sequence voltage calculation unit 512FBk is configured to execute the calculation expressed by Equation (12) and output command values for the zero-sequence voltages v _Zp and v _Zn . The value input to the zero-phase voltage calculation unit 512FBk is based on the capacitor voltage average difference value. Therefore, the command values of the zero-phase voltages v _Zp and v _Zn output by the zero-phase voltage calculation unit 512FBk are correction values for correcting the current capacitor voltage average difference value to be small.

As shown in FIG. 5, the feedforward unit 512FF provided in the voltage suppression unit 512 is configured to control the effective value V _{S_n} of the negative phase component of the system voltages v _u , v _v , v _w and the system currents i _u , i _v , i The signal obtained by multiplying the effective value I _S of _w by √3 and multiplying by -1 is the signal obtained by inverting the polarity of the signal of the effective value I _S of the system currents i _u , i _v , i _w (a negative polarity signal). The power is controlled in the opposite direction when the voltage of the capacitor C1 provided on the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W is unbalanced (for example, when the voltage of the capacitor C1 is high, the capacitor C1 is In order to control the electric power in the direction of discharging, a value multiplied by -1 is input to one of the dividers 512FFa. The division unit 512FFa calculates the two input signals and outputs the effective value V _z of the zero-phase voltages v _Zp and v _Zn .

The feedforward unit 512FF receives a signal of the effective value V _z of the zero-phase voltages v _Zp , v _Zn input from the dividing unit 512FFa, and a signal of the phase difference Φ _z of the zero-phase voltages v _Zp , v _Zn . It has a zero-phase voltage calculation section 512FFb. The signal of the phase difference Φ _z between the zero-sequence voltages v _Zp and v _Zn that is input to the zero-sequence voltage calculation unit 512FFb is the first term on the right side of equation (11), that is, the amount of power generated due to the influence of the negative sequence voltage. It is set to a value that cancels out imbalance. That is, the phase difference Φ _z between the zero-sequence voltages v _Zp and v _Zn is a value in which the second term on the right side of equation (13) is reversed by 180 degrees from the first term on the right side of equation (13), and "Φ _z =2×Φ _pf −Φ _vn ”. Here, Φ _vn is the phase difference between the negative phase voltage when the phase of the positive phase voltage of the U-phase leg 31U is taken as a reference. The zero-sequence voltage calculation unit 512FFb performs the calculation expressed by equation (12) using the signal of the effective value V _z of the zero-sequence voltages v _Zp and v _Zn and the signal of the phase difference Φ _z of the zero-sequence voltage v _Zp . configured to run.

In the power conversion device 1, when the effective value _{VS_n} of the negative phase component of the system voltages v _u , v _v , v _w is known, the degree of the unbalanced state of the voltage of the capacitor C1 occurring between the legs can be predicted. Effective value _{VS_n} of negative phase components of system voltages v _u , v _v , v _{w ,} effective value I _S of system currents i _u , i _v , i _w , phase difference Φ _pf of system current i _u , upper neutral point 32p and the phase difference Φ _{cir_n} between the circulating currents i _{cir_n} flowing into and out of the lower neutral point 32 n. It is obtained from detected values such as voltages v _u , v _v , v _w and system currents i _u , i _v , i _w detected by the current detection unit. Therefore, the feedforward unit 512FF outputs command values for the zero-phase voltages v _Zp and v _Zn based on the unbalanced state of the voltage of the capacitor C1 predicted from the detected values from the zero-phase voltage calculation unit 512FFb.

As shown in FIG. 5, the voltage suppressing unit 512 uses command values of zero-sequence voltages v _Zp and v _Zn inputted from a zero-sequence voltage calculation unit 512FBk, and zero-sequence voltage v inputted from a zero-sequence voltage calculation unit 512FFb. It has an addition section 512F that adds the command values of _Zp and _vZn . The signals of the command values of the zero-phase voltages v _Zp and v _Zn input from the zero-phase voltage calculation unit 512FBk are signals of negative polarity, and the command values of the zero-phase voltage v _Zp input from the zero-phase voltage calculation unit 512FFb. The signal is a positive polarity signal. For this reason, the addition unit 512F calculates the zero-phase voltages v _Zp , v _Zn input from the zero-phase voltage calculation unit 512FBk from the signals of the command values of the zero-phase voltages v Zp , v _Zn input from the zero-phase voltage calculation unit _512FFb . Performs an operation equivalent to subtracting the command value signal. As a result, the adder 512F uses the zero-phase voltage v as a correction value for correcting the command value signals of the zero-phase voltages v _Zp and v _Zn based on the detected values so that the current capacitor voltage average difference value becomes small. The zero-phase voltage command value v _{Zp_ref} is output by correcting the command values of _Zp and v _Zn . Thereby, the zero-phase voltage command value v _{Zp_ref} output from the voltage suppressing section 512 becomes a command value for suppressing the capacitor voltage average difference value. The zero-sequence voltage command value v _{Zp_ref} is used as a command value for both the zero-sequence voltage v _Zp and the zero-sequence voltage v _Zn .

In this way, the power conversion device 1 includes the voltage detection unit 313 that detects the stored energy of the capacitor C1 as a power storage element or an amount equivalent to the stored energy, and performs inter-leg power balancing control provided in the power conversion device 1. The unit 5a includes a voltage suppressing unit (an example of an adjusting unit) 512 that adjusts the effective value _Vz (an example of a voltage component) of the zero-phase voltage _vZp according to the detected value detected by the voltage detecting unit 313. There is. In this embodiment, the voltage detection unit 313 detects the voltage between both electrodes of the capacitor C1 as an amount corresponding to the stored energy of the power storage element. The voltage suppressing unit 512 uses the capacitor voltage average difference value based on the voltage of the capacitor C1 detected by the voltage detecting unit 313 to generate a zero-phase voltage command value _{vZp_ref} for adjusting the effective value _Vz of the zero-phase voltage _vZp . is configured to generate.

FIG. 6 is a block diagram showing an example of a schematic configuration of the arm voltage command value generation section 52 provided in the inter-leg power balancing control section 5a. In FIG. 6, for ease of understanding, the capacitor voltage balancing control section 51 connected to the arm voltage command value generation section 52, the current adjustment section 5b, the gate pulse signal generation section 5c, and the connection to the gate pulse signal generation section 5c are shown. A carrier wave generating section 5d is also shown.

As shown in FIG. 6, the arm voltage command value generation unit 52 generates an output current i _Un of the U-phase lower arm 31Un and an output current i _Up of the U-phase upper arm 31Up detected by a current detection unit (not shown). It has an adding section 521u that adds the respective current signals. Further, the arm voltage command value generation section 52 includes a subtraction section 522u that subtracts the addition signal output from the addition section 521u by half. The arm voltage command value generation unit 52 can calculate the circulating current i _{cir_u} circulating through the U-phase leg 31U at the current time using the addition unit 521u and the subtraction unit 522u. The addition unit 521u and the subtraction unit 522u are an example of a calculation unit that calculates the circulating current i _{cir_u} using the output current i _Un flowing to the U-phase lower arm 31Un and the output current i _Up flowing to the U-phase upper arm 31Up. Equivalent to. In the present embodiment, the current value of the circulating current i _{cir_u} is half the sum of the respective current values of the output current i _Un flowing to the U-phase lower arm 31Un and the output current i _Up flowing to the upper arm 31Up.

The arm voltage command value generation section 52 has a P control section 524u connected to a subtraction section 522u. The P control section 524u is configured to perform proportional control on the signal of the circulating current i _{cir_u} input from the subtraction section 522u. The proportional calculation performed in the P control unit 524u includes a parameter for converting current into voltage. Thereby, the P control unit 524u can generate the arm voltage command correction value v _{u_cir_ref} for correcting the arm voltage command value v _{u_acr_ref} generated by the current adjustment unit 5b. The arm voltage command value v _{u_acr_ref} is a command value of a reactive voltage to be input/output between the U-phase AC power supply 211 and the U-phase leg 31U of the three-phase power system 2.

As shown in FIG. 6, the current adjustment section 5b connected to the arm voltage command value generation section 52 is composed of, for example, an ACR (Auto Current Regulator). System voltages v _u , v _v , v _w detected by a voltage detection unit (not shown) provided in the power converter 1 are input to the current adjustment unit 5 b. In addition, the current adjustment unit 5b includes system currents i _u , i _v , i _w is input. Further, grid current command values i _{u_ref} , i v_ref , i _{w_ref} , which are command values for grid currents i _u , i _v , i _w , are input to the _current adjustment unit 5b. The current adjustment unit 5b sets an arm voltage command based on input system voltages v _u , v _v , v _w , system currents i _u , i _v , i _w and system current command values i _{u_ref} , i _{v_ref} , i _{w_ref} It is configured to generate the values v _{u_acr_ref} , v _{v_acr_ref} , v _{w_acr_ref} . The arm voltage command value v _{v_acr_ref} is a command value of a reactive voltage to be input/output between the V-phase AC power supply 212 and the V-phase leg 31V of the three-phase power system 2. The arm voltage command value v _{w_acr_ref} is a command value of a reactive voltage to be input/output between the W-phase AC power supply 213 and the W-phase leg 31W of the three-phase power system 2.

As shown in FIG. 6, the arm voltage command value generation section 52 includes a first addition section 525u and a second addition section 526u into which the arm voltage command correction value v _{u_cir_ref} output from the P control section 524u is input. There is. A signal obtained by inverting the polarity of the arm voltage command value v _{u_acr_ref} of the U-phase leg 31U output from the current adjustment unit 5b is also input to the first addition unit 525u. A signal that does not invert the polarity of the arm voltage command value v _{u_acr_ref} of the U-phase leg 31U output from the current adjustment unit 5b is also input to the second addition unit 526u.

The first addition unit 525u adds the signal of the arm voltage command correction value v _{u_cir_ref} to the signal obtained by inverting the polarity of the arm voltage command value v _{u_acr_ref} of the U-phase leg 31U. As a result, the first addition unit 525u generates an arm voltage reserve of the U-phase upper arm 31Up, which has shifted the voltage of the signal obtained by inverting the polarity of the arm voltage command value v _{u_acr_ref} to the positive side by the arm voltage command correction value v _{u_cir_ref} . A command value v _{up_pre_ref} is generated. The second addition unit 526u adds the signal of the arm voltage command correction value v _{u_cir_ref} to the signal of the arm voltage command value v _{u_acr_ref} of the U-phase leg 31U. As a result, the second adder 526u generates an arm voltage preliminary command value v _{un_pre_ref} of the U-phase lower arm 31Un, which is obtained by voltage-shifting the signal of the arm voltage command value v _{u_acr_ref} to the positive side by the arm voltage command correction value v _{u_cir_ref} . generate.

As shown in FIG. 6, the arm voltage command value generation unit 52 generates the arm voltage preliminary command value v _{up_pre_ref} generated by the first addition unit 525u and the zero-phase voltage command value v output from the capacitor voltage balancing control unit 51. It has a first calculation unit 527u to which _{Zp_ref} is input. Further, the arm voltage command value generation unit 52 receives the arm voltage preliminary command value v _{un_pre_ref} generated by the second addition unit 526u and the zero-phase voltage command value v _{Zp_ref} output from the capacitor voltage balancing control unit 51. It has a second calculation unit 528u.

The first calculation unit 527u is configured to perform an addition process of adding the signal of the arm voltage preliminary command value v _{up_pre_ref} and the signal of the zero-phase voltage command value v _{Zp_ref} . The first calculation unit 527u applies the signal of the zero-phase voltage command value v _{Zp_ref} to the signal of the arm voltage preliminary command value v _{up_pre_ref} generated by the first addition unit 525u. Thereby, the first calculation unit 527u generates an arm voltage command value _{vUp_ref} in which a signal component for suppressing the unbalanced state of the capacitor C1 is added to the signal of the arm voltage preliminary command value _{vup_pre_ref} . Further, the second calculation unit 528u is configured to perform an addition process of adding the signal of the arm voltage preliminary command value v _{un_pre_ref} and the signal of the zero-phase voltage command value v _{Zp_ref} . The second calculation unit 528u applies the signal of the zero-phase voltage command value _{vZp_ref} to the signal of the arm voltage preliminary command value _{vun_pre_ref} generated by the second addition unit 526u. Thereby, the second calculation unit 528u generates an arm voltage command value v _{Un_ref} in which a signal component for suppressing the unbalanced state of the capacitor C1 is added to the signal of the arm voltage preliminary command value v _{un_pre_ref} . The arm voltage command value v _{Up_ref} generated by the first calculation unit 527u and the arm voltage command value v _{Un_ref} generated by the second calculation unit 528u are input to the gate pulse signal generation unit 5c.

As shown in FIG. 6, the arm voltage command value generation unit 52 generates an output current _iVn of the V-phase lower arm 31Vn and an output current iVp of the V-phase upper arm _31Vp detected by a current detection unit (not shown). It has an adding section 521v that adds the respective current signals. Further, the arm voltage command value generation section 52 includes a subtraction section 522v that subtracts the addition signal output from the addition section 521v by half. The arm voltage command value generation unit 52 can calculate the circulating current i _{cir_v} circulating through the V-phase leg 31V at the current time using the addition unit 521v and the subtraction unit 522v. The addition unit 521v and the subtraction unit 522v are an example of a calculation unit that calculates the circulating current i _{cir_v} using the output current i _Vn flowing to the V-phase lower arm 31Vn and the output current i _Vp flowing to the V-phase upper arm 31Vp. Equivalent to. In this embodiment, the current value of the circulating current i _{cir_v} is half the sum of the respective current values of the output current i _Vn flowing to the V-phase lower arm 31Vn and the output current i _Vp flowing to the V-phase upper arm 31Vp. become.

The arm voltage command value generation section 52 has a P control section 524v connected to a subtraction section 522v. The P control section 524v is configured to perform proportional control on the signal of the circulating current i _{cir_v} input from the subtraction section 522v. The proportional calculation performed by the P control unit 524v includes a parameter for converting current into voltage. Thereby, the P control unit 524v can generate an arm voltage command correction value _{vv_cir_ref} for correcting the arm voltage command value _{vv_acr_ref} generated by the current adjustment unit 5b.

As shown in FIG. 6, the arm voltage command value generation section 52 includes a first addition section 525v and a second addition section 526v to which the arm voltage command correction value v _{v_cir_ref} output from the P control section 524v is input. There is. A signal obtained by inverting the polarity of the arm voltage command value _{vv_acr_ref} of the V-phase leg 31V output from the current adjustment unit 5b is also input to the first addition unit 525v. A signal that does not invert the polarity of the arm voltage command value _{vv_acr_ref} of the V-phase leg 31V output from the current adjustment unit 5b is also input to the second addition unit 526v.

The first addition unit 525v adds the signal of the arm voltage command correction value _{vv_cir_ref} to the signal obtained by inverting the polarity of the arm voltage command value _{vv_acr_ref} of the V-phase leg 31V. As a result, the first adding unit 525v generates an arm voltage reserve of the V-phase upper arm 31Vp, which voltage-shifts the signal obtained by inverting the polarity of the arm voltage command value v _{v_acr_ref} to the positive side by the arm voltage command correction value v _{v_cir_ref} . A command value v _{vp_pre_ref} is generated. The second adder 526v adds the signal of the arm voltage command correction value _{vv_cir_ref} to the signal of the arm voltage command value _{vv_acr_ref} of the V-phase leg 31V. As a result, the second adder 526v generates an arm voltage preliminary command value _{vvn_pre_ref} of the V-phase lower arm 31Vn, which is a voltage shift of the arm voltage command value _{vv_acr_ref} to the positive side by the arm voltage command correction value _{vv_cir_ref} . generate.

As shown in FIG. 6, the arm voltage command value generation unit 52 generates the arm voltage preliminary command value _{vvp_pre_ref} generated by the first addition unit 525v and the zero-phase voltage command value v output from the capacitor voltage balancing control unit 51. It has a first calculation unit 527v to which _{Zp_ref} is input. Further, the arm voltage command value generation unit 52 receives the arm voltage preliminary command value _{vvn_pre_ref} generated by the second addition unit 526v and the zero-phase voltage command value _{vZp_ref} output from the capacitor voltage balancing control unit 51. It has a second calculation section 528v.

The first calculation unit 527v is configured to perform an addition process of adding the signal of the arm voltage preliminary command value _{vvp_pre_ref} and the signal of the zero-phase voltage command value _{vZp_ref} . The first calculation unit 527v applies the signal of the zero-phase voltage command value _{vZp_ref} to the signal of the arm voltage preliminary command value _{vvp_pre_ref} generated by the first addition unit 525v. Thereby, the first calculation unit 527v generates an arm voltage command value _{vVp_ref} in which a signal component for suppressing the unbalanced state of the capacitor C1 is added to the signal of the arm voltage preliminary command value _{vvp_pre_ref} . Further, the second calculation unit 528v is configured to perform an addition process of adding the signal of the arm voltage preliminary command value _{vvn_pre_ref} and the signal of the zero-phase voltage command value _{vZp_ref} . The second calculation unit 528v applies the signal of the zero-phase voltage command value _{vZp_ref} to the signal of the arm voltage preliminary command value _{vvn_pre_ref} generated by the second addition unit 526v. Thereby, the second calculation unit 528v generates an arm voltage command value _{vVn_ref} in which a signal component for suppressing the unbalanced state of the capacitor C1 is added to the signal of the arm voltage preliminary command value _{vvn_pre_ref} . The arm voltage command value _{vVp_ref} generated by the first calculation unit 527v and the arm voltage command value _{vVn_ref} generated by the second calculation unit 528v are input to the gate pulse signal generation unit 5c.

As shown _in FIG. 6, the arm voltage command value generation unit 52 generates an output current iWn of the W-phase lower arm _31Wn and an output current iWp of the W-phase upper arm 31Wp detected by a current detection unit (not shown). It has an adding section 521w that adds the respective current signals. Further, the arm voltage command value generation section 52 includes a subtraction section 522w that subtracts the addition signal output from the addition section 521w by half. The arm voltage command value generation unit 52 can calculate the circulating current i _{cir_w} circulating through the W-phase leg 31W at the current time using the addition unit 521w and the subtraction unit 522w. The addition unit 521w and the subtraction unit 522w are an example of a calculation unit that calculates the circulating current i _{cir_w} using the output current i _Wn flowing to the W-phase lower arm 31Wn and the output current i _Wp flowing to the W-phase upper arm 31Wp. Equivalent to. In this embodiment, the current value of the circulating current i _{cir_w} is half the sum of the respective current values of the output current i _Wn flowing to the W-phase lower arm 31Wn and the output current i _Wp flowing to the W-phase upper arm 31Wp. become.

The arm voltage command value generation section 52 has a P control section 524w connected to a subtraction section 522w. The P control section 524w is configured to perform proportional control on the signal input from the subtraction section 522w. The proportional calculation performed by the P control unit 524w includes a parameter for converting current into voltage. Thereby, the P control unit 524w can generate the arm voltage command correction value v _{w_cir_ref} for correcting the arm voltage command value v _{w_acr_ref} generated by the current adjustment unit 5b.

As shown in FIG. 6, the arm voltage command value generation section 52 includes a first addition section 525w and a second addition section 526w to which the arm voltage command correction value v _{w_cir_ref} output from the P control section 524w is input. There is. A signal obtained by inverting the polarity of the arm voltage command value _{vw_acr_ref} of the W-phase leg 31W output from the current adjustment unit 5b is also input to the first addition unit 525w. A signal that does not invert the polarity of the arm voltage command value _{vw_acr_ref} of the W-phase leg 31W output from the current adjustment unit 5b is also input to the second addition unit 526w.

The first addition unit 525w adds the signal of the arm voltage command correction value v _{w_cir_ref} to the signal obtained by inverting the polarity of the arm voltage command value v _{w_acr_ref} of the W-phase leg 31W. As a result, the first addition unit 525w generates an arm voltage reserve of the W-phase upper arm 31Wp, which has shifted the voltage of the signal obtained by inverting the polarity of the arm voltage command value v _{w_acr_ref} to the positive side by the arm voltage command correction value v _{w_cir_ref} . A command value v _{wp_pre_ref} is generated. The second addition unit 526w adds the signal of the arm voltage command correction value v _{w_cir_ref} to the signal of the arm voltage command value v _{w_acr_ref} of the W-phase leg 31W. As a result, the second adder 526w generates an arm voltage preliminary command value _{vwn_pre_ref} of the W-phase lower arm 31Wn, which is a voltage shift of the arm voltage command value _{vw_acr_ref} to the positive side by the arm voltage command correction value _{vw_cir_ref} . generate.

As shown in FIG. 6, the arm voltage command value generation unit 52 generates the arm voltage preliminary command value _{vwp_pre_ref} generated by the first addition unit 525w and the zero-phase voltage command value v output from the capacitor voltage balancing control unit 51. It has a first calculation unit 527w to which _{Zp_ref} is input. Further, the arm voltage command value generation unit 52 receives the arm voltage preliminary command value v _{wn_pre_ref} generated by the second addition unit 526w and the zero-phase voltage command value v _{Zp_ref} output from the capacitor voltage balancing control unit 51. It has a second calculation section 528w.

The first calculation unit 527w is configured to perform an addition process of adding the signal of the arm voltage preliminary command value v _{wp_pre_ref} and the signal of the zero-phase voltage command value v _{Zp_ref} . The first calculation unit 527w applies the signal of the zero-phase voltage command value _{vZp_ref} to the signal of the arm voltage preliminary command value _{vwp_pre_ref} generated by the first addition unit 525w. Thereby, the first calculation unit 527w generates an arm voltage command value v _{Wp_ref} in which a signal component for suppressing the unbalanced state of the capacitor C1 is added to the signal of the arm voltage preliminary command value v _{wp_pre_ref} . Further, the second calculation unit 528w is configured to perform an addition process of adding the signal of the arm voltage preliminary command value v _{wn_pre_ref} and the signal of the zero-phase voltage command value v _{Zp_ref} . The second calculation unit 528w applies the signal of the zero-phase voltage command value _{vZp_ref} to the signal of the arm voltage preliminary command value _{vwn_pre_ref} generated by the second addition unit 526w. Thereby, the second calculation unit 528w generates an arm voltage command value _{vWn_ref} in which a signal component for suppressing the unbalanced state of the capacitor C1 is added to the signal of the arm voltage preliminary command value _{vwn_pre_ref} . The arm voltage command value _{vWp_ref} generated by the first calculation unit 527w and the arm voltage command value _{vWn_ref} generated by the second addition unit 526w are input to the gate pulse signal generation unit 5c.

As shown in FIG. 6, the arm voltage command value generation section 52 includes a carrier wave generation section 5d. The carrier wave generation unit 5d generates a carrier wave SCui for the U-phase leg 31U, a carrier wave SCvi for the V-phase leg 31V, and a carrier wave SCwi for the W-phase leg 31W, and outputs them to the gate pulse signal generation unit 5c. do. The carrier wave SCui, the carrier wave SCvi, and the carrier wave SCwi have the same phase between phases, and are shifted in phase by 1/(x+1) degrees within the phase.

The gate pulse signal generation unit 5c is provided in the upper arm 31Up of the U-phase leg 31U based on the arm voltage command value v _{Up_ref} input from the first calculation unit 527u and the carrier wave SCui input from the carrier wave generation unit 5d. A gate pulse signal S _{Upi_a} for controlling the semiconductor switch Qa provided in each of the power inverter circuit cells 311Upi (i is a natural number from 1 to x) and a gate pulse signal S _{Upi_b} for controlling the semiconductor switch Qb. , generates a gate pulse signal S _{Upi_c} for controlling the semiconductor switch Qc and a gate pulse signal S _{Upi_d} for controlling the semiconductor switch Qd.

The gate pulse signal generation section 5c is provided in the lower arm 31Un of the U-phase leg 31U based on the arm voltage command value v _{un_ref} inputted from the second calculation section 528u and the carrier wave SCui inputted from the carrier wave generation section 5d. A gate pulse signal S _{Uni_a} for controlling the semiconductor switch Qa provided in each of the power inverter circuit cells 311Uni (i is a natural number from 1 to x) and a gate pulse signal S _{Uni_b} for controlling the semiconductor switch Qb. , generates a gate pulse signal S _{Uni_c} for controlling the semiconductor switch Qc and a gate pulse signal S _{Uni_d} for controlling the semiconductor switch Qd.

The gate pulse signal generation section 5c is provided in the upper arm 31Vp of the V-phase leg 31V based on the arm voltage command value v _{vp_ref} inputted from the first calculation section 527v and the carrier wave SCvi inputted from the carrier wave generation section 5d. A gate pulse signal S Vpi_a for controlling the semiconductor switch Qa provided in each _{of the power inverter circuit cells 311Vpi (i is a natural number from 1 to x) and a gate pulse signal S Vpi_b for} controlling the semiconductor switch Qb. , generates a gate pulse signal S _{Vpi_c} for controlling the semiconductor switch Qc and a gate pulse signal S _{Vpi_d} for controlling the semiconductor switch Qd.

The gate pulse signal generation section 5c is provided in the lower arm 31Vn of the V-phase leg 31V based on the arm voltage command value _{vvn_ref} inputted from the second calculation section 528v and the carrier wave SCvi inputted from the carrier wave generation section 5d. A gate pulse signal S Vni_a for controlling the semiconductor switch Qa provided in each _{of the power conversion circuit cells 311Vni (i is a natural number from 1 to x) and a gate pulse signal S Vni_b for} controlling the semiconductor switch Qb. , generates a gate pulse signal S _{Vni_c} for controlling the semiconductor switch Qc and a gate pulse signal S _{Vni_d} for controlling the semiconductor switch Qd.

The gate pulse signal generation section 5c is provided in the upper arm 31Wp of the W-phase leg 31W based on the arm voltage command value v _{wp_ref} inputted from the first calculation section 527w and the carrier wave SCwi inputted from the carrier wave generation section 5d. A gate pulse signal S _{Wpi_a} for controlling the semiconductor switch Qa provided in each of the power conversion circuit cells 311Wpi (i is a natural number from 1 to x) and a gate pulse signal S _{Wpi_b} for controlling the semiconductor switch Qb. , generates a gate pulse signal S _{Wpi_c} for controlling the semiconductor switch Qc and a gate pulse signal S _{Wpi_d} for controlling the semiconductor switch Qd.

The gate pulse signal generation section 5c is provided in the lower arm 31Wn of the W-phase leg 31W based on the arm voltage command value _{vWn_ref} inputted from the second calculation section 528w and the carrier wave SCwi inputted from the carrier wave generation section 5d. A gate pulse signal S _{Wni_a} for controlling the semiconductor switch Qa provided in each of the power conversion circuit cells 311Wni (i is a natural number from 1 to x) and a gate pulse signal S _{Wni_b} for controlling the semiconductor switch Qb. , generates a gate pulse signal S _{Wni_c} for controlling the semiconductor switch Qc and a gate pulse signal S _{Wni_d} for controlling the semiconductor switch Qd.

In this way, the gate pulse signals S _{Uni_a} ~ SU _{ni_d} , S _{Upi_a} ~ S _{Upi_d} , S _{Vni_a} ~ S _{Vni_d} , S _{Vpi_a} ~ S _{Vpi_d} , S _{Wni_a} ~ S _{Wni_d} , S _{Wpi_a} ~ S _{Wpi_d} are the output power differences between the legs. (that is, the capacitor voltage average difference value between legs) is generated based on arm voltage command values v _{Un_ref} , v _{Up_ref} , v _{Vn_ref} , v _{Vp_ref} , v _{Wn_ref} , and v _{Wp_ref} . For this reason, the semiconductor switches Qa, Qb, Qc, Qd provided in the lower arm 31Un and upper arm 31Up of the U phase, the lower arm 31Vn and upper arm Vp of the V phase, and the lower arm 31Wu and upper arm Wp of the W phase, respectively. is turned on/off by gate pulse signals S _{Uni_a} ~ SU _{ni_d} , S _{Upi_a} ~ S _{Upi_d} , S _{Vni_a} ~ S _{Vni_d} , S _{Vpi_a} ~ S _{Vpi_d} , S _{Wni_a} ~ S _{Wni_d} , S _{Wpi_a} ~ S _{Wpi_d} , The output power difference (ie, the capacitor voltage average difference value between the legs) is suppressed.

That is, the inter-leg power balancing control unit 5a uses the gate pulse signals S _{Uni_a} to S _{Wpi_d} based on the arm voltage command values v _{Un_ref} to v _{Wp_ref} generated by the arm voltage command value generation unit 52 to By controlling the semiconductor switches Qa, Qb, Qc, and Qd provided in each of the leg 31V and the W-phase leg 31W, the power of the first zero-sequence power of the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W is Suppress the difference. That is, the inter-leg power balancing control unit 5a detects the power as an amount equivalent to the stored energy so as to suppress the unbalanced state of power among each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W. The power difference between the first zero-phase power of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W is adjusted. As a result, the power conversion device 1 can continue to operate stably even if the system voltage becomes three-phase unbalanced.

As described above, the power converter 1 according to the present embodiment includes a U-phase leg 31U having a lower arm 31Un and an upper arm 31Up connected in series, and a V-phase leg having a lower arm 31Vn and an upper arm 31Vp connected in series. 31V and a W-phase leg 31W having a lower arm 31Wn and an upper arm 31Wp connected in series. Further, the power converter 1 is connected to upper arms 31Up, 31Vp, and 31Wp of both ends of lower arms 31Un, 31Vn, and 31Wn provided on the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W. A lower neutral point 32n whose ends are connected to each other, and a lower arm 31Un of both ends of upper arms 31Up, 31Vp, and 31Wp provided on the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W. , 31Vn, and 31Wn, and an upper neutral point 32p whose ends are connected to each other. Furthermore, the power conversion device 1 includes a control device 5 that controls a U-phase leg 31U, a V-phase leg 31V, and a W-phase leg 31W.

The lower arms 31Un, 31Vn, 31Wn include power conversion circuit cells 311Un1, . . . , 311Unx having semiconductor switches Qa, Qb connected in series and a capacitor C1 connected in parallel to the semiconductor switches Qa, Qb; It has an AC reactor 312Un connected in series to 311Un1, . . . , 311Unx.
Upper arms 31Up, 31Vp, 31Wp are connected in series to power conversion circuit cells 311Up1, . It has a connected AC reactor 312Up.
The control device 5 adjusts the effective value _Vz corresponding to the same voltage component contained in each of the zero-sequence voltage _vZn of the lower neutral point 32n and the zero-sequence voltage _vZp of the upper neutral point 32p, and It has an inter-leg power balancing control section 5a that adjusts the first zero-sequence power flowing in and out between each of the phase leg 31U, V-phase leg 31V, and W-phase leg 31W.

A power conversion device having such a configuration can continue to operate stably even if the grid voltage becomes unbalanced in three phases.

[Second embodiment]
A power conversion device according to a second embodiment of the present invention will be described using FIGS. 7 to 9. The power conversion device according to this embodiment is different from the power conversion device 1 according to the first embodiment described above in that the power between the legs is balanced using the power generated by the zero-sequence voltage, the grid current, and the circulating current. have. Hereinafter, in the description of the power conversion device according to the present embodiment, reference will be made to FIGS. 1 to 3, and the same reference numerals will be given to components that perform the same actions and functions as the power conversion device 1 according to the first embodiment. Therefore, the explanation will be omitted.

In this embodiment, as an example, as a method of balancing the capacitor voltage between the legs, the capacitor voltage average difference values Δv _{C_α} and Δv _{C_β} are used together with the second and third terms on the right side of equation (8), That is, a method of balancing power between legs using power generated by zero-phase voltages v _Zp , v _Zn , system currents i _u , i _v , i _w and circulating currents i _{cir_u} , i _{cir_v} , i _{cir_w} will be described. Here, as a specific example of the third term on the right side of equation (8), we use a DC circulating current and a DC voltage component of the zero-sequence voltage (the difference between the zero-sequence voltage _{v_Zp} and the zero-sequence voltage _{v_Zn} ). Explain the method. When the amplitude of the DC circulating currents i _{cir_u} , i _{cir_v} , i _{cir_w} is set as I _cir and the phase is set as Φ _cir , the circulating currents i _{cir_u} , i _{cir_v} , i _{cir_w} can be defined as the following equation (14). I can do it. The phase Φ _cir is the phase difference of the circulating current with respect to the grid current. Here, the circulating currents i _{cir_u} , i _{cir_v} , i _{cir_w} are defined using the phase Φ _cir for convenience. The phase Φ _cir corresponds to a parameter that determines the current sharing between the legs (interphases) of the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W.

Amplitude V of the difference between the zero-sequence voltage v _Zp of the DC voltage component of the upper neutral point 32p and the zero-sequence voltage v _Zn of the lower neutral point 32n, which are injected into the power converter 1 according to the present embodiment _zpn is defined as the following equation (15). Hereinafter, the difference between the DC voltage component of the zero-sequence voltage v _Zp and the DC voltage component of the zero-sequence voltage v _Zn may be abbreviated as "difference between the DC voltage components of the zero-sequence voltages v _Zp and v _Zn ."

Substituting Equations (10), Equations (14), and Equations (15) into Equation (9) and combining it with the derivation result of Equation (13), the DC component ΔP _{_α} of the inflow power Δp _{_α} and the DC component of the inflow power Δp _{_β} The component _{ΔP_β} is determined as shown in equation (16).

The first term on the right side of equation (16) corresponds to the first term on the right side of equation (8), and is the system voltage v _u , v _v , v _w and system current i _u , i _v of the three-phase power system 2. , i _w . The second term on the right side of Equation (16) corresponds to the second term on the right side of Equation (8), and is the power based on the zero-sequence voltages v _Zp , v _Zn and the grid currents i _u , i _v , i _w , i.e. This is the first zero-phase power. The third term on the right side of Equation (16) corresponds to the third term on the right side of Equation (8), and is the voltage difference between the zero-sequence voltage v _Zp and the zero-sequence voltage v _Zn and the circulating currents i _{u_cir} , i _{v_cir} , It is the power (second zero-sequence power) based on i _{w_cir} .

In this way, the inter-leg power balancing control unit 5a provided in the power converter 1 according to the present embodiment adjusts the zero-sequence voltage v _Zn (an example of the first voltage) of the lower neutral point 32n and the upper neutral point The same voltage component included in each of the zero-phase voltage v _Zp (an example of a second voltage) of 32p is adjusted to cause the voltage to flow in and out between each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W. It is configured to control one zero-phase power (an example of first power). Furthermore, the inter-leg power balancing control unit 5a controls the voltage difference between the zero-sequence voltage _vZn at the lower neutral point 32n and the zero-sequence voltage _vZp at the upper neutral point 32p, as well as the circulating current i flowing through the U-phase leg 31U. _{u_cir} is configured to control the second zero-phase power (an example of the second power) by adjusting at least one of the circulating current i _{v_cir} flowing in the V-phase leg 31V and the circulating current i _{w_cir} flowing in the W-phase leg 31W. There is. The inter-leg power balancing control unit 5a in this embodiment controls the first zero-sequence power and the second zero-sequence power to control the balance of the inflow powers Δp _{_U} , Δp _{_V} , and Δp _{_W} .

Next, a control block of the control device 5 provided in the power conversion device 1 according to the present embodiment will be explained using FIGS. 7 to 9. Regarding the control device 5 in this embodiment, the different configurations from the control device 5 in the first embodiment will be mainly explained, and the same configurations will be explained as necessary. The control device 5 in this embodiment performs capacitor voltage balance control between legs using the effective value _Vz of the zero-phase voltages v _Zp and v _Zn , and amplitude of the difference between the DC voltage components of the zero-phase voltages v _Zp and v _Zn . It is configured to perform a combined function of inter-leg capacitor voltage balance control using V _zpn .

The power converter 1 according to the present embodiment includes a voltage and current suppressor 513 instead of the voltage suppressor 512 (see FIG. 4) provided in the power converter 1 according to the first embodiment.

As shown in FIG. 7, the capacitor voltage balancing control section 51 provided in the inter-leg power balancing control section 5a of the control device 5 includes a capacitor voltage average difference detection section 511 and a voltage/current suppression section 513. ing. The capacitor voltage average difference detection unit 511 in this embodiment has the same configuration as the capacitor voltage average difference detection unit 511 in the first embodiment, and is designed to perform the same function.

Here, an example of a specific configuration of the voltage/current suppressor 513 will be described using FIG. 8.
As shown in FIG. 8, the voltage and current suppressor 513 includes a feedback section 513FB and a feedforward section 513FF. The feedback unit 513FB is configured to generate a DC circulating current command value based on the capacitor voltage average difference values Δv _{C_α} and Δv _{C_β} input from the capacitor voltage average difference detection unit 511. As in the first embodiment, the feedforward unit 513FF corrects the unbalanced state of the output power between the legs caused by the negative phase voltage component before the capacitor voltage between the legs becomes unbalanced. configured to correct.

As shown in FIG. 8, the feedback unit 513FB converts the amplitude signal of the first zero-sequence power output from the amplitude calculation unit 512FBd into a signal of the amplitude V _zpn of the difference between the DC voltage components of the zero-phase voltages v _Zp and v _Zn . It has a division unit 513FBe that divides by . The division unit 513FBe divides the signal of the amplitude of the first zero-phase power output from the amplitude calculation unit 512FBd by the signal of the amplitude V _zpn of the difference between the DC voltage components of the zero-phase voltages v _Zp and v _Zn . An amplitude command value I _{cir_FB} that is a command value for the amplitude of the circulating current can be calculated.

The feedback unit 512FB receives the capacitor voltage average difference value ΔV _{C_α} output from the low-pass filter 512FBa and the capacitor voltage average difference value ΔV _{C_β} output from the low-pass filter 512FBf, and calculates the level of the DC circulating current. It has a phase difference calculation unit 513FBi that calculates a phase difference command value Φ _{cir_FB} that is a command value of the phase difference. The phase difference calculation section 513FBi has a calculation section 513FBi-1 that calculates the ratio of the capacitor voltage average difference value ΔV _{C_β} to the capacitor voltage average difference value ΔV _{C_α} . The phase difference calculation unit 513FBi is a calculation unit that calculates the phase difference command value Φ _{cir_FB} of the DC circulating current by calculating the inverse function (arctangent) of the tangent of the calculation result input from the calculation unit 513FBi-1. 513FBi-2. The DC circulating current is in phase with the capacitor voltage average difference values ΔV _{C_α} and ΔV _{C_β} . Therefore, the phase difference command value Φ _{cir_FB} of the DC circulating current can be calculated using the capacitor voltage average difference values ΔV _{C_α} and ΔV _{C_β} .

The feedback unit 513FB receives the signal of the DC circulating current amplitude command value I _{cir_FB} inputted from the dividing unit 513FBe and the signal of the DC circulating current phase difference command value Φ _{cir_FB} inputted from the phase difference calculation unit 512FBi. It has a circulating current calculation unit 513FBk that receives input. The circulating current calculation unit 513FBk executes the calculation expressed _by equation (14) and outputs the circulating current first command values i _{cir_u_FB} , i _{cir_v_FB} , i _{cir_w_FB} of the circulating currents i cir_u , i _{cir_v} , _i cir_w. It is configured. The value input to the circulating current calculation unit 513FBk is based on the capacitor voltage average difference value. Therefore, the circulating current first command values i _{cir_u_FB} , i _{cir_v_FB} , and i _{cir_w_FB} output by the circulating current calculation unit 513FBk are correction values for correcting the current capacitor voltage average difference value to be small.

As shown in FIG. 8, the feedforward section 513FF provided in the voltage and current suppressing section 513 receives the zero-sequence voltage v _Zp output from the dividing section 512FFa having the same configuration as the dividing section 512FFa in the first embodiment. It has an upper limit limiting section 513FFb to which a signal of preliminary effective value V _zz of v _Zn is input. The upper limit limiter 513FFb is configured to output an effective value V _z of the zero-phase voltages v _Zp and v _Zn whose values are limited to the upper limit value βVmax when the input preliminary effective value V _zz is larger than the upper limit value βVmax. It is composed of On the other hand, the upper limit limiter 513FFb outputs the _preliminary effective value V _zz as the effective value V _z of the zero-phase voltages v _Zp and v _Zn when the input preliminary effective value V zz is less than the upper limit value βVmax. It is configured.

Here, "Vmax" of the upper limit value βVmax is the value that can be output by the U-phase lower arm 31Un and upper arm 31Up, the V-phase lower arm 31Vn and upper arm 31Vp, and the W-phase lower arm 31Wn and upper arm 31Wp. This is the residual voltage, and has a value of, for example, about 15% of the system voltages v _u , v _v , v _w . "β" of the upper limit value βVmax is the first zero-sequence power based on the effective value _Vz corresponding to the same voltage component of the zero-sequence voltages v _Zp and v _Zn , and the direct current of the zero-sequence voltages v _Zp and v _Zn . This is the injection ratio of the second zero-sequence power based on the amplitude V _zpn of the voltage component difference. In the power conversion device 1 according to the present embodiment, for example, in an initial state, more emphasis is placed on the first zero-sequence power than on the second zero-sequence power, and the initial value of the injection ratio β is set to, for example, 0.7. Details of the injection ratio β will be described later.

As shown in FIG. 8, the zero-phase voltage calculation unit 512FFb provided in the feedforward unit 513FF receives the signal of the effective value _Vz of the zero-phase voltage v _Zp and v _Zn input from the upper limit limiting unit 513FFb, and the feedforward The unit 513FF is configured to execute the calculation expressed by equation (12) using a signal of phase difference Φ _z between zero-phase voltages v _Zp and v _Zn inputted from the outside of the unit 513FF.

As shown in FIG. 8, the feedforward unit 513FF includes an amplitude calculation unit 513FFd to which the signal of the residual voltage Vmax and the signal of the injection ratio β are input. The amplitude calculation unit 513FFd executes the calculation expressed by "(1-β)×Vmax", for example, and calculates the amplitude V _zpn /2 of the zero-phase voltages v _Zp and v _Zn . The amplitude V _zpn /2 of the zero-sequence voltages v _Zp , v _Zn corresponds to 1/2 of the amplitude V _zpn of the difference between the DC voltage components of the zero-sequence voltages v _Zp , v _Zn .

The feedforward unit 513FF includes an amplifier unit 513FFe that doubles the signal of the amplitude V _zpn /2 of the zero-phase voltages v _Zp and v _Zn input from the amplitude calculation unit 513FFd. The amplification unit 513FFe doubles the amplitude V _zpn /2 of the zero-phase voltages v _Zp and v _Zn and outputs a signal with an amplitude V _zpn of the difference between the DC voltage components of the zero-phase voltages v _Zp and v _Zn .

The feedforward unit 513FF receives a signal (negative polarity signal) obtained by inverting the polarity of the signal having the amplitude V _zpn of the difference between the DC voltage components of the zero-phase voltages v _Zp and v _Zn output from the amplification unit 513FFe, and It has a dividing unit 513FFf to which a signal of remaining power (hereinafter sometimes abbreviated as "required remaining power") necessary to balance the power of is input. The required remaining power is calculated by multiplying the effective value _{VS_n} of the negative phase components of the grid voltages v _u , v _v , v _w and the effective value I _S of the grid currents i _u , i _v , i _w divided by √3. The value is obtained by subtracting _the value obtained by integrating the ratio of the effective value V z of the zero-phase voltages v _Zp , v _Zn to the preliminary effective value V _zz of the zero-phase voltages v _Zp , v _Zn . The dividing unit 513FFf divides the signal of the required remaining power by the signal of the amplitude V _zpn /2 of the zero-phase voltages v _Zp and v Zn to calculate an amplitude command value _{I cir_FF} that is a command value of the amplitude of the DC circulating current. .

The feedforward unit 513FF includes a circulating current calculation unit 513FFg to which the signal of the DC circulating current amplitude command value I _{cir_FF} input from the dividing unit 513FFf and the signal of the DC circulating current phase difference Φ _{cir_FF} are input. are doing. The phase difference Φ _{cir_FF} of the DC circulating current input to the circulating current calculation unit 513FFg is the phase difference Φ pf of the system current _{i u} with respect to the phase of the system voltages v _u , v _v , v _w as the phase difference Φ _pf of the system voltage v _u , v v , _{v w} , v _w by subtracting it from the phase difference Φ _vn of the anti-phase components. The circulating current calculation unit 513FFg executes the calculation expressed by equation (14) using the signal of the amplitude command value I _{cir_FF} of the DC circulating current and the signal of the phase difference Φ _{cir_FF} of the DC circulating current, _It is configured to output circulating current second command values i _{cir_u_FF} , i _{cir_v_FF} , i _{cir_w_FF} of the circulating currents i _{cir_u} , i cir_v , i _{cir_w} .

In the power converter 1 according to the present embodiment, similarly to the power converter 1 according to the first embodiment, when the effective value V _{S_n} of the negative phase component of the grid voltages v _u , v _v , v _w is known, the The extent of the resulting unbalanced voltage across capacitor C1 can be predicted. Therefore, the feedforward unit 513FF sets circulating current second command values i _{cir_u_FF} , i _{cir_v_FF} , i _{cir_w_FF} of the circulating currents i _{cir_u} , i _{cir_v} , i _{cir_w} based on the unbalanced state of the voltage of the capacitor C1 predicted from the detected values. is output from the circulating current calculation unit 513FFg.

As shown in FIG. 8, the voltage and current suppressing unit 513 receives signals of circulating current first command values i _{cir_u_FB} , i _{cir_v_FB} , and i _{cir_w_FB} input from the circulating current calculating unit 513FBk, and signals input from the circulating current calculating unit 513FFg. It has an adding section 513Fa that adds the signals of the circulating current second command values i _{cir_u_FF} , i _{cir_v_FF} , and i _{cir_w_FF} . The adding unit 513Fa uses the circulating current first command value as a correction value for correcting the signals of the circulating current second command values i _{cir_u_FF} , i _{cir_v_FF} , i _{cir_w_FF} based on the detected values to make the current capacitor voltage average difference value small. The circulating current command values i _{cir_u_ref} , i _{cir_v_ref} , i _{cir_w_ref} are output by correcting them using _{i cir_u_FB} , i _{cir_v_FB} , i _{cir_w_FB} . Thereby, the circulating current command values i _{cir_u_ref} , i _{cir_v_ref} , and i _{cir_w_ref} output from the voltage and current suppressing section 513 become command values for suppressing the capacitor voltage average difference value. Circulating current command value i _{cir_u_ref} is a command value of circulating current i _{cir_u} , circulating current command value i _{cir_v_ref} is a command value of circulating current i _{cir_v} , and circulating current command value i _{cir_w_ref} is a command value of circulating current i _{cir_w} . It is a value.

As shown in FIG. 8, the voltage and current suppressing unit 513 receives signals of amplitude V _zpn /2 of the zero-phase voltages v _Zp and v _Zn input from the amplitude calculating unit 513FFd and input from the zero-phase voltage calculating unit 512FFb. It has an adding section 513Fb that adds the signals of the command values of the zero-phase voltages v _Zp and v _Zn . The adding unit 513Fb adds the signal of the amplitude V _zpn /2 of the zero-phase voltages v _Zp , v _Zn and the signal of the command value of the zero-phase voltages v _Zp , v _Zn to obtain the voltage command value of the zero-phase voltage v _Zp . Output v _{Zp_ref} .

As shown in FIG. 8, the voltage and current suppressor 513 generates a signal (a negative polarity signal) in which the polarity of the signal with amplitude V _zpn /2 of the zero-phase voltages v _Zp and v _Zn inputted from the amplitude calculation unit 513FFd is inverted. ) and signals of command values of zero-phase voltages v _Zp and v _Zn inputted from zero-phase voltage calculating section 512FFb. The adder 513Fc performs an operation equivalent to subtracting the signal of the amplitude V _zpn /2 of the zero-sequence voltage v _Zp , v _Zn from the signal of the command value of the zero-sequence voltage v _Zp , v _Zn to obtain the zero-sequence voltage. A voltage command value _{vZn_ref} of _vZn is output.

By the way, depending on the system conditions, the value of the first term on the right side of equation (16) becomes too large, and when the injection ratio β is at the initial value (for example, 0.7), the power balancing control between the legs cannot keep up. There are cases. Here, the case where the control of power balancing between legs cannot keep up means that the seriousness of the loss failure, which will be described later, is 0.5 [p. u. ] is the case for severe system failure conditions. The exact value depends on the design specifications of the power converter as STATCOM, the type of system failure, the type of winding of the transformer installed between the system failure point and the power converter as STATCOM, etc. In that case, the power conversion device 1 is configured to recalculate and reset the optimal injection ratio β so that the power balancing control ability between the legs is maximized. Here, a method for calculating the optimum injection ratio β will be explained.

The control device 5 provided in the power converter 1 controls the circulating currents i _{cir_u} , i _{cir_v} , and i _{cir_w} to a maximum value determined from the heat generation upper limit value and the peak current upper limit value of the components constituting the main circuit section 3 . When Imax is reached, the injection ratio β is updated to the optimum value. As shown in Equation (17), by adjusting the second and third terms on the right side so that the left side becomes zero in Equation (16), the power between the legs generated by the three-phase unbalanced system condition can be calculated. Unbalanced conditions can be offset.

At the time when the circulating currents i _{cir_u} , i _{cir_v} , i _{cir_w} reach the maximum value Imax, equation (17) can be expressed as equation (18). The injection ratio β that satisfies equation (18) is the optimal value.

In this manner, the control device 5 controls the first zero-sequence power to be controlled based on the adjustment of the respective voltage components of the zero-sequence voltage _vZn of the lower neutral point 32n and the zero-sequence voltage _vZp of the upper neutral point 32p. and the injection ratio β with the second zero-phase power based on the adjustment of the circulating currents i _{cir_u} , i _{cir_v} , i _{cir_w} to the maximum voltage that the lower arms 31Un, 31Vn, 31Wn and the upper arms 31Up, 31Vp, 31Wp can output. based value (i.e. residual voltage Vmax) and the voltage at the connection part of AC reactors 312Un, 312Vn, 312Wn (an example of a first coil) and AC reactors 312Up, 312Vp, 312Wp (an example of a second coil) (i.e., a system voltage v _u , v _v , v _w ), the voltage component, and the voltage difference between the zero-sequence voltage v _Zn and the zero-sequence voltage v _Zp . The value based on the maximum voltage that can be output by the lower arms 31Un, 31Vn, 31Wn and the upper arms 31Up, 31Vp, 31Wp corresponds to the residual voltage Vmax shown on the right side of equations (17) and (18). The value based on the voltage at the connection portion of the AC reactors 312Un, 312Vn, 312Wn and the AC reactors 312Up, 312Vp, 312Wp corresponds to the power expressed by the first term on the right side of equations (17) and (18). The voltage component of the zero-sequence voltage v _Zn , _Zp corresponds to the effective value V _z of the zero-sequence voltage v _Zn , _Zp shown on the right side of equations (17) and (18). The voltage difference between the zero-sequence voltage v _Zn and the zero-sequence voltage v _Zp is the amplitude V _zpn of the difference between the DC voltage components of the zero-sequence voltages v _Zp and v _Zn , that is, on the right side of equations (17) and (18). This corresponds to "(1-β)Vmax" shown in FIG.

FIG. 9 is a block diagram showing an example of a schematic configuration of the arm voltage command value generation section 52 provided in the inter-leg power balancing control section 5a. In FIG. 9, for ease of understanding, the capacitor voltage balancing control section 51 connected to the arm voltage command value generation section 52, the current adjustment section 5b, the gate pulse signal generation section 5c, and the connection to the gate pulse signal generation section 5c are shown. A carrier wave generating section 5d is also shown.

As shown in FIG. 9, the arm voltage command value generation unit 52 generates an output current i Un of the U-phase lower arm 31 Un and an output current i _Un of the U-phase upper arm 31 _Up input from the capacitor voltage balancing control unit 51. It has an adding section 521u that adds up the respective current signals of _Up . Further, the arm voltage command value generation section 52 includes a subtraction section 522u that subtracts the addition signal output from the addition section 521u by half. The arm voltage command value generation unit 52 can calculate the circulating current i _{cir_u} circulating through the U-phase leg 31U at the current time using the addition unit 521u and the subtraction unit 522u. The addition unit 521u and the subtraction unit 522u are an example of a calculation unit that calculates the circulating current i _{cir_u} using the output current i _Un flowing to the U-phase lower arm 31Un and the output current i _Up flowing to the U-phase upper arm 31Up. Equivalent to. In this embodiment, the current value of the circulating current i _{cir_u} is half the sum of the current values of the output current i _Un flowing to the U-phase lower arm 31Un and the output current i _Up flowing to the U-phase upper arm 31Up. become.

The arm voltage command value generation unit 52 receives the circulating current i _{cir_u} output from the subtraction unit 522u and the addition unit 513Fa (see FIG. 8) provided in the voltage and current suppression unit 513 of the capacitor voltage balancing control unit 51. The adder 523u is provided with a signal obtained by inverting the polarity of the circulating current command value i _{cir_u_ref} . The adding unit 523u adds the current signal of the circulating current _{icir_u} and the signal of the circulating current command value i _{cir_u_ref} whose polarity is inverted, that is, subtracts the signal of the circulating current command value i _{cir_u_ref} from the current signal of the circulating current i _{cir_u} .

The arm voltage command value generation section 52 includes a P control section 524u connected to an addition section 523u. The P control section 524u is configured to perform proportional control on the signal input from the addition section 523u. The proportional calculation performed in the P control section 524u includes a parameter for converting the unit of the addition result in the addition section 523u from current to voltage. Thereby, the P control unit 524u can generate the arm voltage command correction value v _{u_cir_ref} for correcting the arm voltage command value v _{u_acr_ref} generated by the current adjustment unit 5b. The arm voltage command value v _{u_acr_ref} is a command value of a reactive voltage to be input/output between the U-phase AC power supply 211 and the U-phase leg 31U of the three-phase power system 2.

The configuration after the P control unit 524u of the arm voltage command value generation unit 52 in this embodiment is the same as the configuration after the P control unit 524u of the arm voltage command value generation unit 52 according to the first embodiment, so the description will be Omitted.

As shown in FIG. 9, the arm voltage command value generation unit 52 generates an output current _iVn of the V-phase lower arm 31Vn and an output current _iUp of the V-phase upper arm 31Vp input from the capacitor voltage balancing control unit 51. It has an adding section 521v that adds the respective current signals. Further, the arm voltage command value generation section 52 includes a subtraction section 522v that subtracts the addition signal output from the addition section 521v by half. The arm voltage command value generation unit 52 can calculate the circulating current i _{cir_v} circulating through the V-phase leg 31V at the current time using the addition unit 521v and the subtraction unit 522v. The adding unit 521v and the subtracting unit 522v calculate the circulating current i _{cir_v} using the output current i _Vn flowing to the lower arm 31Vn of the V-phase leg 31V and the output current i _Vp flowing to the upper arm 31Vp of the V-phase leg 31V. This corresponds to an example of the section. In this embodiment, the current value of the circulating current i _{cir_v} is the sum of the respective current values of the output current i _Vn flowing to the lower arm 31Vn of the V-phase leg 31V and the output current i _Vp flowing to the upper arm 31Vp of the V-phase leg 31V. will be half the value.

The arm voltage command value generation unit 52 receives the circulating current i _{cir_v} output from the subtraction unit 522v and the addition unit 513Fa (see FIG. 8) provided in the voltage and current suppression unit 513 of the capacitor voltage balancing control unit 51. The adder 523v is provided with a signal obtained by inverting the polarity of the circulating current command value i _{cir_v_ref} . The adding unit 523v adds the current signal of the circulating current i _{cir_v} and the signal of the circulating current command value i _{cir_v_ref} with the polarity inverted, that is, subtracts the signal of the circulating current command value i _{cir_v_ref} from the current signal of the circulating current i _{cir_v} .

The arm voltage command value generation section 52 has a P control section 524v connected to an addition section 523v. The P control section 524v is configured to perform proportional control on the signal input from the addition section 523v. The proportional calculation performed in the P control section 524v includes a parameter for converting the unit of the addition result in the addition section 523v from current to voltage. Thereby, the P control unit 524v can generate an arm voltage command correction value _{vv_cir_ref} for correcting the arm voltage command value _{vV_acr_ref} generated by the current adjustment unit 5b. The arm voltage command value v _{v_acr_ref} is a command value of a reactive voltage to be input/output between the V-phase AC power supply 212 and the V-phase leg 31V of the three-phase power system 2.

The configuration after the P control unit 524v of the arm voltage command value generation unit 52 in this embodiment is the same as the configuration after the P control unit 524v of the arm voltage command value generation unit 52 according to the first embodiment, so the description will be Omitted.

As shown in FIG. 9, the arm voltage command value generation unit 52 generates an output current iWn of the W-phase lower arm _31Wn and an output current _iWp of the W-phase upper arm 31Wp input from the capacitor voltage balancing control unit 51. It has an adding section 521w that adds the respective current signals. Further, the arm voltage command value generation section 52 includes a subtraction section 522w that subtracts the addition signal output from the addition section 521w by half. The arm voltage command value generation unit 52 can calculate the circulating current i _{cir_w} circulating through the W-phase leg 31W at the current time using the addition unit 521w and the subtraction unit 522w. The addition unit 521w and the subtraction unit 522w are an example of a calculation unit that calculates the circulating current i _{cir_w} using the output current i _Wn flowing to the W-phase lower arm 31Wn and the output current i _Wp flowing to the W-phase upper arm 31Wp. Equivalent to. In this embodiment, the current value of the circulating current i _{cir_w} is half the sum of the respective current values of the output current i _Wn flowing to the W-phase lower arm 31Wn and the output current i _Wp flowing to the W-phase upper arm 31Wp. become.

The arm voltage command value generation unit 52 receives the circulating current i _{cir_w} output from the subtraction unit 522w and the addition unit 513Fa (see FIG. 8) provided in the voltage and current suppression unit 513 of the capacitor voltage balancing control unit 51. The adder 523w receives a signal obtained by inverting the polarity of the circulating current command value i _{cir_w_ref} . The adding unit 523w adds the current signal of the circulating current _{icir_w} and the signal of the circulating current command value i _{cir_w_ref} whose polarity is inverted, that is, subtracts the signal of the circulating current command value i _{cir_w_ref} from the current signal of the circulating current i _{cir_w} .

The arm voltage command value generation section 52 includes a P control section 524w connected to an addition section 523w. The P control section 524w is configured to perform proportional control on the signal input from the addition section 523w. The proportional calculation performed in the P control section 524w includes a parameter for converting the unit of the addition result in the addition section 523w from current to voltage. Thereby, the P control unit 524w can generate the arm voltage command correction value v _{w_cir_ref} for correcting the arm voltage command value v _{w_acr_ref} generated by the current adjustment unit 5b. The arm voltage command value v _{w_acr_ref} is a command value of a reactive voltage to be input/output between the W-phase AC power supply 213 and the W-phase leg 31W of the three-phase power system 2.

The configuration after the P control unit 524w of the arm voltage command value generation unit 52 in this embodiment is the same as the configuration after the P control unit 524w of the arm voltage command value generation unit 52 according to the first embodiment, so the description will be Omitted.

In this way, the arm voltage command value generation unit 52 in this embodiment generates the arm voltage command values v Un_ref , _{Vn_ref} based on the circulating current command values i _{cir_u_ref} , i _{cir_v_ref} , i _{cir_w_ref} and the voltage command values v _{Zp_ref} , _{v Zn_ref .} , _{Wn_ref} . Thereby, the arm voltage command value generation unit 52 adjusts the circulating currents i _{cir_u} , i _{cir_v} , i _{cir_w} and the zero-phase voltages v _Zp , v _Zn to suppress the unbalanced state of the capacitor C1, and the inflow power Δp _{_U} , The balance between Δp _{_V} and Δp _{_W} can be controlled.

As described above, in addition to the configuration of the power converter 1 according to the first embodiment, the power converter 1 according to the present embodiment has a zero-sequence voltage v _Zn at the lower neutral point 32n and the upper neutral point 32p. and the zero-sequence voltage v _Zp , and at least one of the circulating current i _{u_cir} flowing in the U-phase leg 31U, the circulating current i _{v_cir} flowing in the V-phase leg 31V, and the circulating current i _{w_cir} flowing in the W-phase leg 31W. It includes an inter-leg power balancing control section 5a that can control second zero-phase power (an example of second power).

Thereby, the power conversion device 1 according to this embodiment can obtain the same effects as the power conversion device 1 according to the first embodiment. Furthermore, the power conversion device 1 according to the present embodiment can also use circulating currents i _{cir_u} , i _{cir_v} , i _{cir_w} in order to control the balance of the inflow powers Δp _{_U} , Δp _{_V} , Δp _{_W} .

(Effects of the power conversion device according to the first embodiment and the second embodiment)
Next, effects of the power converter devices according to the first embodiment and the second embodiment will be explained using FIGS. 10 to 12. FIG. 10 shows the reactive power at the time of a grid failure when the power conversion device according to the first embodiment described above uses a method similar to that of the power converter according to the first embodiment, that is, when the injected power based on the zero-sequence voltage is injected to control the power unbalanced state between the legs. It is a graph showing the simulation result of the maximum value. FIG. 11 shows a method similar to that of the power converter according to the second embodiment, that is, injecting power based on the zero-sequence voltage and injecting power based on the voltage difference between the circulating current and the zero-sequence voltage to eliminate power imbalance between legs. It is a graph which shows the simulation result of the maximum value of reactive power at the time of a system failure when an equilibrium state is controlled. As a reference example, Figure 12 shows the simulation results of the maximum value of reactive power in the event of a grid failure when the power imbalance between legs is controlled by injecting power based on the voltage difference between circulating current and zero-sequence voltage. This is a graph showing.

The horizontal axes of the graphs shown in FIGS. 10 to 12 indicate the severity of system failure (Voltage Dip Severity) [p. u. ], and the vertical axis of the graph represents the reactive current [p. u. ] represents. The degree of severity of a grid failure indicates that the closer it is to "1", the smaller the grid voltage drop caused by the grid short circuit fault, and the closer it is to "0", the larger the grid voltage drop. A curve L1 connecting the triangle marks shown in FIG. 10 represents the characteristic of the maximum value of reactive power at the time of a one-phase ground fault system failure. A straight line L2 connecting the circles shown in FIG. 10 represents the characteristic of the maximum value of reactive power at the time of a two-phase short-circuit system failure. A straight line L3 connecting the cross marks shown in FIG. 10 represents the characteristic of the maximum value of reactive power at the time of a two-phase ground fault system failure. A curve L4 connecting the triangle marks shown in FIG. 11 represents the characteristic of the maximum value of reactive power at the time of a one-phase ground fault system failure. A straight line L5 connecting the circles shown in FIG. 11 represents the characteristic of the maximum value of reactive power at the time of a two-phase short-circuit system failure. A straight line L6 connecting the cross marks shown in FIG. 11 represents the characteristic of the maximum value of reactive power at the time of a two-phase ground fault system failure. A curve L7 connecting the triangle marks shown in FIG. 12 represents the characteristic of the maximum value of reactive power at the time of a one-phase ground fault system failure. A curve L8 connecting the circles shown in FIG. 12 represents the characteristic of the maximum value of reactive power at the time of a two-phase short-circuit system failure. A curve L9 connecting the cross marks shown in FIG. 12 represents the characteristic of the maximum value of reactive power at the time of a two-phase ground fault system failure.

10 to 12, the vertical axis represents the reactive current [p. u. ] However, since reactive power is proportional to reactive current, the vertical axis is equivalent to representing reactive power. Furthermore, the graphs shown in FIGS. 10 to 12 are simulation results assuming a STATCOM with a rating of 80 MVar for large-scale offshore power plants.

As shown in FIG. 10, when the capacitor equilibrium state control (balance control) method in the power converter according to the first embodiment is applied, two-phase short circuit (see straight line L2) and two-phase ground fault (see straight line L3) occur. Under these conditions, the reactive power reaches its maximum value regardless of the severity of the system failure, so the rated reactive power can be output. However, if the capacitor equilibrium state control (balance control) method in the power converter according to the first embodiment is applied, the seriousness of the system failure is smaller than 0.4 under the condition of one-phase ground fault (see straight line L1). Since the reactive current drops sharply within this range, the reactive power that can be output also drops sharply. Therefore, the capacitor balance state control (balance control) method in the power conversion device according to the first embodiment is a method that is more effective against two-phase short circuits and two-phase ground faults than one-phase ground faults.

As shown in FIG. 11, when the capacitor equilibrium state control (balance control) method in the power converter according to the second embodiment is applied, two-phase short circuit (see straight line L5) and two-phase ground fault (see straight line L6) occur. Under these conditions, since the injected power based on the zero-sequence voltage is mainly used, the reactive power reaches its maximum value and the rated reactive power can be output regardless of the severity of the system failure. Moreover, when the capacitor balance state control (balance control) method in the power converter according to the second embodiment is applied, under the condition of one-phase ground fault (see straight line L4), injection based on the voltage difference between the circulating current and the zero-sequence voltage Electric power can also be injected. Therefore, when this method is applied, the reactive current does not drop sharply in a range where the seriousness of the system failure is less than 0.4, so the reactive power that can be output also does not drop sharply. As a result, when this method is applied, even in the case where the severity of the system failure is the highest, the output of reactive power of about 70% of the rated reactive current can be maintained.

When the capacitor balance state control (balance control) method according to the reference example is applied, the condition of 1-phase ground fault (see curve L7), 2-phase short circuit (see curve L8), and 2-phase ground fault (see curve L9) However, since the reactive current decreases in a range where the severity of the system failure is smaller than a predetermined value, the reactive power that can be output also decreases. Therefore, the balanced state control (balance control) method according to the reference example has a problem in that the rated reactive power cannot be maintained in response to any system failure. Furthermore, since the capacitor equilibrium state control (balance control) method according to the reference example uses a circulating current, there is also a problem that a loss occurs due to the circulating current when controlling the capacitor equilibrium state.

The capacitor balanced state control (balance control) method in the power converter according to the first embodiment can maintain the rated reactive power against system failures such as two-phase short circuit and two-phase ground fault. Therefore, the method according to the first embodiment is superior to the method according to the reference example with respect to system failures such as two-phase short circuits and two-phase ground faults.

The capacitor balanced state control (balance control) method in the power converter according to the first embodiment can maintain the rated reactive power against system failures such as two-phase short circuit and two-phase ground fault. Furthermore, the capacitor equilibrium state control (balance control) method in the power converter according to the second embodiment suppresses a decrease in the rated reactive power by resetting the injection ratio β in the case of a one-phase ground fault system failure. can. Therefore, the method according to the second embodiment is superior to the method according to the reference example with respect to system failures.

[Third embodiment]
A power conversion device according to a third embodiment of the present invention will be described using FIG. 13. The power conversion device according to this embodiment is characterized in that the remaining capacity of a secondary battery provided as a power storage element is controlled to suppress the output power difference between the upper and lower arms within a predetermined range. The power converter according to the present embodiment has the same general configuration as the power converter according to the first embodiment, except that the configuration of the power converter circuit cell is different. Hereinafter, in the description of the power conversion device according to the present embodiment, reference will be made to FIG. Explanation will be omitted.

As shown in FIG. 13, the power storage element provided in the power conversion circuit cell 311Uni (i is a natural number from 1 to x) of the lower arm 31Un of the U-phase leg 31U is connected in parallel to the capacitor C2. It has a secondary battery 314. Further, the power conversion circuit cell 311Uni has a battery management system (BMS) 315 that detects the remaining capacity (State-Of-Charge: SOC) of the secondary battery 314. The battery management system 315 is connected to the control device 5. Information on the remaining capacity of the secondary battery 314 detected by the battery management system 315 is transmitted to the control device 5.

Similarly, the power storage element provided in the power conversion circuit cell 311Upi (i is a natural number from 1 to x) of the upper arm 31Up of the U-phase leg 31U is connected in parallel to the capacitor C2 and the two semiconductor switches Qa and Qb. It has a connected secondary battery 314. Further, the power conversion circuit cell 311Upi includes a battery management system 315 that detects the remaining capacity of the secondary battery 314. The battery management system 315 is connected to the control device 5. Information on the remaining capacity of the secondary battery 314 detected by the battery management system 315 is transmitted to the control device 5.

Although not shown, the power conversion circuit cells provided in each of the lower arm 31Vn and upper arm 31Vp of the V-phase leg 31V and the lower arm 31Wn and upper arm 31Wp of the W-phase leg 31W also have two capacitors C2 and C2. It has a secondary battery 314 connected in parallel to the semiconductor switches Qa and Qb, and a battery management system 315 that detects the remaining capacity of the secondary battery 314.

The voltage between both electrodes of capacitor C2 is determined by the voltage across secondary battery 314. Therefore, the power conversion device according to this embodiment does not need to output the DC voltage between both electrodes of the capacitor C2 to the control device 5. The power conversion device according to the present embodiment is configured to transmit information on the remaining capacity of the secondary battery 314 detected by the battery management system 315 to the control device 5 instead of the DC voltage between both electrodes of the capacitor C2. There is. The control device 5 is configured to be able to suppress the difference in remaining capacity of the secondary battery 314 of the power conversion circuit cell inputted from the battery management system 315.

The inter-leg power balancing control unit (an example of a power control unit) provided in the control device 5 balances the remaining capacity of the secondary battery 314 provided in the U-phase lower arm 31Uni and the remaining capacity of the secondary battery 314 provided in the U-phase upper arm 31Upi. It is configured to detect the difference in remaining capacity of the secondary battery 314. The inter-leg power balancing control unit also calculates the difference between the remaining capacity of the secondary battery 314 provided in the V-phase lower arm 31Vni and the remaining capacity of the secondary battery 314 provided in the V-phase upper arm 31Vpi. Configured to detect. Furthermore, the inter-leg power balancing control section calculates the difference between the remaining capacity of the secondary battery 314 provided in the W-phase lower arm 31Wni and the remaining capacity of the secondary battery 314 provided in the W-phase upper arm 31Wpi. Configured to detect.

The inter-leg power balancing control section is configured to be able to convert the detected remaining capacity of the secondary battery 314 into voltage. The inter-leg power balancing control section can perform the same operation as the inter-leg power balancing control section 5a provided in the power converter according to the first embodiment and the second embodiment using the converted voltage. Become. As a result, the power conversion device according to the present embodiment performs the same operation as the power conversion device according to the first embodiment or the second embodiment, so that the capacitor voltage average difference values between the legs Δv _{C_U} , Δv _{C_V} , Δv _{C_W} can be kept within a predetermined range.

As a result, the power conversion device according to this embodiment can obtain the same effects as the power conversion devices according to the first and second embodiments. Further, the power conversion device according to the present embodiment includes the secondary battery 314 in parallel with the capacitor C2, so that the surge voltage can be suppressed by the capacitor C2, and active power can be compensated for a longer period of time.

The present invention is not limited to the above-described embodiments, and various modifications are possible.
Although the power conversion devices 1 according to the first to third embodiments are configured to detect the voltage of the capacitor C1 as an amount equivalent to the stored energy, the present invention is not limited to this. For example, even if the power conversion device 1 detects the stored energy stored in the capacitor C1 and performs control so that the detected stored energy is balanced, the power conversion device 1 according to the first embodiment to the third embodiment described above may The same effects as the power conversion device 1 can be obtained.

Although the power conversion device 1 according to the first to third embodiments includes a plurality of power conversion circuit cells each having four semiconductor switches, the present invention is not limited thereto. For example, the same effect can be obtained even if the power conversion device includes a plurality of power conversion circuit cells each having two semiconductor switches connected in series.

Although the power conversion device 1 according to the first embodiment to the third embodiment has semiconductor switches Qa, Qb, Qc, and Qd configured with IGBTs, the present invention is not limited thereto. The power conversion device 1 includes, for example, a gate turn-off thyristor (GTO), an integrated gate commutated turn-off thyristor (GCT), or a MOS field effect transistor (Metal). -Oxide -Semiconductor Field-Effect Transistor) or the like.

In the power conversion devices according to the first embodiment and the second embodiment, the capacitance of the capacitor C1 may be designed to be larger than the capacitance required to balance the power between the upper and lower arms. In this case, the power conversion device can supply active power to the load of the power system for a short time even if the power system experiences a momentary power outage, for example.

The scope of the invention is not limited to the exemplary embodiments shown and described, but also includes all embodiments which give equivalent effects to the object of the invention. Furthermore, the scope of the invention is not limited to the combinations of inventive features delineated by the claims, but may be delimited by any desired combinations of specific features of each and every disclosed feature. sell.

1 Power conversion device 2 Three-phase power system 3 Main circuit section 5 Control device 5a Inter-leg power balancing control section 5b Current adjustment section 5c Gate pulse signal generation section 5d Carrier wave generation section 21 Three-phase AC power supply 22 Cable 31U U-phase leg 31Un, 31Vn, 31Wn Lower arm 31Up, 31Vp, 31Wp Upper arm 31Ut, 31Vt, 31Wt, T1, T2 Terminal 31V V phase leg 31W W phase leg 32n Lower neutral point 32p Upper neutral point 51 Capacitor voltage balancing control section 52 Arm voltage command value generation unit 211 U-phase AC power supply 212 V-phase AC power supply 213 W-phase AC power supply 221 U-phase cable 222 V-phase cable 223 W-phase cable 311Un1, 311Uni, 311Uni-1, 311Unx, 311Up, 311Up1, 311Upi, 311Upi-1, 311Upx, 311Vn1, 311Vni, 311Vnx, 311Vp, 311Vp1, 311Vpi, 311Wn1, 311Wni, 311Wnx, 311Wp, 311Wp1, 311Wpi Power conversion circuit cell 312Un, 312Up, 312Vn, 3 12Vp, 312Wn, 312Wp AC reactor 313 Voltage detection section 314 Secondary battery 315 Battery management system 511 Capacitor voltage average difference detection unit 512 Voltage suppression unit 513 Voltage and current suppression unit 512F, 512FBb, 512FBg, 512FBj, 513Fa, 513Fb, 513Fc, 521u, 521v, 521w, 523u, 523v, 523w Addition Sections 512FB, 513FB Feedback sections 512FBa, 512FBf Low-pass filters 512FBc, 512FBh PI control sections 512FBd, 513FFd Amplitude calculation sections 512FBe, 512FFa, 513FBe, 513FFf Division sections 512FBi, 513FBi Phase difference calculation section 512F Bi-1, 513FBi-1 Arithmetic unit 512FBi-2, 513FBi-2 Calculation unit 512FBk, 512FFb Zero-phase voltage calculation unit 512FF, 513FF Feedforward unit 513 Voltage and current suppression unit 513FBk, 513FFg Circulating current calculation unit 513FFb Upper limit restriction unit 513FFe Amplification unit 522u, 522v, 522w Subtraction unit 52 4u , 524v, 524w P control section 525u, 525v, 525w First addition section 526u, 526v, 526w Second addition section 527u, 527v, 527w First calculation section 528u, 528v, 528w Second calculation section C1, C2 Capacitors Da, Db , Dc, Dd Freewheeling diode Ma, Mb, Mc, Md Semiconductor module PS Power control system Qa, Qb, Qc, Qd Semiconductor switch

Claims (10)

a plurality of legs each having a first arm and a second arm connected in series;
a first connection portion in which the ends of the first arm provided on each of the plurality of legs that are not connected to the second arm are connected to each other;
a second connection part in which the ends of the second arm provided on each of the plurality of legs, which are not connected to the first arm, are connected to each other;
a control device that controls the plurality of legs;
The first arm is connected in series to a first power inverter circuit cell having two semiconductor switches connected in series and a power storage element connected in parallel to the two semiconductor switches, and the first power inverter circuit cell. a first coil,
The second arm is connected in series to a second power inverter circuit cell having two semiconductor switches connected in series and a power storage element connected in parallel to the two semiconductor switches, and the second power inverter circuit cell. and a second coil,
The control device adjusts the same voltage component contained in each of the first voltage of the first connection part and the second voltage of the second connection part to cause the same voltage component to flow in and out between each of the plurality of legs. A power conversion device having a power control unit that controls power. The power conversion device according to claim 1, wherein the first power is power generated by a current flowing between the plurality of legs and a power system connected to each of the plurality of legs and the voltage component. comprising a detection unit that detects the accumulated energy of the electricity storage element or an amount equivalent to the accumulated energy,
The power conversion device according to claim 1 , wherein the power control unit includes an adjustment unit that adjusts the voltage component according to a detection value detected by the detection unit. The power conversion device according to claim 3, wherein the power storage element includes a capacitor. The power conversion device according to claim 4, wherein the detection unit detects the voltage of the capacitor as the corresponding amount. The power conversion device according to claim 4 or 5, wherein the power control unit adjusts the first power of the plurality of legs so as to suppress an unbalanced state of power between each of the plurality of legs. The power control unit controls the second power by adjusting at least one of a voltage difference between the first voltage and the second voltage and a circulating current flowing through each of the plurality of legs. The power conversion device according to any one of the items. The power conversion device according to claim 7, wherein the power control section includes a calculation section that calculates the circulating current using a current flowing through the first arm and a current flowing through the second arm. The control device is configured such that the first arm and the second arm can output an injection ratio between the first power that is controlled based on the adjustment of the voltage component and the second power that is controlled based on the adjustment of the circulating current. The electric power according to claim 7 or 8, wherein the electric power is adjusted based on a value based on a maximum voltage, a value based on a voltage at a connection portion of the first coil and the second coil, the voltage component, and the voltage difference. conversion device. The power storage element has a secondary battery connected in parallel to the two semiconductor switches,
Any one of claims 1 to 9, wherein the power control unit detects a difference between the remaining capacity of the secondary battery provided in the first arm and the remaining capacity of the secondary battery provided in the second arm. The power conversion device according to item 1.

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